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Merge branch 'master' into xvmc-i915

This commit is contained in:
Zhenyu Wang 2007-08-10 16:45:56 +08:00
parent 105f8a183e 7b143e5c83
commit 02ad9cee33
20 changed files with 414 additions and 221 deletions
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10
configure.ac
View File

@ -26,16 +26,6 @@ AC_INIT([xf86-video-intel],
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-intel)
AC_DEFINE_UNQUOTED([INTEL_VERSION_MAJOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^\([[0-9]]*\)\.[[0-9]]*\.[[0-9]]*/\1/')],
[Major version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_MINOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]*\.\([[0-9]]*\)\.[[0-9]]*/\1/')],
[Minor version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_PATCH],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]*\.[[0-9]]*\.\([[0-9]]*\)/\1/')],
[Patch version])
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
AC_CONFIG_AUX_DIR(.)

2
man/intel.man
View File

@ -141,7 +141,7 @@ and that is used with the 3D driver in Mesa from version 6.5.2 and
upwards. If the size is set too high to make room for pre-allocated
VideoRam, the driver will try to reduce it automatically. If you use only
older Mesa or DRM versions, you may set this value to zero, and
atctivate the legacy texture pool (see
activate the legacy texture pool (see
.B "Option \*qLegacy3D\*q"
). If you run 3D programs with large texture memory requirements, you might
gain some performance by increasing this value.

1
src/Makefile.am
View File

@ -92,6 +92,7 @@ intel_drv_la_SOURCES = \
i830_debug.h \
i830_display.c \
i830_display.h \
i830_quirks.c \
i830_driver.c \
i830_dvo.c \
i830.h \

3
src/bios_reader/bios_dumper.c
View File

@ -29,6 +29,7 @@
#include <stdlib.h>
#include <string.h>
#include <stdarg.h>
#include <sys/stat.h>
#include <fcntl.h>
#include <errno.h>
#include <pciaccess.h>
@ -80,7 +81,7 @@ int main(int argc, char **argv)
exit(1);
}
fd = open(argv[1], O_RDWR | O_CREAT | O_TRUNC);
fd = open(argv[1], O_RDWR | O_CREAT | O_TRUNC, DEFFILEMODE);
if (fd < 0) {
fprintf(stderr, "Couldn't open output: %s\n", strerror(errno));
exit(1);

12
src/common.h
View File

@ -331,10 +331,14 @@ extern int I810_DEBUG;
#ifndef PCI_CHIP_I945_GM
#define PCI_CHIP_I945_GM 0x27A2
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
#endif
#ifndef PCI_CHIP_I945_GME
#define PCI_CHIP_I945_GME 0x27AE
#define PCI_CHIP_I945_GME_BRIDGE 0x27AC
#endif
#ifndef PCI_CHIP_I965_G_1
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
@ -357,10 +361,14 @@ extern int I810_DEBUG;
#ifndef PCI_CHIP_I965_GM
#define PCI_CHIP_I965_GM 0x2A02
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_I965_GM_BRIDGE 0x2A00
#endif
#ifndef PCI_CHIP_I965_GME
#define PCI_CHIP_I965_GME 0x2A12
#define PCI_CHIP_I965_GME_BRIDGE 0x2A10
#endif
#ifndef PCI_CHIP_G33_G
#define PCI_CHIP_G33_G 0x29C2
#define PCI_CHIP_G33_G_BRIDGE 0x29C0

4
src/i810.h
View File

@ -66,6 +66,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I810_DRIVER_NAME "intel"
#define I810_LEGACY_DRIVER_NAME "i810"
#define INTEL_VERSION_MAJOR PACKAGE_VERSION_MAJOR
#define INTEL_VERSION_MINOR PACKAGE_VERSION_MINOR
#define INTEL_VERSION_PATCH PACKAGE_VERSION_PATCHLEVEL
/* HWMC Surfaces */
#define I810_MAX_SURFACES 7
#define I810_MAX_SUBPICTURES 2

12
src/i810_reg.h
View File

@ -822,6 +822,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
# define PP_SEQUENCE_MASK 0x30000000
#define PP_CONTROL 0x61204
# define POWER_DOWN_ON_RESET (1 << 1)
# define POWER_TARGET_ON (1 << 0)
#define LVDSPP_ON 0x61208
@ -1066,6 +1067,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BLC_PWM_CTL 0x61254
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
#define BACKLIGHT_MODULATION_FREQ_SHIFT2 (16)
/**
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
@ -1073,7 +1075,9 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
* The actual value is this field multiplied by two.
*/
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
#define BACKLIGHT_MODULATION_FREQ_MASK2 (0xffff << 16)
#define BLM_LEGACY_MODE (1 << 16)
/**
* This is the number of cycles out of the backlight modulation cycle for which
* the backlight is on.
@ -1084,6 +1088,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)
/* On 965+ backlight control is in another register */
#define BLC_PWM_CTL2 0x61250
#define BLM_LEGACY_MODE2 (1 << 30)
#define BLM_CTL 0x61260
#define BLM_THRESHOLD_0 0x61270
#define BLM_THRESHOLD_1 0x61274
@ -2021,6 +2029,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DSPBCNTR 0x71180
#define DISPLAY_PLANE_ENABLE (1<<31)
#define DISPLAY_PLANE_DISABLE 0
#define DISPLAY_PLANE_TILED (1<<10)
#define DISPPLANE_GAMMA_ENABLE (1<<30)
#define DISPPLANE_GAMMA_DISABLE 0
#define DISPPLANE_PIXFORMAT_MASK (0xf<<26)
@ -2160,12 +2169,15 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define XY_COLOR_BLT_CMD ((2<<29)|(0x50<<22)|(0x4))
#define XY_COLOR_BLT_WRITE_ALPHA (1<<21)
#define XY_COLOR_BLT_WRITE_RGB (1<<20)
#define XY_COLOR_BLT_TILED (1<<11)
#define XY_SETUP_CLIP_BLT_CMD ((2<<29)|(3<<22)|1)
#define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6)
#define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21)
#define XY_SRC_COPY_BLT_WRITE_RGB (1<<20)
#define XY_SRC_COPY_BLT_SRC_TILED (1<<15)
#define XY_SRC_COPY_BLT_DST_TILED (1<<11)
#define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|0x4)
#define SRC_COPY_BLT_WRITE_ALPHA (1<<21)

11
src/i830.h
View File

@ -411,9 +411,8 @@ typedef struct _I830Rec {
CloseScreenProcPtr CloseScreen;
#ifdef I830_USE_EXA
unsigned int copy_src_pitch;
unsigned int copy_src_off;
ExaDriverPtr EXADriverPtr;
PixmapPtr pSrcPixmap;
#endif
I830WriteIndexedByteFunc writeControl;
@ -538,6 +537,7 @@ typedef struct _I830Rec {
CARD32 savePaletteB[256];
CARD32 saveSWF[17];
CARD32 saveBLC_PWM_CTL;
CARD32 saveBLC_PWM_CTL2;
CARD32 saveFBC_CFB_BASE;
CARD32 saveFBC_LL_BASE;
CARD32 saveFBC_CONTROL2;
@ -547,6 +547,7 @@ typedef struct _I830Rec {
/** Enables logging of debug output related to mode switching. */
Bool debug_modes;
unsigned int quirk_flag;
} I830Rec;
#define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
@ -762,4 +763,10 @@ extern const int I830CopyROP[16];
#define _845_DRAM_RW_CONTROL 0x90
#define DRAM_WRITE 0x33330000
/* quirk flag definition */
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
extern void i830_fixup_devices(ScrnInfoPtr);
#endif /* _I830_H_ */

3
src/i830_bios.h
View File

@ -130,9 +130,6 @@ struct aimdb_block {
CARD16 aimdb_size;
} __attribute__((packed));
struct vch_bdb_20 {
} __attribute__((packed));
struct vch_panel_data {
CARD16 fp_timing_offset;
CARD8 fp_timing_size;

234
src/i830_display.c
View File

@ -498,6 +498,123 @@ i830_pipe_a_require_deactivate (ScrnInfoPtr scrn)
return;
}
static Bool
i830_use_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
if (!pI830->fb_compression)
return FALSE;
/* Pre-965 only supports plane A */
if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
return FALSE;
/* Need 15, 16, or 32 (w/alpha) pixel format */
if (!(pScrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */
pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
return FALSE;
/*
* No checks for pixel multiply, incl. horizontal, or interlaced modes
* since they're currently unused.
*/
return TRUE;
}
/*
* Several restrictions:
* - DSP[AB]CNTR - no line duplication && no pixel multiplier
* - pixel format == 15 bit, 16 bit, or 32 bit xRGB_8888
* - no alpha buffer discard
* - no dual wide display
* - progressive mode only (DSP[AB]CNTR)
* - uncompressed fb is <= 2048 in width, 0 mod 8
* - uncompressed fb is <= 1536 in height, 0 mod 2
* - SR display watermarks must be equal between 16bpp and 32bpp?
*
* FIXME: verify above conditions are true
*/
static void
i830_enable_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
uint32_t fbc_ctl = 0;
unsigned long compressed_stride;
int pipe = intel_crtc->pipe;
/* FIXME: plane & pipe might not always be equal */
int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
unsigned long uncompressed_stride = pScrn->displayWidth * pI830->cpp;
unsigned long interval = 1000;
if (INREG(FBC_CONTROL) & FBC_CTL_EN) {
char cur_pipe = (INREG(FBC_CONTROL2) & 1) ? 'b' : 'a';
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "fbc already enabled on "
"pipe %c, not enabling on pipe %c\n", cur_pipe, pipe ? 'b' :
'a');
return;
}
compressed_stride = pI830->compressed_front_buffer->size /
FBC_LL_SIZE;
if (uncompressed_stride < compressed_stride)
compressed_stride = uncompressed_stride;
/* FBC_CTL wants 64B units */
compressed_stride = (compressed_stride / 64) - 1;
/* Set it up... */
/* Wait for compressing bit to clear */
while (INREG(FBC_STATUS) & FBC_STAT_COMPRESSING)
; /* nothing */
i830WaitForVblank(pScrn);
OUTREG(FBC_CFB_BASE, pI830->compressed_front_buffer->bus_addr);
OUTREG(FBC_LL_BASE, pI830->compressed_ll_buffer->bus_addr + 6);
OUTREG(FBC_CONTROL2, FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_FULL |
FBC_CTL_CPU_FENCE | plane);
/* Zero buffers */
memset(pI830->FbBase + pI830->compressed_front_buffer->offset, 0,
pI830->compressed_front_buffer->size);
memset(pI830->FbBase + pI830->compressed_ll_buffer->offset, 0,
pI830->compressed_ll_buffer->size);
/* enable it... */
fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT;
fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
fbc_ctl |= FBC_CTL_UNCOMPRESSIBLE;
OUTREG(FBC_CONTROL, fbc_ctl);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc enabled on plane %c\n", pipe ?
'b' : 'a');
}
static void
i830_disable_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t fbc_ctl;
char pipe = (INREG(FBC_CONTROL2) & 1) ? 'b' : 'a';
/* Disable compression */
fbc_ctl = INREG(FBC_CONTROL);
fbc_ctl &= ~FBC_CTL_EN;
OUTREG(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
while (INREG(FBC_STATUS) & FBC_STAT_COMPRESSING)
; /* nothing */
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc disabled on pipe %c\n", pipe);
}
/**
* Sets the power management mode of the pipe and plane.
@ -561,8 +678,16 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
/* Give the overlay scaler a chance to enable if it's on this pipe */
i830_crtc_dpms_video(crtc, TRUE);
/* Reenable compression if needed */
if (i830_use_fb_compression(crtc))
i830_enable_fb_compression(crtc);
break;
case DPMSModeOff:
/* Shut off compression if in use */
if (i830_use_fb_compression(crtc))
i830_disable_fb_compression(crtc);
/* Give the overlay scaler a chance to disable if it's on this pipe */
i830_crtc_dpms_video(crtc, FALSE);
@ -656,112 +781,6 @@ i830_crtc_unlock (xf86CrtcPtr crtc)
#endif
}
static Bool
i830_use_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
if (!pI830->fb_compression)
return FALSE;
/* Pre-965 only supports plane A */
if (!IS_I965GM(pI830) && plane != FBC_CTL_PLANEA)
return FALSE;
/* Need 15, 16, or 32 (w/alpha) pixel format */
if (!(pScrn->bitsPerPixel == 16 || /* covers 15 bit mode as well */
pScrn->bitsPerPixel == 32)) /* mode_set dtrt if fbc is in use */
return FALSE;
/*
* No checks for pixel multiply, incl. horizontal, or interlaced modes
* since they're currently unused.
*/
return TRUE;
}
/*
* Several restrictions:
* - DSP[AB]CNTR - no line duplication && no pixel multiplier
* - pixel format == 15 bit, 16 bit, or 32 bit xRGB_8888
* - no alpha buffer discard
* - no dual wide display
* - progressive mode only (DSP[AB]CNTR)
* - uncompressed fb is <= 2048 in width, 0 mod 8
* - uncompressed fb is <= 1536 in height, 0 mod 2
* - SR display watermarks must be equal between 16bpp and 32bpp?
*
* FIXME: verify above conditions are true
*/
static void
i830_enable_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
uint32_t fbc_ctl;
unsigned long compressed_stride;
int pipe = intel_crtc->pipe;
int plane = (pipe == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB);
unsigned long uncompressed_stride = pScrn->displayWidth * pI830->cpp;
unsigned long interval = 1000;
if (INREG(FBC_CONTROL) & FBC_CTL_EN) {
char cur_pipe = (INREG(FBC_CONTROL2) & 1) ? 'b' : 'a';
xf86DrvMsg(pScrn->scrnIndex, X_WARNING, "fbc already enabled on "
"pipe %c, not enabling on pipe %c\n", cur_pipe, pipe ? 'b' :
'a');
return;
}
compressed_stride = pI830->compressed_front_buffer->size /
FBC_LL_SIZE;
if (uncompressed_stride < compressed_stride)
compressed_stride = uncompressed_stride;
/* FBC_CTL wants 64B units */
compressed_stride = (compressed_stride / 64) - 1;
/* Set it up... */
OUTREG(FBC_CFB_BASE, pI830->compressed_front_buffer->bus_addr);
OUTREG(FBC_LL_BASE, pI830->compressed_ll_buffer->bus_addr + FBC_LL_PAD);
OUTREG(FBC_CONTROL2, FBC_CTL_CPU_FENCE | plane);
/* enable it... */
fbc_ctl = INREG(FBC_CONTROL);
fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC;
fbc_ctl |= (compressed_stride & 0xff) << FBC_CTL_STRIDE_SHIFT;
fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
OUTREG(FBC_CONTROL, fbc_ctl);
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc enabled on pipe %c\n", pipe ?
'b' : 'a');
}
static void
i830_disable_fb_compression(xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t fbc_ctl;
char pipe = (INREG(FBC_CONTROL2) & 1) ? 'b' : 'a';
/* Disable compression */
fbc_ctl = INREG(FBC_CONTROL);
fbc_ctl &= ~FBC_CTL_EN;
OUTREG(FBC_CONTROL, fbc_ctl);
/* Wait for compressing bit to clear */
while (INREG(FBC_STATUS) & FBC_STAT_COMPRESSING)
; /* nothing */
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "fbc disabled on pipe %c\n", pipe);
}
static void
i830_crtc_prepare (xf86CrtcPtr crtc)
{
@ -1059,6 +1078,9 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
else
dspcntr |= DISPPLANE_SEL_PIPE_B;
if (pI830->tiling)
dspcntr |= DISPLAY_PLANE_TILED;
pipeconf = INREG(pipeconf_reg);
if (pipe == 0 && !IS_I965G(pI830))
{

3
src/i830_driver.c
View File

@ -1192,6 +1192,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
(unsigned long)pI830->MMIOAddr);
/* check quirks */
i830_fixup_devices(pScrn);
/* Allocate an xf86CrtcConfig */
xf86CrtcConfigInit (pScrn, &i830_xf86crtc_config_funcs);
xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);

106
src/i830_exa.c
View File

@ -54,7 +54,7 @@ do { \
#define I830FALLBACK(s, arg...) \
do { \
return FALSE; \
} while(0)
} while(0)
#endif
const int I830CopyROP[16] =
@ -97,6 +97,21 @@ const int I830PatternROP[16] =
ROP_1
};
static Bool
exaPixmapTiled(PixmapPtr p)
{
ScreenPtr pScreen = p->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
if (!pI830->tiling)
return FALSE;
if (p == pScreen->GetScreenPixmap(pScreen))
return TRUE;
return FALSE;
}
/**
* I830EXASync - wait for a command to finish
* @pScreen: current screen
@ -133,12 +148,12 @@ I830EXAPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
offset = exaGetPixmapOffset(pPixmap);
pitch = exaGetPixmapPitch(pPixmap);
if ( offset % pI830->EXADriverPtr->pixmapOffsetAlign != 0)
if (offset % pI830->EXADriverPtr->pixmapOffsetAlign != 0)
I830FALLBACK("pixmap offset not aligned");
if ( pitch % pI830->EXADriverPtr->pixmapPitchAlign != 0)
if (pitch % pI830->EXADriverPtr->pixmapPitchAlign != 0)
I830FALLBACK("pixmap pitch not aligned");
pI830->BR[13] = (pitch & 0xffff);
pI830->BR[13] = (I830PatternROP[alu] & 0xff) << 16 ;
switch (pPixmap->drawable.bitsPerPixel) {
case 8:
break;
@ -151,7 +166,6 @@ I830EXAPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
pI830->BR[13] |= ((1 << 24) | (1 << 25));
break;
}
pI830->BR[13] |= (I830PatternROP[alu] & 0xff) << 16 ;
pI830->BR[16] = fg;
return TRUE;
}
@ -161,19 +175,29 @@ I830EXASolid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
unsigned long offset;
unsigned long offset, pitch;
uint32_t cmd;
offset = exaGetPixmapOffset(pPixmap);
pitch = exaGetPixmapPitch(pPixmap);
offset = exaGetPixmapOffset(pPixmap);
{
BEGIN_LP_RING(6);
if (pPixmap->drawable.bitsPerPixel == 32)
OUT_RING(XY_COLOR_BLT_CMD | XY_COLOR_BLT_WRITE_ALPHA
| XY_COLOR_BLT_WRITE_RGB);
else
OUT_RING(XY_COLOR_BLT_CMD);
OUT_RING(pI830->BR[13]);
cmd = XY_COLOR_BLT_CMD;
if (pPixmap->drawable.bitsPerPixel == 32)
cmd |= XY_COLOR_BLT_WRITE_ALPHA | XY_COLOR_BLT_WRITE_RGB;
if (IS_I965G(pI830) && exaPixmapTiled(pPixmap)) {
assert((pitch % 512) == 0);
pitch >>= 2;
cmd |= XY_COLOR_BLT_TILED;
}
OUT_RING(cmd);
OUT_RING(pI830->BR[13] | pitch);
OUT_RING((y1 << 16) | (x1 & 0xffff));
OUT_RING((y2 << 16) | (x2 & 0xffff));
OUT_RING(offset);
@ -206,11 +230,9 @@ I830EXAPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
if (!EXA_PM_IS_SOLID(&pSrcPixmap->drawable, planemask))
I830FALLBACK("planemask is not solid");
pI830->copy_src_pitch = exaGetPixmapPitch(pSrcPixmap);
pI830->copy_src_off = exaGetPixmapOffset(pSrcPixmap);
pI830->pSrcPixmap = pSrcPixmap;
pI830->BR[13] = exaGetPixmapPitch(pDstPixmap);
pI830->BR[13] |= I830CopyROP[alu] << 16;
pI830->BR[13] = I830CopyROP[alu] << 16;
switch (pSrcPixmap->drawable.bitsPerPixel) {
case 8:
@ -231,30 +253,49 @@ I830EXACopy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
{
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t cmd;
int dst_x2, dst_y2;
unsigned int dst_off;
unsigned int dst_off, dst_pitch, src_off, src_pitch;
dst_x2 = dst_x1 + w;
dst_y2 = dst_y1 + h;
dst_off = exaGetPixmapOffset(pDstPixmap);
dst_pitch = exaGetPixmapPitch(pDstPixmap);
src_off = exaGetPixmapOffset(pI830->pSrcPixmap);
src_pitch = exaGetPixmapPitch(pI830->pSrcPixmap);
{
BEGIN_LP_RING(8);
if (pDstPixmap->drawable.bitsPerPixel == 32)
OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
else
OUT_RING(XY_SRC_COPY_BLT_CMD);
cmd = XY_SRC_COPY_BLT_CMD;
OUT_RING(pI830->BR[13]);
if (pDstPixmap->drawable.bitsPerPixel == 32)
cmd |= XY_SRC_COPY_BLT_WRITE_ALPHA | XY_SRC_COPY_BLT_WRITE_RGB;
if (IS_I965G(pI830)) {
if (exaPixmapTiled(pDstPixmap)) {
assert((dst_pitch % 512) == 0);
dst_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_DST_TILED;
}
if (exaPixmapTiled(pI830->pSrcPixmap)) {
assert((src_pitch % 512) == 0);
src_pitch >>= 2;
cmd |= XY_SRC_COPY_BLT_SRC_TILED;
}
}
OUT_RING(cmd);
OUT_RING(pI830->BR[13] | dst_pitch);
OUT_RING((dst_y1 << 16) | (dst_x1 & 0xffff));
OUT_RING((dst_y2 << 16) | (dst_x2 & 0xffff));
OUT_RING(dst_off);
OUT_RING((src_y1 << 16) | (src_x1 & 0xffff));
OUT_RING(pI830->copy_src_pitch);
OUT_RING(pI830->copy_src_off);
OUT_RING(src_pitch);
OUT_RING(src_off);
ADVANCE_LP_RING();
}
@ -410,11 +451,12 @@ I830EXAInit(ScreenPtr pScreen)
pI830->exa_offscreen->size;
pI830->EXADriverPtr->flags = EXA_OFFSCREEN_PIXMAPS;
DPRINTF(PFX, "EXA Mem: memoryBase 0x%x, end 0x%x, offscreen base 0x%x, memorySize 0x%x\n",
pI830->EXADriverPtr->memoryBase,
pI830->EXADriverPtr->memoryBase + pI830->EXADriverPtr->memorySize,
pI830->EXADriverPtr->offScreenBase,
pI830->EXADriverPtr->memorySize);
DPRINTF(PFX, "EXA Mem: memoryBase 0x%x, end 0x%x, offscreen base 0x%x, "
"memorySize 0x%x\n",
pI830->EXADriverPtr->memoryBase,
pI830->EXADriverPtr->memoryBase + pI830->EXADriverPtr->memorySize,
pI830->EXADriverPtr->offScreenBase,
pI830->EXADriverPtr->memorySize);
/* Limits are described in the BLT engine chapter under Graphics Data Size

115
src/i830_lvds.c
View File

@ -46,6 +46,30 @@ struct i830_lvds_priv {
int backlight_duty_cycle;
};
/**
* Use legacy backlight controls?
*
* \param pI830 device in question
*
* Returns TRUE if legacy backlight should be used, false otherwise.
*/
static int
i830_lvds_backlight_legacy(I830Ptr pI830)
{
CARD32 blc_pwm_ctl, blc_pwm_ctl2;
/* 965GM+ change the location of the legacy control bit */
if (IS_I965GM(pI830)) {
blc_pwm_ctl2 = INREG(BLC_PWM_CTL2);
if (blc_pwm_ctl2 & BLM_LEGACY_MODE2)
return TRUE;
} else {
blc_pwm_ctl = INREG(BLC_PWM_CTL);
if (blc_pwm_ctl & BLM_LEGACY_MODE)
return TRUE;
}
return FALSE;
}
/**
* Sets the backlight level.
@ -59,18 +83,12 @@ i830_lvds_set_backlight(xf86OutputPtr output, int level)
I830Ptr pI830 = I830PTR(pScrn);
CARD32 blc_pwm_ctl;
if (i830_lvds_backlight_legacy(pI830))
pciWriteByte(pI830->PciTag, LEGACY_BACKLIGHT_BRIGHTNESS, 0xfe);
blc_pwm_ctl = INREG(BLC_PWM_CTL);
if (blc_pwm_ctl & BLM_LEGACY_MODE)
{
pciWriteByte (pI830->PciTag,
LEGACY_BACKLIGHT_BRIGHTNESS,
level & 0xff);
}
else
{
blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
}
blc_pwm_ctl &= ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
}
/**
@ -82,12 +100,24 @@ i830_lvds_get_max_backlight(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
CARD32 pwm_ctl = INREG(BLC_PWM_CTL);
CARD32 val;
if (IS_I965GM(pI830)) {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK2) >>
BACKLIGHT_MODULATION_FREQ_SHIFT2);
} else {
val = ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
}
if (pwm_ctl & BLM_LEGACY_MODE)
return 0xff;
else
return ((pwm_ctl & BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
/*
* In legacy control mode, backlight value is calculated:
* if (LBB[7:0] != 0xff)
* backlight = BLC_PWM_CTL[15:0] * BPC[7:0]
* else
* backlight = BLC_PWM_CTL[15:0]
*/
return val;
}
/**
@ -138,21 +168,15 @@ i830_lvds_save (xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
if (IS_I965GM(pI830))
pI830->saveBLC_PWM_CTL2 = INREG(BLC_PWM_CTL2);
pI830->savePP_ON = INREG(LVDSPP_ON);
pI830->savePP_OFF = INREG(LVDSPP_OFF);
pI830->savePP_CONTROL = INREG(PP_CONTROL);
pI830->savePP_CYCLE = INREG(PP_CYCLE);
pI830->saveBLC_PWM_CTL = INREG(BLC_PWM_CTL);
if (pI830->saveBLC_PWM_CTL & BLM_LEGACY_MODE)
{
dev_priv->backlight_duty_cycle = pciReadByte (pI830->PciTag,
LEGACY_BACKLIGHT_BRIGHTNESS);
}
else
{
dev_priv->backlight_duty_cycle = (pI830->saveBLC_PWM_CTL &
BACKLIGHT_DUTY_CYCLE_MASK);
}
dev_priv->backlight_duty_cycle = (pI830->saveBLC_PWM_CTL &
BACKLIGHT_DUTY_CYCLE_MASK);
/*
* If the light is off at server startup, just make it full brightness
@ -167,6 +191,8 @@ i830_lvds_restore(xf86OutputPtr output)
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
if (IS_I965GM(pI830))
OUTREG(BLC_PWM_CTL2, pI830->saveBLC_PWM_CTL2);
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
OUTREG(LVDSPP_OFF, pI830->savePP_OFF);
@ -462,6 +488,9 @@ i830_lvds_init(ScrnInfoPtr pScrn)
DisplayModePtr modes, scan, bios_mode;
struct i830_lvds_priv *dev_priv;
if (pI830->quirk_flag & QUIRK_IGNORE_LVDS)
return;
output = xf86OutputCreate (pScrn, &i830_lvds_output_funcs, "LVDS");
if (!output)
return;
@ -575,29 +604,23 @@ i830_lvds_init(ScrnInfoPtr pScrn)
/* Blacklist machines with BIOSes that list an LVDS panel without actually
* having one.
*/
if (pI830->PciInfo->chipType == PCI_CHIP_I945_GM) {
if (pI830->PciInfo->subsysVendor == 0xa0a0) /* aopen mini pc */
goto disable_exit;
if (pI830->quirk_flag & QUIRK_IGNORE_MACMINI_LVDS) {
/* It's a Mac Mini or Macbook Pro.
*
* Apple hardware is out to get us. The macbook pro has a real
* LVDS panel, but the mac mini does not, and they have the same
* device IDs. We'll distinguish by panel size, on the assumption
* that Apple isn't about to make any machines with an 800x600
* display.
*/
if ((pI830->PciInfo->subsysVendor == 0x8086) &&
(pI830->PciInfo->subsysCard == 0x7270)) {
/* It's a Mac Mini or Macbook Pro.
*
* Apple hardware is out to get us. The macbook pro has a real
* LVDS panel, but the mac mini does not, and they have the same
* device IDs. We'll distinguish by panel size, on the assumption
* that Apple isn't about to make any machines with an 800x600
* display.
*/
if (dev_priv->panel_fixed_mode != NULL &&
if (dev_priv->panel_fixed_mode != NULL &&
dev_priv->panel_fixed_mode->HDisplay == 800 &&
dev_priv->panel_fixed_mode->VDisplay == 600)
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Suspected Mac Mini, ignoring the LVDS\n");
goto disable_exit;
}
{
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Suspected Mac Mini, ignoring the LVDS\n");
goto disable_exit;
}
}

5
src/i830_memory.c
View File

@ -1453,11 +1453,6 @@ i830_set_fence(ScrnInfoPtr pScrn, int nr, unsigned int offset,
assert(tile_format != TILING_NONE);
if (IS_I965G(pI830)) {
if (tile_format == TILING_XMAJOR)
pitch = 512;
else
pitch = 128;
if (nr < 0 || nr >= FENCE_NEW_NR) {
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
"i830_set_fence(): fence %d out of range\n",nr);

84
src/i830_quirks.c Normal file
View File

@ -0,0 +1,84 @@
/*
* Copyright © 2007 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Zhenyu Wang <zhenyu.z.wang@intel.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "i830.h"
#define SUBSYS_ANY (~0)
typedef struct {
int chipType;
int subsysVendor;
int subsysCard;
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
static void quirk_ignore_tv (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
static void quirk_ignore_lvds (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_LVDS;
}
static void quirk_mac_mini (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_MACMINI_LVDS;
}
static i830_quirk i830_quirk_list[] = {
/* Lenovo T61 has no TV output */
{ PCI_CHIP_I965_GM, 0x17aa, 0x20b5, quirk_ignore_tv },
/* Panasonic Toughbook CF-Y4 has no TV output */
{ PCI_CHIP_I915_GM, 0x10f7, 0x8338, quirk_ignore_tv },
/* Lenovo 3000 v200 */
{ PCI_CHIP_I965_GM, 0x17aa, 0x3c18, quirk_ignore_tv },
/* Aopen mini pc */
{ PCI_CHIP_I945_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
/* Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
{ 0, 0, 0, NULL },
};
void i830_fixup_devices(ScrnInfoPtr scrn)
{
I830Ptr pI830 = I830PTR(scrn);
i830_quirk_ptr p = i830_quirk_list;
while (p && p->chipType != 0) {
if (pI830->PciInfo->chipType == p->chipType &&
pI830->PciInfo->subsysVendor == p->subsysVendor &&
(pI830->PciInfo->subsysCard == p->subsysCard ||
p->subsysCard == SUBSYS_ANY))
p->hook(pI830);
++p;
}
}

7
src/i830_reg.h
View File

@ -36,6 +36,7 @@
#define FBC_CTL_EN (1<<31)
#define FBC_CTL_PERIODIC (1<<30)
#define FBC_CTL_INTERVAL_SHIFT (16)
#define FBC_CTL_UNCOMPRESSIBLE (1<<14)
#define FBC_CTL_STRIDE_SHIFT (5)
#define FBC_CTL_FENCENO (1<<0)
#define FBC_COMMAND 0x0320c
@ -46,9 +47,15 @@
#define FBC_STAT_MODIFIED (1<<29)
#define FBC_STAT_CURRENT_LINE (1<<0)
#define FBC_CONTROL2 0x03214
#define FBC_CTL_FENCE_DBL (0<<4)
#define FBC_CTL_IDLE_IMM (0<<2)
#define FBC_CTL_IDLE_FULL (1<<2)
#define FBC_CTL_IDLE_LINE (2<<2)
#define FBC_CTL_IDLE_DEBUG (3<<2)
#define FBC_CTL_CPU_FENCE (1<<1)
#define FBC_CTL_PLANEA (0<<0)
#define FBC_CTL_PLANEB (1<<0)
#define FBC_FENCE_OFF 0x0321b
#define FBC_LL_SIZE (1536)
#define FBC_LL_PAD (32)

3
src/i830_tv.c
View File

@ -1625,6 +1625,9 @@ i830_tv_init(ScrnInfoPtr pScrn)
struct i830_tv_priv *dev_priv;
CARD32 tv_dac_on, tv_dac_off, save_tv_dac;
if (pI830->quirk_flag & QUIRK_IGNORE_TV)
return;
if ((INREG(TV_CTL) & TV_FUSE_STATE_MASK) == TV_FUSE_STATE_DISABLED)
return;

2
src/i830_xaa.c
View File

@ -126,7 +126,6 @@ I830XAAInit(ScreenPtr pScreen)
if (!infoPtr)
return FALSE;
pI830->bufferOffset = 0;
infoPtr->Flags = LINEAR_FRAMEBUFFER | OFFSCREEN_PIXMAPS | PIXMAP_CACHE;
/* Use the same sync function as the I830.
@ -235,6 +234,7 @@ I830XAAInit(ScreenPtr pScreen)
infoPtr->RestoreAccelState = I830RestoreAccelState;
}
/* Set up pI830->bufferOffset */
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
if (!XAAInit(pScreen, infoPtr))

2
src/i915_render.c
View File

@ -288,7 +288,7 @@ i915_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
((pPix->drawable.height - 1) << MS3_HEIGHT_SHIFT) |
((pPix->drawable.width - 1) << MS3_WIDTH_SHIFT);
if (pI830->tiling)
pI830->samplerstate[unit * 3 + 1] |= MS3_USE_FENCE_REGS;
pI830->mapstate[unit * 3 + 1] |= MS3_USE_FENCE_REGS;
pI830->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT;
pI830->samplerstate[unit * 3 + 0] = (MIPFILTER_NONE <<

16
src/i965_render.c
View File

@ -161,16 +161,9 @@ static Bool i965_get_dest_format(PicturePtr pDstPicture, CARD32 *dst_format)
case PICT_x1r5g5b5:
*dst_format = BRW_SURFACEFORMAT_B5G5R5X1_UNORM;
break;
/* COLR_BUF_8BIT is special for YUV surfaces. While we may end up being
* able to use it depending on how the hardware implements it, disable it
* for now while we don't know what exactly it does (what channel does it
* read from?
*/
/*
case PICT_a8:
*dst_format = COLR_BUF_8BIT;
*dst_format = BRW_SURFACEFORMAT_A8_UNORM;
break;
*/
case PICT_a4r4g4b4:
case PICT_x4r4g4b4:
*dst_format = BRW_SURFACEFORMAT_B4G4R4A4_UNORM;
@ -292,7 +285,7 @@ static int next_offset, total_state_size;
static char *state_base;
static int state_base_offset;
static float *vb;
static int vb_size = (4 * 4) * 4 ; /* 4 DWORDS per vertex*/
static int vb_size = (6 * 4) * 4 ; /* 6 DWORDS per vertex - and mask*/
static CARD32 src_blend, dst_blend;
@ -503,7 +496,7 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
next_offset = mask_sampler_offset + sizeof(*mask_sampler_state);
}
/* Align VB to native size of elements, for safety */
vb_offset = ALIGN(next_offset, 8);
vb_offset = ALIGN(next_offset, 32);
next_offset = vb_offset + vb_size;
/* And then the general state: */
@ -800,7 +793,8 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
* back to SF which then hands pixels off to WM.
*/
if (pMask)
memcpy(sf_kernel, sf_kernel_static_mask, sizeof (sf_kernel_static));
memcpy(sf_kernel, sf_kernel_static_mask,
sizeof (sf_kernel_static_mask));
else if (rotation_program)
memcpy(sf_kernel, sf_kernel_static_rotation,
sizeof (sf_kernel_static_rotation));