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Give each user of tiling separate xorg.conf options 

So that you can indeed allocate a linear framebuffer if you so desire
without breaking mesa.

Adds:

Section "Driver"
  Option "LinearFramebuffer" "False|True" # default false
EndSection

to xorg.conf

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2011-03-09 08:27:02 +00:00
parent 0bb1a5f19e
commit 049ce4397d
6 changed files with 34 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
man/intel.man
View File

@ -181,12 +181,20 @@ the framerate of applications that render frames at less than refresh rate.
Default: enabled.
.TP
.BI "Option \*qTiling\*q \*q" boolean \*q
This option controls whether memory buffers are allocated in tiled mode. In
This option controls whether memory buffers for Pixmaps are allocated in tiled mode. In
most cases (especially for complex rendering), tiling dramatically improves
performance.
.IP
Default: enabled.
.TP
.BI "Option \*qLinearFramebuffer\*q \*q" boolean \*q
This option controls whether the memory for the scanout (also known as the
front or frame buffer) is allocated in linear memory. A tiled framebuffer is
required for power conservation features, but for certain system configurations
you may wish to override this and force a linear layout.
.IP
Default: disabled
.TP
.BI "Option \*qXvMC\*q \*q" boolean \*q
Enable XvMC driver. Current support MPEG2 MC on 915/945 and G33 series.
User should provide absolute path to libIntelXvMC.so in XvMCConfig file.

7
src/intel.h
View File

@ -297,7 +297,12 @@ typedef struct intel_screen_private {
Bool need_mi_flush;
Bool tiling;
unsigned int tiling;
#define INTEL_TILING_FB 0x1
#define INTEL_TILING_2D 0x2
#define INTEL_TILING_3D 0x4
#define INTEL_TILING_ALL (~0)
Bool swapbuffers_wait;
Bool has_relaxed_fencing;

4
src/intel_dri.c
View File

@ -219,7 +219,7 @@ I830DRI2CreateBuffers(DrawablePtr drawable, unsigned int *attachments,
if (pixmap == NULL) {
unsigned int hint = INTEL_CREATE_PIXMAP_DRI2;
if (intel->tiling) {
if (intel->tiling & INTEL_TILING_3D) {
switch (attachments[i]) {
case DRI2BufferDepth:
if (SUPPORTS_YTILING(intel))
@ -328,7 +328,7 @@ I830DRI2CreateBuffer(DrawablePtr drawable, unsigned int attachment,
if (pixmap == NULL) {
unsigned int hint = INTEL_CREATE_PIXMAP_DRI2;
if (intel->tiling) {
if (intel->tiling & INTEL_TILING_3D) {
switch (attachment) {
case DRI2BufferDepth:
case DRI2BufferDepthStencil:

23
src/intel_driver.c
View File

@ -89,7 +89,8 @@ typedef enum {
OPTION_VIDEO_KEY,
OPTION_COLOR_KEY,
OPTION_FALLBACKDEBUG,
OPTION_TILING,
OPTION_TILING_FB,
OPTION_TILING_2D,
OPTION_SHADOW,
OPTION_SWAPBUFFERS_WAIT,
#ifdef INTEL_XVMC
@ -108,7 +109,8 @@ static OptionInfoRec I830Options[] = {
{OPTION_COLOR_KEY, "ColorKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_VIDEO_KEY, "VideoKey", OPTV_INTEGER, {0}, FALSE},
{OPTION_FALLBACKDEBUG, "FallbackDebug", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_TILING, "Tiling", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_TILING_2D, "Tiling", OPTV_BOOLEAN, {0}, TRUE},
{OPTION_TILING_FB, "LinearFramebuffer", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_SHADOW, "Shadow", OPTV_BOOLEAN, {0}, FALSE},
{OPTION_SWAPBUFFERS_WAIT, "SwapbuffersWait", OPTV_BOOLEAN, {0}, TRUE},
#ifdef INTEL_XVMC
@ -586,12 +588,13 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE) != 0;
/* Enable tiling by default */
intel->tiling = TRUE;
intel->tiling = INTEL_TILING_ALL;
/* Allow user override if they set a value */
if (!ALWAYS_TILING(intel))
intel->tiling = xf86ReturnOptValBool(intel->Options,
OPTION_TILING, TRUE);
if (!xf86ReturnOptValBool(intel->Options, OPTION_TILING_2D, TRUE))
intel->tiling &= ~INTEL_TILING_2D;
if (xf86ReturnOptValBool(intel->Options, OPTION_TILING_FB, FALSE))
intel->tiling &= ~INTEL_TILING_FB;
intel->can_blt = can_accelerate_blt(intel);
intel->use_shadow = !intel->can_blt;
@ -616,8 +619,12 @@ static Bool I830PreInit(ScrnInfoPtr scrn, int flags)
if (IS_GEN6(intel))
intel->swapbuffers_wait = FALSE;
xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Tiling %sabled\n",
intel->tiling ? "en" : "dis");
xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Framebuffer %s\n",
intel->tiling & INTEL_TILING_FB ? "tiled" : "linear");
xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "Pixmaps %s\n",
intel->tiling & INTEL_TILING_2D ? "tiled" : "linear");
xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "3D buffers %s\n",
intel->tiling & INTEL_TILING_3D ? "tiled" : "linear");
xf86DrvMsg(scrn->scrnIndex, X_CONFIG, "SwapBuffers wait %sabled\n",
intel->swapbuffers_wait ? "en" : "dis");

2
src/intel_driver.h
View File

@ -223,8 +223,6 @@
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */
#define SUPPORTS_YTILING(pI810) (INTEL_INFO(intel)->gen >= 40)
#define ALWAYS_TILING(intel) IS_GEN6(intel)
extern SymTabRec *intel_chipsets;
struct intel_chipset {

4
src/intel_memory.c
View File

@ -185,7 +185,7 @@ drm_intel_bo *intel_allocate_framebuffer(ScrnInfoPtr scrn,
uint32_t tiling_mode;
unsigned long pitch;
if (intel->tiling)
if (intel->tiling & INTEL_TILING_FB)
tiling_mode = I915_TILING_X;
else
tiling_mode = I915_TILING_NONE;
@ -231,7 +231,7 @@ retry:
return NULL;
}
if (intel->tiling && tiling_mode != I915_TILING_X) {
if ((intel->tiling & INTEL_TILING_FB) && tiling_mode != I915_TILING_X) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"Failed to set tiling on frontbuffer.\n");
}