sna/gen4: Restore normal state after CA pass and FLUSH_EVERY_VERTEX
By working around the broken shaders, we emitted the CA rectangle in the middle of a sequence of glyphs and left the state setup for CA. So we need to reset the pipeline state at the start of every composite blt. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
2dff681efe
commit
0594724dc4
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@ -58,6 +58,12 @@
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#define PREFER_BLT 1
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#define FLUSH_EVERY_VERTEX 1
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#define NO_COMPOSITE 0
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#define NO_COPY 0
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#define NO_COPY_BOXES 0
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#define NO_FILL 0
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#define NO_FILL_BOXES 0
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#if FLUSH_EVERY_VERTEX
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#define FLUSH() do { \
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gen4_vertex_flush(sna); \
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@ -276,7 +282,7 @@ static const struct formatinfo {
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#define SAMPLER_OFFSET(sf, se, mf, me, k) \
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((((((sf) * EXTEND_COUNT + (se)) * FILTER_COUNT + (mf)) * EXTEND_COUNT + (me)) * KERNEL_COUNT + (k)) * 64)
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static bool
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static void
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gen4_emit_pipelined_pointers(struct sna *sna,
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const struct sna_composite_op *op,
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int blend, int kernel);
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@ -313,14 +319,15 @@ static void gen4_magic_ca_pass(struct sna *sna,
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return;
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DBG(("%s: CA fixup\n", __FUNCTION__));
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assert(op->mask.bo != NULL);
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assert(op->has_component_alpha);
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if (FLUSH_EVERY_VERTEX)
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OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
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gen4_emit_pipelined_pointers
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(sna, op, PictOpAdd,
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gen4_choose_composite_kernel(PictOpAdd,
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TRUE, TRUE, op->is_affine));
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gen4_emit_pipelined_pointers(sna, op, PictOpAdd,
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gen4_choose_composite_kernel(PictOpAdd,
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TRUE, TRUE, op->is_affine));
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OUT_BATCH(GEN4_3DPRIMITIVE |
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GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
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@ -447,9 +454,10 @@ static uint32_t gen4_get_blend(int op,
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static uint32_t gen4_get_dest_format(PictFormat format)
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{
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switch (format) {
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default:
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assert(0);
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case PICT_a8r8g8b8:
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case PICT_x8r8g8b8:
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default:
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return GEN4_SURFACEFORMAT_B8G8R8A8_UNORM;
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case PICT_a8b8g8r8:
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case PICT_x8b8g8r8:
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@ -1068,7 +1076,7 @@ static int gen4_get_rectangles__flush(struct sna *sna)
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gen4_vertex_finish(sna, FALSE);
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sna->render.vertex_index = 0;
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return ARRAY_SIZE(sna->render.vertex_data);
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return ARRAY_SIZE(sna->render.vertex_data);
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}
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inline static int gen4_get_rectangles(struct sna *sna,
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@ -1088,7 +1096,7 @@ inline static int gen4_get_rectangles(struct sna *sna,
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if (!gen4_rectangle_begin(sna, op))
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return 0;
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if (want * op->floats_per_vertex*3 > rem)
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if (want > 1 && want * op->floats_per_vertex*3 > rem)
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want = rem / (3*op->floats_per_vertex);
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sna->render.vertex_index += 3*want;
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@ -1099,19 +1107,15 @@ static uint32_t *gen4_composite_get_binding_table(struct sna *sna,
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const struct sna_composite_op *op,
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uint16_t *offset)
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{
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uint32_t *table;
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sna->kgem.surface -=
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sizeof(struct gen4_surface_state_padded) / sizeof(uint32_t);
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/* Clear all surplus entries to zero in case of prefetch */
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table = memset(sna->kgem.batch + sna->kgem.surface,
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0, sizeof(struct gen4_surface_state_padded));
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*offset = sna->kgem.surface;
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DBG(("%s(%x)\n", __FUNCTION__, 4*sna->kgem.surface));
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return table;
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/* Clear all surplus entries to zero in case of prefetch */
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*offset = sna->kgem.surface;
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return memset(sna->kgem.batch + sna->kgem.surface,
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0, sizeof(struct gen4_surface_state_padded));
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}
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static void
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@ -1131,6 +1135,9 @@ gen4_emit_urb(struct sna *sna)
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int urb_sf_start, urb_sf_size;
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int urb_cs_start, urb_cs_size;
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if (!sna->render_state.gen4.needs_urb)
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return;
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urb_vs_start = 0;
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urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
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urb_gs_start = urb_vs_start + urb_vs_size;
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@ -1158,6 +1165,8 @@ gen4_emit_urb(struct sna *sna)
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/* Constant buffer state */
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OUT_BATCH(GEN4_CS_URB_STATE | 0);
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OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | URB_CS_ENTRIES << 0);
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sna->render_state.gen4.needs_urb = false;
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}
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static void
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@ -1246,13 +1255,19 @@ gen4_emit_binding_table(struct sna *sna, uint16_t offset)
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OUT_BATCH(offset*4);
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}
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static bool
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static void
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gen4_emit_pipelined_pointers(struct sna *sna,
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const struct sna_composite_op *op,
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int blend, int kernel)
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{
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uint16_t offset = sna->kgem.nbatch, last;
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DBG(("%s: has_mask=%d, src=(%d, %d), mask=(%d, %d),kernel=%d, blend=%d, ca=%d, format=%x\n",
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__FUNCTION__, op->mask.bo != NULL,
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op->src.filter, op->src.repeat,
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op->mask.filter, op->mask.repeat,
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kernel, blend, op->has_component_alpha, op->dst.format));
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OUT_BATCH(GEN4_3DSTATE_PIPELINED_POINTERS | 5);
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OUT_BATCH(sna->render_state.gen4.vs);
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OUT_BATCH(GEN4_GS_DISABLE); /* passthrough */
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@ -1267,16 +1282,13 @@ gen4_emit_pipelined_pointers(struct sna *sna,
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last = sna->render_state.gen4.last_pipelined_pointers;
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if (last &&
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sna->kgem.batch[offset + 1] == sna->kgem.batch[last + 1] &&
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sna->kgem.batch[offset + 3] == sna->kgem.batch[last + 3] &&
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sna->kgem.batch[offset + 4] == sna->kgem.batch[last + 4] &&
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sna->kgem.batch[offset + 5] == sna->kgem.batch[last + 5] &&
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sna->kgem.batch[offset + 6] == sna->kgem.batch[last + 6]) {
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sna->kgem.nbatch = offset;
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return false;
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} else {
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sna->render_state.gen4.last_pipelined_pointers = offset;
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return true;
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gen4_emit_urb(sna);
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}
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}
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@ -1377,8 +1389,7 @@ gen4_emit_state(struct sna *sna,
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uint16_t wm_binding_table)
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{
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gen4_emit_binding_table(sna, wm_binding_table);
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if (gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel))
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gen4_emit_urb(sna);
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gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel);
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gen4_emit_vertex_elements(sna, op);
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gen4_emit_drawing_rectangle(sna, op);
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}
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@ -1413,6 +1424,14 @@ gen4_bind_surfaces(struct sna *sna,
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op->mask.card_format,
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FALSE);
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if (sna->kgem.surface == offset &&
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*(uint64_t *)(sna->kgem.batch + sna->render_state.gen4.surface_table) == *(uint64_t*)binding_table &&
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(op->mask.bo == NULL ||
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sna->kgem.batch[sna->render_state.gen4.surface_table+2] == binding_table[2])) {
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sna->kgem.surface += sizeof(struct gen4_surface_state_padded) / sizeof(uint32_t);
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offset = sna->render_state.gen4.surface_table;
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}
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gen4_emit_state(sna, op, offset);
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}
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@ -1428,6 +1447,11 @@ gen4_render_composite_blt(struct sna *sna,
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r->dst.x, r->dst.y, op->dst.x, op->dst.y,
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r->width, r->height));
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if (FLUSH_EVERY_VERTEX && op->need_magic_ca_pass)
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/* We have to reset the state after every FLUSH */
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gen4_emit_pipelined_pointers(sna, op,
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op->op, op->u.gen4.wm_kernel);
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if (!gen4_get_rectangles(sna, op, 1)) {
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gen4_bind_surfaces(sna, op);
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gen4_get_rectangles(sna, op, 1);
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@ -1828,17 +1852,14 @@ picture_is_cpu(PicturePtr picture)
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return is_cpu(picture->pDrawable);
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}
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static inline bool prefer_blt(struct sna *sna)
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{
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#if PREFER_BLT
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static inline bool prefer_blt(struct sna *sna)
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{
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return true;
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}
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#else
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static inline bool prefer_blt(struct sna *sna)
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{
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return sna->kgem.mode != KGEM_RENDER;
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}
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#endif
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}
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static Bool
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try_blt(struct sna *sna,
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@ -1876,6 +1897,17 @@ gen4_render_composite(struct sna *sna,
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DBG(("%s: %dx%d, current mode=%d\n", __FUNCTION__,
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width, height, sna->kgem.mode));
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#if NO_COMPOSITE
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if (mask)
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return FALSE;
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return sna_blt_composite(sna, op,
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src, dst,
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src_x, src_y,
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dst_x, dst_y,
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width, height, tmp);
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#endif
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if (mask == NULL &&
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try_blt(sna, dst, src, width, height) &&
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sna_blt_composite(sna, op,
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@ -2107,6 +2139,14 @@ gen4_render_copy_boxes(struct sna *sna, uint8_t alu,
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{
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struct sna_composite_op tmp;
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#if NO_COPY_BOXES
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return sna_blt_copy_boxes(sna, alu,
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src_bo, src_dx, src_dy,
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dst_bo, dst_dx, dst_dy,
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dst->drawable.bitsPerPixel,
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box, n);
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#endif
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if (prefer_blt(sna) &&
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sna_blt_copy_boxes(sna, alu,
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src_bo, src_dx, src_dy,
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@ -2198,6 +2238,13 @@ gen4_render_copy(struct sna *sna, uint8_t alu,
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PixmapPtr dst, struct kgem_bo *dst_bo,
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struct sna_copy_op *op)
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{
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#if NO_COPY
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return sna_blt_copy(sna, alu,
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src_bo, dst_bo,
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dst->drawable.bitsPerPixel,
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op);
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#endif
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if (prefer_blt(sna) &&
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sna_blt_copy(sna, alu,
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src_bo, dst_bo,
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@ -2357,6 +2404,10 @@ gen4_render_fill_boxes(struct sna *sna,
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return FALSE;
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}
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#if NO_FILL_BOXES
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return FALSE;
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#endif
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if (!sna_get_pixel_from_rgba(&pixel,
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color->red,
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color->green,
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@ -2425,6 +2476,13 @@ gen4_render_fill(struct sna *sna, uint8_t alu,
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uint32_t color,
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struct sna_fill_op *op)
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{
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#if NO_FILL
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return sna_blt_fill(sna, alu,
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dst_bo, dst->drawable.bitsPerPixel,
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color,
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op);
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#endif
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if (prefer_blt(sna) &&
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sna_blt_fill(sna, alu,
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dst_bo, dst->drawable.bitsPerPixel,
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@ -2482,6 +2540,7 @@ gen4_render_flush(struct sna *sna)
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static void gen4_render_reset(struct sna *sna)
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{
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sna->render_state.gen4.needs_invariant = TRUE;
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sna->render_state.gen4.needs_urb = TRUE;
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sna->render_state.gen4.vb_id = 0;
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sna->render_state.gen4.ve_id = -1;
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sna->render_state.gen4.last_primitive = -1;
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@ -282,6 +282,7 @@ struct gen4_render_state {
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uint16_t last_pipelined_pointers;
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Bool needs_invariant;
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Bool needs_urb;
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};
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struct gen5_render_state {
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