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Merge branch 'master' into exa 

Conflicts:

	man/i810.man
	src/Makefile.am
	src/i830_accel.c
	src/i830_dga.c
	src/i830_driver.c
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Wang Zhenyu 2006-08-24 10:23:22 +08:00
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163
README
View File

@ -1,8 +1,6 @@
$XFree86:
xc/programs/Xserver/hw/xfree86/doc/sgml/i810.sgml,v 1.4
2001/04/04 01:34:18 dawes Exp $ Information for i810 Users
Precision Insight, Inc.
3 March 2000
Information for Intel graphics driver users
Eric Anholt
2006-08-04
____________________________________________________________
Table of Contents
@ -12,88 +10,85 @@
2. Supported Hardware
3. Features
4. Technical Notes
5. Reported Working Video Cards
6. Configuration
7. Driver Options
8. Known Limitations
9. Author
5. Configuration
6. Driver Options
7. Known Limitations
8. Author
______________________________________________________________________
1. Introduction
11.. IInnttrroodduuccttiioonn
This document provides a brief summary of the i810/i815 support
provided by the i810 driver. Support for later chipsets is not
covered here. More up to date information about the i810 driver can
be found in the i810(4) manual page.
This document provides a brief summary of the Intel graphics support
provided by the xf86-video-intel driver. More information can also be
found in the i810(4) manual page.
2. Supported Hardware
22.. SSuuppppoorrtteedd HHaarrddwwaarree
+o Intel 810 motherboards:
+o i810,
+o i810,
+o i810-dc100,
+o i810-dc100,
+o i810e
+o i810e
+o i815
+o i815
+o i830
+o i845
+o i852
+o i855
+o i915
+o i945
+o i965
3. Features
33.. FFeeaattuurreess
+o Full support for 8, 15, 16, and 24 bit pixel depths.
+o Hardware cursor support to reduce sprite flicker.
+o Hardware accelerated 2D drawing engine support for 8, 15, 16 and 24
bit pixel depths.
+o Support for high resolution video modes up to 1600x1200.
+o Hardware accelerated 3D drawing using OpenGL and the DRI.
+o Fully programmable clock supported.
+o Hardware cursor support to reduce sprite flicker.
+o Robust text mode restore for VT switching.
+o Textured video XV implementation on i915 through i965.
+o Hardware overlay XV implementation up through i945.
+o Screen resize and rotation on chipsets up through i945.
+o Screen resize on i965.
4. Technical Notes
44.. TTeecchhnniiccaall NNootteess
+o Hardware acceleration is not possible when using the framebuffer in
32 bit per pixel format, and this mode is not supported by this
driver.
+o Interlace modes cannot be supported.
+o This driver currently only works for Linux/ix86 and recent versions
of FreeBSD. It requires the agpgart kernel support, which is
included in Linux kernels 2.3.42 and higher, and FreeBSD 4.1 and
higher.
+o This driver requires kernel support for AGP, which is included in
Linux kernels 2.3.42 and higher, and FreeBSD 4.1 and higher.
5. Reported Working Video Cards
+o Intel evaluation hardware - i810, i810-dc100, i810e and i815.
+o Tyan Tomcat Motherboard.
+o HappyPC set-top box.
6. Configuration
55.. CCoonnffiigguurraattiioonn
The driver auto-detects all device information necessary to initialize
the card. The only lines you need in the "Device" section of your
xorg.conf file are:
the card. The only lines you should need in the "Device" section of
your xorg.conf file are:
Section "Device"
Identifier "Intel i810"
@ -101,54 +96,68 @@
EndSection
or let xorgconfig do this for you.
However, if you have problems with auto-detection, you can specify:
In order to use most resolutions, it is necessary to install the
"agpgart.o" module. You will probably have to compile the module
yourself (see the notes in the module).
+o DacSpeed - in MHz
+o MemBase - physical address of the linear framebuffer
66.. DDrriivveerr OOppttiioonnss
+o IOBase - physical address of the memory mapped IO registers
In order to use most resolutions, it is necessary to install the (see
the notes in the module).
Note: the i810 driver detects whether your motherboard has display
cache video memory. This memory is has reduced bandwidth compared to
normal system memory, and isn't used by the server. The main function
of this memory is for ancillary buffers (eg. z buffer) in a
forthcoming 3d capable server.
Please refer to the i810(4) manual page for information on
configuration options.
7. Driver Options
77.. KKnnoowwnn LLiimmiittaattiioonnss
+o "NoAccel" - Turn off hardware acceleration
+o Many systems with Intel graphics have issues with setting video
modes at larger than some small maximum resolution. This is not
fixed in the current release, but is being actively worked on in
the modesetting branch.
+o Bug #5795: Some systems have issues with VT switching. This should
be fixed with the modesetting brach integration.
+o "SWCursor" - Request a software cursor (hardware is default)
+o Bug #5817: Hotkey switching from LVDS to CRT breaks CRT output.
This is a known issue, but will not be fixed in the current
release.
+o "Dac6Bit" - Force the use of a 6 Bit Dac (8 Bit is the default)
+o Bug #6635: Video is output from an incorrect offset in the
framebuffer. This is expected to be fixed with the modesetting
branch integration.
+o GL_EXT_texture_compression_s3tc is not supported. We can't support
the extension due to patent restrictions on compression, but may be
able to support an option for partial extension support in the
future. For now, this prevents Quake4 and some other games from
running.
8. Known Limitations
+o Some X Test Suite cases sometimes fail due to a timeout. These
cases include: Xt8/XtResizeWindow, Xt8/XtQueryGeometry,
Xt9/XtAppAddInput, Xt9/XtRemoveInput, Xt9/XtAppAddTimeOut,
Xt9/XtRemoveTimeOut, Xt9/XtAddGrab, Xt9/XtRemoveGrab.
+o Some X Test Suite cases fail in 64-bit mode: Xlib9/XDrawArc,
XDrawImageString, XDrawLine, XDrawRectangle, XDrawSegments,
XFillArc, XFillPolygon, XFillRectangle, XPutImage,
Xt11/XtVaGetSubresources, XtSetSubvalues, and XtVaSetSubvalues.
+o No 3D support in this release.
+o Running two X servers on different VTs is not supported at this
time.
+o Some GLEAN test cases fail if DRI is enabled: pointAtten,
readPixSanity, texCombine, texCube, texEnv, texgen,
coloredTexPerf2, and coloredLitPerf2.
9. Author
88.. AAuutthhoorr
+o Eric Anholt
+o Keith Whitwell
The X11R6.8 version of this driver originally came from XFree86 4.4
The X11R7.1 version of this driver originally came from XFree86 4.4
rc2.
The XFree86 version of this driver was donated to The XFree86 Project
@ -160,7 +169,9 @@
http://www.precisioninsight.com
The X.Org version of this driver is maintained by Intel Corporation.
http://www.intellinuxgraphics.org

117
README.sgml
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@ -3,31 +3,31 @@
]>
<article>
<title>Information for i810 Users
<author>Precision Insight, Inc.
<date>3 March 2000
<ident>
$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/i810.sgml,v 1.4 2001/04/04 01:34:18 dawes Exp $
</ident>
<title>Information for Intel graphics driver users
<author>Eric Anholt
<date>2006-08-04
<toc>
<sect>Introduction
<p>
This document provides a brief summary of the i810/i815 support provided
by the i810 driver. Support for later chipsets is not covered here.
More up to date information about the i810 driver can be found in the
This document provides a brief summary of the Intel graphics support provided
by the xf86-video-intel driver. More information can also be found in the
<htmlurl name="i810(4)" url="i810.4.html"> manual page.
<sect>Supported Hardware
<p>
<itemize>
<item>Intel 810 motherboards:
<itemize>
<item>i810,
<item>i810-dc100,
<item>i810e
<item>i815
</itemize>
<item>i810,
<item>i810-dc100,
<item>i810e
<item>i815
<item>i830
<item>i845
<item>i852
<item>i855
<item>i915
<item>i945
<item>i965
</itemize>
@ -35,42 +35,31 @@ More up to date information about the i810 driver can be found in the
<p>
<itemize>
<item>Full support for 8, 15, 16, and 24 bit pixel depths.
<item>Hardware cursor support to reduce sprite flicker.
<item>Hardware accelerated 2D drawing engine support for 8, 15, 16 and
24 bit pixel depths.
<item>Support for high resolution video modes up to 1600x1200.
<item>Fully programmable clock supported.
<item>Robust text mode restore for VT switching.
<item>Hardware accelerated 3D drawing using OpenGL and the DRI.
<item>Hardware cursor support to reduce sprite flicker.
<item>Textured video XV implementation on i915 through i965.
<item>Hardware overlay XV implementation up through i945.
<item>Screen resize and rotation on chipsets up through i945.
<item>Screen resize on i965.
</itemize>
<sect>Technical Notes
<p>
<itemize>
<item>Hardware acceleration is not possible when using the framebuffer
in 32 bit per pixel format, and this mode is not supported by
this driver.
<item>Interlace modes cannot be supported.
<item>This driver currently only works for Linux/ix86 and recent versions
of FreeBSD. It requires the agpgart kernel support, which is
<item>This driver requires kernel support for AGP, which is
included in Linux kernels 2.3.42 and higher, and FreeBSD 4.1
and higher.
</itemize>
<sect>Reported Working Video Cards
<p>
<itemize>
<item>Intel evaluation hardware - i810, i810-dc100, i810e and i815.
<item>Tyan Tomcat Motherboard.
<item>HappyPC set-top box.
</itemize>
<sect>Configuration
<p>
The driver auto-detects all device information necessary to
initialize the card. The only lines you need in the "Device"
initialize the card. The only lines you should need in the "Device"
section of your xorg.conf file are:
<verb>
Section "Device"
@ -78,45 +67,51 @@ section of your xorg.conf file are:
Driver "i810"
EndSection
</verb>
or let <tt>xorgconfig</tt> do this for you.
However, if you have problems with auto-detection, you can specify:
<itemize>
<item>DacSpeed - in MHz
<item>MemBase - physical address of the linear framebuffer
<item>IOBase - physical address of the memory mapped IO registers
</itemize>
In order to use most resolutions, it is necessary to install the
'agpgart.o' module. You will probably have to compile the module yourself
"agpgart.o" module. You will probably have to compile the module yourself
(see the notes in the module).
Note: the i810 driver detects whether your motherboard has display cache
video memory. This memory is has reduced bandwidth compared to normal
system memory, and isn't used by the server. The main function of this
memory is for ancillary buffers (eg. z buffer) in a forthcoming 3d
capable server.
<sect>Driver Options
<p>
<itemize>
<item>"NoAccel" - Turn off hardware acceleration
<item>"SWCursor" - Request a software cursor (hardware is default)
<item>"Dac6Bit" - Force the use of a 6 Bit Dac (8 Bit is the default)
</itemize>
Please refer to the <htmlurl name="i810(4)" url="i810.4.html"> manual page
for information on configuration options.
<sect>Known Limitations
<p>
<itemize>
<item>No 3D support in this release.
<item>Running two X servers on different VTs is not supported at this time.
<item>Many systems with Intel graphics have issues with setting video modes
at larger than some small maximum resolution. This is not fixed in the current
release, but is being actively worked on in the modesetting branch.
<item>Bug #5795: Some systems have issues with VT switching. This should
be fixed with the modesetting brach integration.
<item>Bug #5817: Hotkey switching from LVDS to CRT breaks CRT output. This
is a known issue, but will not be fixed in the current release.
<item>Bug #6635: Video is output from an incorrect offset in the framebuffer.
This is expected to be fixed with the modesetting branch integration.
<item>GL_EXT_texture_compression_s3tc is not supported. We can't support the
extension due to patent restrictions on compression, but may be able to support
an option for partial extension support in the future. For now, this prevents
Quake4 and some other games from running.
<item>Some X Test Suite cases sometimes fail due to a timeout. These cases
include: Xt8/XtResizeWindow, Xt8/XtQueryGeometry, Xt9/XtAppAddInput,
Xt9/XtRemoveInput, Xt9/XtAppAddTimeOut, Xt9/XtRemoveTimeOut, Xt9/XtAddGrab,
Xt9/XtRemoveGrab.
<item>Some X Test Suite cases fail in 64-bit mode: Xlib9/XDrawArc,
XDrawImageString, XDrawLine, XDrawRectangle, XDrawSegments, XFillArc,
XFillPolygon, XFillRectangle, XPutImage, Xt11/XtVaGetSubresources,
XtSetSubvalues, and XtVaSetSubvalues.
<item>Some GLEAN test cases fail if DRI is enabled: pointAtten,
readPixSanity, texCombine, texCube, texEnv, texgen, coloredTexPerf2, and
coloredLitPerf2.
</itemize>
<sect>Author
<p>
<itemize>
<item>Eric Anholt
<item>Keith Whitwell
</itemize>
@ -129,8 +124,10 @@ The XFree86 version of this driver was donated to The XFree86 Project by:
USA
</verb>
<htmlurl name="http://www.precisioninsight.com"
url="http://www.precisioninsight.com">
The X.Org version of this driver is maintained by Intel Corporation.
<htmlurl name="http://www.intellinuxgraphics.org"
url="http://www.intellinuxgraphics.org">
</article>

13
configure.ac
View File

@ -22,10 +22,20 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-i810],
1.6.0,
1.6.5,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-i810)
AC_DEFINE_UNQUOTED([INTEL_VERSION_MAJOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^\([[0-9]]\)\.[[0-9]]\.[[0-9]]/\1/')],
[Major version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_MINOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.\([[0-9]]\)\.[[0-9]]/\1/')],
[Minor version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_PATCH],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.[[0-9]]\.\([[0-9]]\)/\1/')],
[Patch version])
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
AC_CONFIG_AUX_DIR(.)
@ -54,6 +64,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XF86DRI, xextproto x11)

2
man/.gitignore vendored
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@ -1,2 +0,0 @@
i810.4
i810.4x

34
man/i810.man
View File

@ -17,30 +17,29 @@ i810 \- Intel 8xx integrated graphics chipsets
is an __xservername__ driver for Intel integrated graphics chipsets.
The driver supports depths 8, 15, 16 and 24. All visual types are
supported in depth 8. For the i810/i815 other depths support the
TrueColor and DirectColor visuals. For the 830M and later, only the
TrueColor and DirectColor visuals. For the i830M and later, only the
TrueColor visual is supported for depths greater than 8. The driver
supports hardware accelerated 3D via the Direct Rendering Infrastructure
(DRI), but only in depth 16 for the i810/i815 and depths 16 and 24 for
the 830M and later.
.SH SUPPORTED HARDWARE
.B i810
supports the i810, i810-DC100, i810e, i815, 830M, 845G, 852GM, 855GM,
865G, 915G and 915GM chipsets.
supports the i810, i810-DC100, i810e, i815, i830M, 845G, 852GM, 855GM,
865G, 915G, 915GM, 945G, 945GM, 965G, 965Q and 946GZ chipsets.
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
details. This section only covers configuration details specific to this
driver.
.PP
The Intel 8xx family of integrated graphics chipsets has a unified memory
architecture and uses system memory for video ram. For the i810 and
The Intel 8xx and 9xx families of integrated graphics chipsets has a unified
memory architecture and uses system memory for video ram. For the i810 and
i815 family of chipset, operating system support for allocating system
memory for video use is required in order to use this driver. For the
830M and later, this is required in order for the driver to use more
video ram than has been pre-allocated at boot time by the BIOS. This
is usually achieved with an "agpgart" or "agp" kernel driver. Linux,
and recent versions of FreeBSD, OpenBSD and NetBSD have such kernel
drivers available.
memory for video use is required in order to use this driver. For the 830M
and later, this is required in order for the driver to use more video ram
than has been pre-allocated at boot time by the BIOS. This is usually
achieved with an "agpgart" or "agp" kernel driver. Linux, and recent
versions of FreeBSD, OpenBSD and NetBSD have such kernel drivers available.
.PP
By default 8 Megabytes
of system memory are used for graphics. For the 830M and later, the
@ -214,10 +213,11 @@ extension. Default: "XAA".
.SH "SEE ALSO"
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
.SH AUTHORS
Authors include: Keith Whitwell, and also Jonathan Bian, Matthew J Sottek,
Authors include: Keith Whitwell, and also Jonathan Bian, Matthew J Sottek,
Jeff Hartmann, Mark Vojkovich, Alan Hourihane, H. J. Lu. 830M and 845G
support reworked for XFree86 4.3 by David Dawes and Keith Whitwell.
852GM, 855GM, and 865G support added by David Dawes and Keith Whitwell.
915G and 915GM support added by Alan Hourihane and Keith Whitwell.
Dual Head, Clone and lid status support added by Alan Hourihane. EXA support
added by Jesse Barnes.
support reworked for XFree86 4.3 by David Dawes and Keith Whitwell. 852GM,
855GM, and 865G support added by David Dawes and Keith Whitwell. 915G,
915GM, 945G, 945GM, 965G, 965Q and 946GZ support added by Alan Hourihane and
Keith Whitwell. Dual Head, Clone and lid status support added by Alan
Hourihane. Textured video support for 915G and later chips added by Keith
Packard and Eric Anholt.

5
src/Makefile.am
View File

@ -31,6 +31,9 @@ i810_drv_la_LDFLAGS = -module -avoid-version
i810_drv_ladir = @moduledir@/drivers
i810_drv_la_SOURCES = \
brw_defines.h \
brw_structs.h \
wm_prog.h \
common.h \
i810_accel.c \
i810_common.h \
@ -53,6 +56,7 @@ i810_drv_la_SOURCES = \
i830_memory.c \
i830_modes.c \
i830_video.c \
i830_video.h \
i830_rotate.c \
i830_randr.c \
i830_3d.c \
@ -60,6 +64,7 @@ i810_drv_la_SOURCES = \
i915_3d.c \
i915_3d.h \
i915_reg.h \
i915_video.c \
i830_exa.c \
i830_xaa.c \
i830_exa_render.c \

847
src/brw_defines.h Normal file
View File

@ -0,0 +1,847 @@
/**************************************************************************
*
* Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H
/*
*/
#if 0
#define MI_NOOP 0x00
#define MI_USER_INTERRUPT 0x02
#define MI_WAIT_FOR_EVENT 0x03
#define MI_FLUSH 0x04
#define MI_REPORT_HEAD 0x07
#define MI_ARB_ON_OFF 0x08
#define MI_BATCH_BUFFER_END 0x0A
#define MI_OVERLAY_FLIP 0x11
#define MI_LOAD_SCAN_LINES_INCL 0x12
#define MI_LOAD_SCAN_LINES_EXCL 0x13
#define MI_DISPLAY_BUFFER_INFO 0x14
#define MI_SET_CONTEXT 0x18
#define MI_STORE_DATA_IMM 0x20
#define MI_STORE_DATA_INDEX 0x21
#define MI_LOAD_REGISTER_IMM 0x22
#define MI_STORE_REGISTER_MEM 0x24
#define MI_BATCH_BUFFER_START 0x31
#define MI_SYNCHRONOUS_FLIP 0x0
#define MI_ASYNCHRONOUS_FLIP 0x1
#define MI_BUFFER_SECURE 0x0
#define MI_BUFFER_NONSECURE 0x1
#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0
#define MI_ARBITRATE_BETWEEN_INSTS 0x1
#define MI_NO_ARBITRATION 0x3
#define MI_CONDITION_CODE_WAIT_DISABLED 0x0
#define MI_CONDITION_CODE_WAIT_0 0x1
#define MI_CONDITION_CODE_WAIT_1 0x2
#define MI_CONDITION_CODE_WAIT_2 0x3
#define MI_CONDITION_CODE_WAIT_3 0x4
#define MI_CONDITION_CODE_WAIT_4 0x5
#define MI_DISPLAY_PIPE_A 0x0
#define MI_DISPLAY_PIPE_B 0x1
#define MI_DISPLAY_PLANE_A 0x0
#define MI_DISPLAY_PLANE_B 0x1
#define MI_DISPLAY_PLANE_C 0x2
#define MI_STANDARD_FLIP 0x0
#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1
#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2
#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3
#define MI_PHYSICAL_ADDRESS 0x0
#define MI_VIRTUAL_ADDRESS 0x1
#define MI_BUFFER_MEMORY_MAIN 0x0
#define MI_BUFFER_MEMORY_GTT 0x2
#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3
#define MI_FLIP_CONTINUE 0x0
#define MI_FLIP_ON 0x1
#define MI_FLIP_OFF 0x2
#define MI_UNTRUSTED_REGISTER_SPACE 0x0
#define MI_TRUSTED_REGISTER_SPACE 0x1
#endif
/* 3D state:
*/
#define _3DOP_3DSTATE_PIPELINED 0x0
#define _3DOP_3DSTATE_NONPIPELINED 0x1
#define _3DOP_3DCONTROL 0x2
#define _3DOP_3DPRIMITIVE 0x3
#define _3DSTATE_PIPELINED_POINTERS 0x00
#define _3DSTATE_BINDING_TABLE_POINTERS 0x01
#define _3DSTATE_VERTEX_BUFFERS 0x08
#define _3DSTATE_VERTEX_ELEMENTS 0x09
#define _3DSTATE_INDEX_BUFFER 0x0A
#define _3DSTATE_VF_STATISTICS 0x0B
#define _3DSTATE_DRAWING_RECTANGLE 0x00
#define _3DSTATE_CONSTANT_COLOR 0x01
#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02
#define _3DSTATE_CHROMA_KEY 0x04
#define _3DSTATE_DEPTH_BUFFER 0x05
#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06
#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07
#define _3DSTATE_LINE_STIPPLE 0x08
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09
#define _3DCONTROL 0x00
#define _3DPRIMITIVE 0x00
#define PIPE_CONTROL_NOWRITE 0x00
#define PIPE_CONTROL_WRITEIMMEDIATE 0x01
#define PIPE_CONTROL_WRITEDEPTH 0x02
#define PIPE_CONTROL_WRITETIMESTAMP 0x03
#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01
#define _3DPRIM_POINTLIST 0x01
#define _3DPRIM_LINELIST 0x02
#define _3DPRIM_LINESTRIP 0x03
#define _3DPRIM_TRILIST 0x04
#define _3DPRIM_TRISTRIP 0x05
#define _3DPRIM_TRIFAN 0x06
#define _3DPRIM_QUADLIST 0x07
#define _3DPRIM_QUADSTRIP 0x08
#define _3DPRIM_LINELIST_ADJ 0x09
#define _3DPRIM_LINESTRIP_ADJ 0x0A
#define _3DPRIM_TRILIST_ADJ 0x0B
#define _3DPRIM_TRISTRIP_ADJ 0x0C
#define _3DPRIM_TRISTRIP_REVERSE 0x0D
#define _3DPRIM_POLYGON 0x0E
#define _3DPRIM_RECTLIST 0x0F
#define _3DPRIM_LINELOOP 0x10
#define _3DPRIM_POINTLIST_BF 0x11
#define _3DPRIM_LINESTRIP_CONT 0x12
#define _3DPRIM_LINESTRIP_BF 0x13
#define _3DPRIM_LINESTRIP_CONT_BF 0x14
#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0
#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1
#define BRW_ANISORATIO_2 0
#define BRW_ANISORATIO_4 1
#define BRW_ANISORATIO_6 2
#define BRW_ANISORATIO_8 3
#define BRW_ANISORATIO_10 4
#define BRW_ANISORATIO_12 5
#define BRW_ANISORATIO_14 6
#define BRW_ANISORATIO_16 7
#define BRW_BLENDFACTOR_ONE 0x1
#define BRW_BLENDFACTOR_SRC_COLOR 0x2
#define BRW_BLENDFACTOR_SRC_ALPHA 0x3
#define BRW_BLENDFACTOR_DST_ALPHA 0x4
#define BRW_BLENDFACTOR_DST_COLOR 0x5
#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
#define BRW_BLENDFACTOR_CONST_COLOR 0x7
#define BRW_BLENDFACTOR_CONST_ALPHA 0x8
#define BRW_BLENDFACTOR_SRC1_COLOR 0x9
#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A
#define BRW_BLENDFACTOR_ZERO 0x11
#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12
#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13
#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14
#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15
#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17
#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18
#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19
#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
#define BRW_BLENDFUNCTION_ADD 0
#define BRW_BLENDFUNCTION_SUBTRACT 1
#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2
#define BRW_BLENDFUNCTION_MIN 3
#define BRW_BLENDFUNCTION_MAX 4
#define BRW_ALPHATEST_FORMAT_UNORM8 0
#define BRW_ALPHATEST_FORMAT_FLOAT32 1
#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0
#define BRW_CHROMAKEY_REPLACE_BLACK 1
#define BRW_CLIP_API_OGL 0
#define BRW_CLIP_API_DX 1
#define BRW_CLIPMODE_NORMAL 0
#define BRW_CLIPMODE_CLIP_ALL 1
#define BRW_CLIPMODE_CLIP_NON_REJECTED 2
#define BRW_CLIPMODE_REJECT_ALL 3
#define BRW_CLIPMODE_ACCEPT_ALL 4
#define BRW_CLIP_NDCSPACE 0
#define BRW_CLIP_SCREENSPACE 1
#define BRW_COMPAREFUNCTION_ALWAYS 0
#define BRW_COMPAREFUNCTION_NEVER 1
#define BRW_COMPAREFUNCTION_LESS 2
#define BRW_COMPAREFUNCTION_EQUAL 3
#define BRW_COMPAREFUNCTION_LEQUAL 4
#define BRW_COMPAREFUNCTION_GREATER 5
#define BRW_COMPAREFUNCTION_NOTEQUAL 6
#define BRW_COMPAREFUNCTION_GEQUAL 7
#define BRW_COVERAGE_PIXELS_HALF 0
#define BRW_COVERAGE_PIXELS_1 1
#define BRW_COVERAGE_PIXELS_2 2
#define BRW_COVERAGE_PIXELS_4 3
#define BRW_CULLMODE_BOTH 0
#define BRW_CULLMODE_NONE 1
#define BRW_CULLMODE_FRONT 2
#define BRW_CULLMODE_BACK 3
#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0
#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1
#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
#define BRW_DEPTHFORMAT_D32_FLOAT 1
#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2
#define BRW_DEPTHFORMAT_D16_UNORM 5
#define BRW_FLOATING_POINT_IEEE_754 0
#define BRW_FLOATING_POINT_NON_IEEE_754 1
#define BRW_FRONTWINDING_CW 0
#define BRW_FRONTWINDING_CCW 1
#define BRW_INDEX_BYTE 0
#define BRW_INDEX_WORD 1
#define BRW_INDEX_DWORD 2
#define BRW_LOGICOPFUNCTION_CLEAR 0
#define BRW_LOGICOPFUNCTION_NOR 1
#define BRW_LOGICOPFUNCTION_AND_INVERTED 2
#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3
#define BRW_LOGICOPFUNCTION_AND_REVERSE 4
#define BRW_LOGICOPFUNCTION_INVERT 5
#define BRW_LOGICOPFUNCTION_XOR 6
#define BRW_LOGICOPFUNCTION_NAND 7
#define BRW_LOGICOPFUNCTION_AND 8
#define BRW_LOGICOPFUNCTION_EQUIV 9
#define BRW_LOGICOPFUNCTION_NOOP 10
#define BRW_LOGICOPFUNCTION_OR_INVERTED 11
#define BRW_LOGICOPFUNCTION_COPY 12
#define BRW_LOGICOPFUNCTION_OR_REVERSE 13
#define BRW_LOGICOPFUNCTION_OR 14
#define BRW_LOGICOPFUNCTION_SET 15
#define BRW_MAPFILTER_NEAREST 0x0
#define BRW_MAPFILTER_LINEAR 0x1
#define BRW_MAPFILTER_ANISOTROPIC 0x2
#define BRW_MIPFILTER_NONE 0
#define BRW_MIPFILTER_NEAREST 1
#define BRW_MIPFILTER_LINEAR 3
#define BRW_POLYGON_FRONT_FACING 0
#define BRW_POLYGON_BACK_FACING 1
#define BRW_PREFILTER_ALWAYS 0x0
#define BRW_PREFILTER_NEVER 0x1
#define BRW_PREFILTER_LESS 0x2
#define BRW_PREFILTER_EQUAL 0x3
#define BRW_PREFILTER_LEQUAL 0x4
#define BRW_PREFILTER_GREATER 0x5
#define BRW_PREFILTER_NOTEQUAL 0x6
#define BRW_PREFILTER_GEQUAL 0x7
#define BRW_PROVOKING_VERTEX_0 0
#define BRW_PROVOKING_VERTEX_1 1
#define BRW_PROVOKING_VERTEX_2 2
#define BRW_RASTRULE_UPPER_LEFT 0
#define BRW_RASTRULE_UPPER_RIGHT 1
#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0
#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1
#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2
#define BRW_STENCILOP_KEEP 0
#define BRW_STENCILOP_ZERO 1
#define BRW_STENCILOP_REPLACE 2
#define BRW_STENCILOP_INCRSAT 3
#define BRW_STENCILOP_DECRSAT 4
#define BRW_STENCILOP_INCR 5
#define BRW_STENCILOP_DECR 6
#define BRW_STENCILOP_INVERT 7
#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0
#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1
#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000
#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001
#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002
#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003
#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004
#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005
#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006
#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007
#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008
#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040
#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041
#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042
#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043
#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044
#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045
#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046
#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080
#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081
#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082
#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083
#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084
#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085
#define BRW_SURFACEFORMAT_R32G32_SINT 0x086
#define BRW_SURFACEFORMAT_R32G32_UINT 0x087
#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088
#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089
#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A
#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B
#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C
#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D
#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E
#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F
#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090
#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091
#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092
#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093
#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094
#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095
#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3
#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4
#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8
#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9
#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA
#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB
#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC
#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD
#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE
#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF
#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2
#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3
#define BRW_SURFACEFORMAT_R32_SINT 0x0D6
#define BRW_SURFACEFORMAT_R32_UINT 0x0D7
#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8
#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9
#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA
#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF
#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0
#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1
#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2
#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3
#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4
#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC
#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED
#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE
#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0
#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1
#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2
#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3
#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4
#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5
#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6
#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7
#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8
#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9
#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100
#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105
#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106
#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107
#define BRW_SURFACEFORMAT_R8G8_SINT 0x108
#define BRW_SURFACEFORMAT_R8G8_UINT 0x109
#define BRW_SURFACEFORMAT_R16_UNORM 0x10A
#define BRW_SURFACEFORMAT_R16_SNORM 0x10B
#define BRW_SURFACEFORMAT_R16_SINT 0x10C
#define BRW_SURFACEFORMAT_R16_UINT 0x10D
#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E
#define BRW_SURFACEFORMAT_I16_UNORM 0x111
#define BRW_SURFACEFORMAT_L16_UNORM 0x112
#define BRW_SURFACEFORMAT_A16_UNORM 0x113
#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114
#define BRW_SURFACEFORMAT_I16_FLOAT 0x115
#define BRW_SURFACEFORMAT_L16_FLOAT 0x116
#define BRW_SURFACEFORMAT_A16_FLOAT 0x117
#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B
#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C
#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D
#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E
#define BRW_SURFACEFORMAT_R16_USCALED 0x11F
#define BRW_SURFACEFORMAT_R8_UNORM 0x140
#define BRW_SURFACEFORMAT_R8_SNORM 0x141
#define BRW_SURFACEFORMAT_R8_SINT 0x142
#define BRW_SURFACEFORMAT_R8_UINT 0x143
#define BRW_SURFACEFORMAT_A8_UNORM 0x144
#define BRW_SURFACEFORMAT_I8_UNORM 0x145
#define BRW_SURFACEFORMAT_L8_UNORM 0x146
#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147
#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148
#define BRW_SURFACEFORMAT_R8_SSCALED 0x149
#define BRW_SURFACEFORMAT_R8_USCALED 0x14A
#define BRW_SURFACEFORMAT_R1_UINT 0x181
#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182
#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183
#define BRW_SURFACEFORMAT_BC1_UNORM 0x186
#define BRW_SURFACEFORMAT_BC2_UNORM 0x187
#define BRW_SURFACEFORMAT_BC3_UNORM 0x188
#define BRW_SURFACEFORMAT_BC4_UNORM 0x189
#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A
#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B
#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C
#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D
#define BRW_SURFACEFORMAT_MONO8 0x18E
#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F
#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190
#define BRW_SURFACEFORMAT_DXT1_RGB 0x191
#define BRW_SURFACEFORMAT_FXT1 0x192
#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193
#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194
#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195
#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196
#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197
#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198
#define BRW_SURFACEFORMAT_BC4_SNORM 0x199
#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A
#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C
#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D
#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F
#define BRW_SURFACERETURNFORMAT_FLOAT32 0
#define BRW_SURFACERETURNFORMAT_S1 1
#define BRW_SURFACE_1D 0
#define BRW_SURFACE_2D 1
#define BRW_SURFACE_3D 2
#define BRW_SURFACE_CUBE 3
#define BRW_SURFACE_BUFFER 4
#define BRW_SURFACE_NULL 7
#define BRW_TEXCOORDMODE_WRAP 0
#define BRW_TEXCOORDMODE_MIRROR 1
#define BRW_TEXCOORDMODE_CLAMP 2
#define BRW_TEXCOORDMODE_CUBE 3
#define BRW_TEXCOORDMODE_CLAMP_BORDER 4
#define BRW_TEXCOORDMODE_MIRROR_ONCE 5
#define BRW_THREAD_PRIORITY_NORMAL 0
#define BRW_THREAD_PRIORITY_HIGH 1
#define BRW_TILEWALK_XMAJOR 0
#define BRW_TILEWALK_YMAJOR 1
#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0
#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1
#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0
#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1
#define BRW_VFCOMPONENT_NOSTORE 0
#define BRW_VFCOMPONENT_STORE_SRC 1
#define BRW_VFCOMPONENT_STORE_0 2
#define BRW_VFCOMPONENT_STORE_1_FLT 3
#define BRW_VFCOMPONENT_STORE_1_INT 4
#define BRW_VFCOMPONENT_STORE_VID 5
#define BRW_VFCOMPONENT_STORE_IID 6
#define BRW_VFCOMPONENT_STORE_PID 7
/* Execution Unit (EU) defines
*/
#define BRW_ALIGN_1 0
#define BRW_ALIGN_16 1
#define BRW_ADDRESS_DIRECT 0
#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
#define BRW_CHANNEL_X 0
#define BRW_CHANNEL_Y 1
#define BRW_CHANNEL_Z 2
#define BRW_CHANNEL_W 3
#define BRW_COMPRESSION_NONE 0
#define BRW_COMPRESSION_2NDHALF 1
#define BRW_COMPRESSION_COMPRESSED 2
#define BRW_CONDITIONAL_NONE 0
#define BRW_CONDITIONAL_Z 1
#define BRW_CONDITIONAL_NZ 2
#define BRW_CONDITIONAL_EQ 1 /* Z */
#define BRW_CONDITIONAL_NEQ 2 /* NZ */
#define BRW_CONDITIONAL_G 3
#define BRW_CONDITIONAL_GE 4
#define BRW_CONDITIONAL_L 5
#define BRW_CONDITIONAL_LE 6
#define BRW_CONDITIONAL_C 7
#define BRW_CONDITIONAL_O 8
#define BRW_DEBUG_NONE 0
#define BRW_DEBUG_BREAKPOINT 1
#define BRW_DEPENDENCY_NORMAL 0
#define BRW_DEPENDENCY_NOTCLEARED 1
#define BRW_DEPENDENCY_NOTCHECKED 2
#define BRW_DEPENDENCY_DISABLE 3
#define BRW_EXECUTE_1 0
#define BRW_EXECUTE_2 1
#define BRW_EXECUTE_4 2
#define BRW_EXECUTE_8 3
#define BRW_EXECUTE_16 4
#define BRW_EXECUTE_32 5
#define BRW_HORIZONTAL_STRIDE_0 0
#define BRW_HORIZONTAL_STRIDE_1 1
#define BRW_HORIZONTAL_STRIDE_2 2
#define BRW_HORIZONTAL_STRIDE_4 3
#define BRW_INSTRUCTION_NORMAL 0
#define BRW_INSTRUCTION_SATURATE 1
#define BRW_MASK_ENABLE 0
#define BRW_MASK_DISABLE 1
#define BRW_OPCODE_MOV 1
#define BRW_OPCODE_SEL 2
#define BRW_OPCODE_NOT 4
#define BRW_OPCODE_AND 5
#define BRW_OPCODE_OR 6
#define BRW_OPCODE_XOR 7
#define BRW_OPCODE_SHR 8
#define BRW_OPCODE_SHL 9
#define BRW_OPCODE_RSR 10
#define BRW_OPCODE_RSL 11
#define BRW_OPCODE_ASR 12
#define BRW_OPCODE_CMP 16
#define BRW_OPCODE_JMPI 32
#define BRW_OPCODE_IF 34
#define BRW_OPCODE_IFF 35
#define BRW_OPCODE_ELSE 36
#define BRW_OPCODE_ENDIF 37
#define BRW_OPCODE_DO 38
#define BRW_OPCODE_WHILE 39
#define BRW_OPCODE_BREAK 40
#define BRW_OPCODE_CONTINUE 41
#define BRW_OPCODE_HALT 42
#define BRW_OPCODE_MSAVE 44
#define BRW_OPCODE_MRESTORE 45
#define BRW_OPCODE_PUSH 46
#define BRW_OPCODE_POP 47
#define BRW_OPCODE_WAIT 48
#define BRW_OPCODE_SEND 49
#define BRW_OPCODE_ADD 64
#define BRW_OPCODE_MUL 65
#define BRW_OPCODE_AVG 66
#define BRW_OPCODE_FRC 67
#define BRW_OPCODE_RNDU 68
#define BRW_OPCODE_RNDD 69
#define BRW_OPCODE_RNDE 70
#define BRW_OPCODE_RNDZ 71
#define BRW_OPCODE_MAC 72
#define BRW_OPCODE_MACH 73
#define BRW_OPCODE_LZD 74
#define BRW_OPCODE_SAD2 80
#define BRW_OPCODE_SADA2 81
#define BRW_OPCODE_DP4 84
#define BRW_OPCODE_DPH 85
#define BRW_OPCODE_DP3 86
#define BRW_OPCODE_DP2 87
#define BRW_OPCODE_DPA2 88
#define BRW_OPCODE_LINE 89
#define BRW_OPCODE_NOP 126
#define BRW_PREDICATE_NONE 0
#define BRW_PREDICATE_NORMAL 1
#define BRW_PREDICATE_ALIGN1_ANYV 2
#define BRW_PREDICATE_ALIGN1_ALLV 3
#define BRW_PREDICATE_ALIGN1_ANY2H 4
#define BRW_PREDICATE_ALIGN1_ALL2H 5
#define BRW_PREDICATE_ALIGN1_ANY4H 6
#define BRW_PREDICATE_ALIGN1_ALL4H 7
#define BRW_PREDICATE_ALIGN1_ANY8H 8
#define BRW_PREDICATE_ALIGN1_ALL8H 9
#define BRW_PREDICATE_ALIGN1_ANY16H 10
#define BRW_PREDICATE_ALIGN1_ALL16H 11
#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5
#define BRW_PREDICATE_ALIGN16_ANY4H 6
#define BRW_PREDICATE_ALIGN16_ALL4H 7
#define BRW_ARCHITECTURE_REGISTER_FILE 0
#define BRW_GENERAL_REGISTER_FILE 1
#define BRW_MESSAGE_REGISTER_FILE 2
#define BRW_IMMEDIATE_VALUE 3
#define BRW_REGISTER_TYPE_UD 0
#define BRW_REGISTER_TYPE_D 1
#define BRW_REGISTER_TYPE_UW 2
#define BRW_REGISTER_TYPE_W 3
#define BRW_REGISTER_TYPE_UB 4
#define BRW_REGISTER_TYPE_B 5
#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */
#define BRW_REGISTER_TYPE_HF 6
#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
#define BRW_REGISTER_TYPE_F 7
#define BRW_ARF_NULL 0x00
#define BRW_ARF_ADDRESS 0x10
#define BRW_ARF_ACCUMULATOR 0x20
#define BRW_ARF_FLAG 0x30
#define BRW_ARF_MASK 0x40
#define BRW_ARF_MASK_STACK 0x50
#define BRW_ARF_MASK_STACK_DEPTH 0x60
#define BRW_ARF_STATE 0x70
#define BRW_ARF_CONTROL 0x80
#define BRW_ARF_NOTIFICATION_COUNT 0x90
#define BRW_ARF_IP 0xA0
#define BRW_AMASK 0
#define BRW_IMASK 1
#define BRW_LMASK 2
#define BRW_CMASK 3
#define BRW_THREAD_NORMAL 0
#define BRW_THREAD_ATOMIC 1
#define BRW_THREAD_SWITCH 2
#define BRW_VERTICAL_STRIDE_0 0
#define BRW_VERTICAL_STRIDE_1 1
#define BRW_VERTICAL_STRIDE_2 2
#define BRW_VERTICAL_STRIDE_4 3
#define BRW_VERTICAL_STRIDE_8 4
#define BRW_VERTICAL_STRIDE_16 5
#define BRW_VERTICAL_STRIDE_32 6
#define BRW_VERTICAL_STRIDE_64 7
#define BRW_VERTICAL_STRIDE_128 8
#define BRW_VERTICAL_STRIDE_256 9
#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
#define BRW_WIDTH_1 0
#define BRW_WIDTH_2 1
#define BRW_WIDTH_4 2
#define BRW_WIDTH_8 3
#define BRW_WIDTH_16 4
#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0
#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1
#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2
#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3
#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4
#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5
#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6
#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7
#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8
#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9
#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10
#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11
#define BRW_POLYGON_FACING_FRONT 0
#define BRW_POLYGON_FACING_BACK 1
#define BRW_MESSAGE_TARGET_NULL 0
#define BRW_MESSAGE_TARGET_MATH 1
#define BRW_MESSAGE_TARGET_SAMPLER 2
#define BRW_MESSAGE_TARGET_GATEWAY 3
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5
#define BRW_MESSAGE_TARGET_URB 6
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2
#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
#define BRW_MATH_FUNCTION_INV 1
#define BRW_MATH_FUNCTION_LOG 2
#define BRW_MATH_FUNCTION_EXP 3
#define BRW_MATH_FUNCTION_SQRT 4
#define BRW_MATH_FUNCTION_RSQ 5
#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
#define BRW_MATH_FUNCTION_TAN 9
#define BRW_MATH_FUNCTION_POW 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
#define BRW_MATH_INTEGER_UNSIGNED 0
#define BRW_MATH_INTEGER_SIGNED 1
#define BRW_MATH_PRECISION_FULL 0
#define BRW_MATH_PRECISION_PARTIAL 1
#define BRW_MATH_SATURATE_NONE 0
#define BRW_MATH_SATURATE_SATURATE 1
#define BRW_MATH_DATA_VECTOR 0
#define BRW_MATH_DATA_SCALAR 1
#define BRW_URB_OPCODE_WRITE 0
#define BRW_URB_SWIZZLE_NONE 0
#define BRW_URB_SWIZZLE_INTERLEAVE 1
#define BRW_URB_SWIZZLE_TRANSPOSE 2
#define BRW_SCRATCH_SPACE_SIZE_1K 0
#define BRW_SCRATCH_SPACE_SIZE_2K 1
#define BRW_SCRATCH_SPACE_SIZE_4K 2
#define BRW_SCRATCH_SPACE_SIZE_8K 3
#define BRW_SCRATCH_SPACE_SIZE_16K 4
#define BRW_SCRATCH_SPACE_SIZE_32K 5
#define BRW_SCRATCH_SPACE_SIZE_64K 6
#define BRW_SCRATCH_SPACE_SIZE_128K 7
#define BRW_SCRATCH_SPACE_SIZE_256K 8
#define BRW_SCRATCH_SPACE_SIZE_512K 9
#define BRW_SCRATCH_SPACE_SIZE_1M 10
#define BRW_SCRATCH_SPACE_SIZE_2M 11
#define CMD_URB_FENCE 0x6000
#define CMD_CONST_BUFFER_STATE 0x6001
#define CMD_CONST_BUFFER 0x6002
#define CMD_STATE_BASE_ADDRESS 0x6101
#define CMD_STATE_INSN_POINTER 0x6102
#define CMD_PIPELINE_SELECT 0x6104
#define CMD_PIPELINED_STATE_POINTERS 0x7800
#define CMD_BINDING_TABLE_PTRS 0x7801
#define CMD_VERTEX_BUFFER 0x7808
#define CMD_VERTEX_ELEMENT 0x7809
#define CMD_INDEX_BUFFER 0x780a
#define CMD_VF_STATISTICS 0x780b
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
#define CMD_CHROMA_KEY 0x7904
#define CMD_DEPTH_BUFFER 0x7905
#define CMD_POLY_STIPPLE_OFFSET 0x7906
#define CMD_POLY_STIPPLE_PATTERN 0x7907
#define CMD_LINE_STIPPLE_PATTERN 0x7908
#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908
#define CMD_PIPE_CONTROL 0x7a00
#define CMD_3D_PRIM 0x7b00
#define CMD_MI_FLUSH 0x0200
/* Various values from the R0 vertex header:
*/
#define R02_PRIM_END 0x1
#define R02_PRIM_START 0x2
#endif

1340
src/brw_structs.h Normal file
View File

File diff suppressed because it is too large Load Diff

35
src/common.h
View File

@ -130,13 +130,17 @@ extern void I830DPRINTF_stub(const char *filename, int line,
#define ADVANCE_LP_RING() do { \
if (ringused > needed) \
ErrorF("%s: ADVANCE_LP_RING: exceeded allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
FatalError("%s: ADVANCE_LP_RING: exceeded allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
else if (ringused < needed) \
FatalError("%s: ADVANCE_LP_RING: under-used allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
RecPtr->LpRing->tail = outring; \
RecPtr->LpRing->space -= ringused; \
if (outring & 0x07) \
ErrorF("ADVANCE_LP_RING: " \
"outring (0x%x) isn't on a QWord boundary\n", outring); \
FatalError("%s: ADVANCE_LP_RING: " \
"outring (0x%x) isn't on a QWord boundary\n", \
__FUNCTION__, outring); \
OUTREG(LP_RING + RING_TAIL, outring); \
} while (0)
@ -277,6 +281,26 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
#endif
#ifndef PCI_CHIP_I965_G_1
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_Q_BRIDGE 0x2990
#endif
#ifndef PCI_CHIP_I965_G
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_G_BRIDGE 0x29A0
#endif
#ifndef PCI_CHIP_I946_GZ
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I946_GZ_BRIDGE 0x2970
#endif
#define IS_I810(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I810 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_DC100 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_E)
@ -292,7 +316,8 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_GM)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810))
#define IS_I965G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_G || pI810->PciInfo->chipType == PCI_CHIP_I965_G_1 || pI810->PciInfo->chipType == PCI_CHIP_I965_Q || pI810->PciInfo->chipType == PCI_CHIP_I946_GZ)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810))
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))

4
src/i810.h
View File

@ -64,10 +64,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I810_VERSION 4000
#define I810_NAME "I810"
#define I810_DRIVER_NAME "i810"
#define I810_MAJOR_VERSION 1
#define I810_MINOR_VERSION 6
#define I810_PATCHLEVEL 0
/* HWMC Surfaces */
#define I810_MAX_SURFACES 7

4
src/i810_dri.h
View File

@ -8,6 +8,10 @@
#define I810_MAX_DRAWABLES 256
#define I810_MAJOR_VERSION 1
#define I810_MINOR_VERSION 6
#define I810_PATCHLEVEL 3
typedef struct {
drm_handle_t regs;
drmSize regsSize;

21
src/i810_driver.c
View File

@ -140,6 +140,10 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I915_GM, "915GM"},
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_I965_G_1, "965G"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{-1, NULL}
};
@ -159,6 +163,10 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@ -324,14 +332,13 @@ const char *I810driSymbols[] = {
"DRICreatePCIBusID",
NULL
};
#endif
#endif /* I830_ONLY */
const char *I810shadowSymbols[] = {
"shadowInit",
"shadowSetup",
"shadowAdd",
"shadowRemove",
"shadowUpdateRotatePacked",
NULL
};
@ -372,7 +379,7 @@ static XF86ModuleVersionInfo i810VersRec = {
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
I810_MAJOR_VERSION, I810_MINOR_VERSION, I810_PATCHLEVEL,
INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_VIDEODRV,
@ -401,9 +408,9 @@ i810Setup(pointer module, pointer opts, int *errmaj, int *errmin)
#ifdef XF86DRI
I810drmSymbols,
I810driSymbols,
#endif
I810shadowSymbols,
I810shadowFBSymbols,
#endif
I810vbeSymbols, vbeOptionalSymbols,
I810ddcSymbols, I810int10Symbols, NULL);
@ -578,6 +585,10 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I915_GM:
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_G_1:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */

323
src/i810_reg.h
View File

@ -293,8 +293,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STATE_VAR_UPDATE_DISABLE 0x02
#define PAL_STIP_DISABLE 0x01
#define INST_DONE 0x2090
#define INST_PS 0x20c4
#define MEMMODE 0x20dc
@ -303,6 +301,66 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define IPEIR 0x2088
#define IPEHR 0x208C
#define INST_DONE 0x2090
#define INST_PS 0x20c4
#define IPEIR_I965 0x2064 /* i965 */
#define IPEHR_I965 0x2068 /* i965 */
#define INST_DONE_I965 0x206c
#define INST_PS_I965 0x2070
#define ACTHD 0x2074
#define DMA_FADD_P 0x2078
#define INST_DONE_1 0x207c
#define CACHE_MODE_0 0x2120
#define CACHE_MODE_1 0x2124
#define MI_ARB_STATE 0x20e4
#define WIZ_CTL 0x7c00
#define WIZ_CTL_SINGLE_SUBSPAN (1<<6)
#define WIZ_CTL_IGNORE_STALLS (1<<5)
#define SVG_WORK_CTL 0x7408
#define TS_CTL 0x7e00
#define TS_MUX_ERR_CODE (0<<8)
#define TS_MUX_URB_0 (1<<8)
#define TS_MUX_DISPATCH_ID_0 (10<<8)
#define TS_MUX_ERR_CODE_VALID (15<<8)
#define TS_MUX_TID_0 (16<<8)
#define TS_MUX_EUID_0 (18<<8)
#define TS_MUX_FFID_0 (22<<8)
#define TS_MUX_EOT (26<<8)
#define TS_MUX_SIDEBAND_0 (27<<8)
#define TS_SNAP_ALL_CHILD (1<<2)
#define TS_SNAP_ALL_ROOT (1<<1)
#define TS_SNAP_ENABLE (1<<0)
#define TS_DEBUG_DATA 0x7e0c
#define TD_CTL 0x8000
#define TD_CTL2 0x8004
#define ECOSKPD 0x21d0
#define EXCC 0x2028
/* I965 debug regs:
*/
#define IA_VERTICES_COUNT_QW 0x2310
#define IA_PRIMITIVES_COUNT_QW 0x2318
#define VS_INVOCATION_COUNT_QW 0x2320
#define GS_INVOCATION_COUNT_QW 0x2328
#define GS_PRIMITIVES_COUNT_QW 0x2330
#define CL_INVOCATION_COUNT_QW 0x2338
#define CL_PRIMITIVES_COUNT_QW 0x2340
#define PS_INVOCATION_COUNT_QW 0x2348
#define PS_DEPTH_COUNT_QW 0x2350
#define TIMESTAMP_QW 0x2358
#define CLKCMP_QW 0x2360
/* General error reporting regs, p296
@ -366,6 +424,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FENCE 0x2000
#define FENCE_NR 8
#define FENCE_NEW 0x3000
#define FENCE_NEW_NR 16
#define FENCE_LINEAR 0
#define FENCE_XMAJOR 1
#define FENCE_YMAJOR 2
#define I915G_FENCE_START_MASK 0x0ff00000
#define I830_FENCE_START_MASK 0x07f80000
@ -772,6 +837,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DSPBPOS 0x7118C
#define DSPBSIZE 0x71190
#define DSPASURF 0x7019C
#define DSPATILEOFF 0x701A4
#define DSPBSURF 0x7119C
#define DSPBTILEOFF 0x711A4
/* Various masks for reserved bits, etc. */
#define I830_FWATER1_MASK (~((1<<11)|(1<<10)|(1<<9)| \
(1<<8)|(1<<26)|(1<<25)|(1<<24)|(1<<5)|(1<<4)|(1<<3)| \
@ -866,15 +937,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
/* 3d state */
#define STATE3D_FOG_MODE ((3<<29)|(0x1d<<24)|(0x89<<16)|2)
#define FOG_MODE_VERTEX (1<<31)
#define STATE3D_MAP_COORD_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8c<<16))
#define DISABLE_TEX_TRANSFORM (1<<28)
#define TEXTURE_SET(x) (x<<29)
#define STATE3D_RASTERIZATION_RULES ((3<<29)|(0x07<<24))
#define POINT_RASTER_ENABLE (1<<15)
#define POINT_RASTER_OGL (1<<13)
#define STATE3D_VERTEX_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8b<<16))
#define DISABLE_VIEWPORT_TRANSFORM (1<<31)
#define DISABLE_PERSPECTIVE_DIVIDE (1<<29)
@ -907,7 +975,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_WRITE_DIRTY_STATE (1<<4)
#define MI_END_SCENE (1<<3)
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2)
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
#define MI_INVALIDATE_MAP_CACHE (1<<0)
/* broadwater flush bits */
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3)
/* Noop */
#define MI_NOOP 0x00
@ -921,6 +992,244 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define ENABLE_FOG_CONST (1<<24)
#define ENABLE_FOG_DENSITY (1<<23)
/*
* New regs for broadwater -- we need to split this file up sensibly somehow.
*/
#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
((Pipeline) << 27) | \
((Opcode) << 24) | \
((Subopcode) << 16))
#define BRW_URB_FENCE BRW_3D(0, 0, 0)
#define BRW_CS_URB_STATE BRW_3D(0, 0, 1)
#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2)
#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3)
#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1)
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0)
#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1)
#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8)
#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9)
#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa)
#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb)
#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0)
#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1)
#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2)
#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4)
#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5)
#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6)
#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7)
#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8)
#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9)
/* These two are BLC and CTG only, not BW or CL */
#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa)
#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb)
#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0)
#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0)
#define PIPELINE_SELECT_3D 0
#define PIPELINE_SELECT_MEDIA 1
#define UF0_CS_REALLOC (1 << 13)
#define UF0_VFE_REALLOC (1 << 12)
#define UF0_SF_REALLOC (1 << 11)
#define UF0_CLIP_REALLOC (1 << 10)
#define UF0_GS_REALLOC (1 << 9)
#define UF0_VS_REALLOC (1 << 8)
#define UF1_CLIP_FENCE_SHIFT 20
#define UF1_GS_FENCE_SHIFT 10
#define UF1_VS_FENCE_SHIFT 0
#define UF2_CS_FENCE_SHIFT 20
#define UF2_VFE_FENCE_SHIFT 10
#define UF2_SF_FENCE_SHIFT 0
/* for BRW_STATE_BASE_ADDRESS */
#define BASE_ADDRESS_MODIFY (1 << 0)
/* for BRW_3DSTATE_PIPELINED_POINTERS */
#define BRW_GS_DISABLE 0
#define BRW_GS_ENABLE 1
#define BRW_CLIP_DISABLE 0
#define BRW_CLIP_ENABLE 1
/* for BRW_PIPE_CONTROL */
#define BRW_PIPE_CONTROL_NOWRITE (0 << 14)
#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14)
#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14)
#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13)
#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12)
#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11)
#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
/* VERTEX_BUFFER_STATE Structure */
#define VB0_BUFFER_INDEX_SHIFT 27
#define VB0_VERTEXDATA (0 << 26)
#define VB0_INSTANCEDATA (1 << 26)
#define VB0_BUFFER_PITCH_SHIFT 0
/* VERTEX_ELEMENT_STATE Structure */
#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27
#define VE0_VALID (1 << 26)
#define VE0_FORMAT_SHIFT 16
#define VE0_OFFSET_SHIFT 0
#define VE1_VFCOMPONENT_0_SHIFT 28
#define VE1_VFCOMPONENT_1_SHIFT 24
#define VE1_VFCOMPONENT_2_SHIFT 20
#define VE1_VFCOMPONENT_3_SHIFT 16
#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0
/* 3DPRIMITIVE bits */
#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15)
/* Primitive types are in brw_defines.h */
#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10
#define BRW_SVG_CTL 0x7400
#define BRW_SVG_CTL_GS_BA (0 << 8)
#define BRW_SVG_CTL_SS_BA (1 << 8)
#define BRW_SVG_CTL_IO_BA (2 << 8)
#define BRW_SVG_CTL_GS_AUB (3 << 8)
#define BRW_SVG_CTL_IO_AUB (4 << 8)
#define BRW_SVG_CTL_SIP (5 << 8)
#define BRW_SVG_RDATA 0x7404
#define BRW_SVG_WORK_CTL 0x7408
#define BRW_VF_CTL 0x7500
#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8)
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8)
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4)
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4)
#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3)
#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2)
#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1)
#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_VF_STRG_VAL 0x7504
#define BRW_VF_STR_VL_OVR 0x7508
#define BRW_VF_VC_OVR 0x750c
#define BRW_VF_STR_PSKIP 0x7510
#define BRW_VF_MAX_PRIM 0x7514
#define BRW_VF_RDATA 0x7518
#define BRW_VS_CTL 0x7600
#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8)
#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_VS_STRG_VAL 0x7604
#define BRW_VS_RDATA 0x7608
#define BRW_SF_CTL 0x7b00
#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8)
#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4)
#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3)
#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_SF_STRG_VAL 0x7b04
#define BRW_SF_RDATA 0x7b18
#define BRW_WIZ_CTL 0x7c00
#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16
#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8)
#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8)
#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)
#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6)
#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5)
#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4)
#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3)
#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_WIZ_STRG_VAL 0x7c04
#define BRW_WIZ_RDATA 0x7c18
#define BRW_TS_CTL 0x7e00
#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8)
#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8)
#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2)
#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1)
#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_TS_STRG_VAL 0x7e04
#define BRW_TS_RDATA 0x7e08
#define BRW_TD_CTL 0x8000
#define BRW_TD_CTL_MUX_SHIFT 8
#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7)
#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6)
#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5)
#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4)
#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2)
#define BRW_TD_CTL2 0x8004
#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28)
#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26)
#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25)
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8)
#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7)
#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6)
#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5)
#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4)
#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3)
#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0)
#define BRW_TD_VF_VS_EMSK 0x8008
#define BRW_TD_GS_EMSK 0x800c
#define BRW_TD_CLIP_EMSK 0x8010
#define BRW_TD_SF_EMSK 0x8014
#define BRW_TD_WIZ_EMSK 0x8018
#define BRW_TD_0_6_EHTRG_VAL 0x801c
#define BRW_TD_0_7_EHTRG_VAL 0x8020
#define BRW_TD_0_6_EHTRG_MSK 0x8024
#define BRW_TD_0_7_EHTRG_MSK 0x8028
#define BRW_TD_RDATA 0x802c
#define BRW_TD_TS_EMSK 0x8030
#define BRW_EU_CTL 0x8800
#define BRW_EU_CTL_SELECT_SHIFT 16
#define BRW_EU_CTL_DATA_MUX_SHIFT 8
#define BRW_EU_ATT_0 0x8810
#define BRW_EU_ATT_1 0x8814
#define BRW_EU_ATT_DATA_0 0x8820
#define BRW_EU_ATT_DATA_1 0x8824
#define BRW_EU_ATT_CLR_0 0x8830
#define BRW_EU_ATT_CLR_1 0x8834
#define BRW_EU_RDATA 0x8840
/* End regs for broadwater */
#define MAX_DISPLAY_PIPES 2

67
src/i830.h
View File

@ -47,6 +47,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef _I830_H_
#define _I830_H_
#include "xf86_OSproc.h"
#include "compiler.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
@ -56,6 +57,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "xf86xv.h"
#include "xf86int10.h"
#include "vbe.h"
#include "vbeModes.h"
#include "vgaHW.h"
#include "randrstr.h"
@ -79,6 +81,11 @@ Bool I830XAAInit(ScreenPtr pScreen);
#include "common.h"
#define NEED_REPLIES /* ? */
#define EXTENSION_PROC_ARGS void *
#include "extnsionst.h" /* required */
#include <X11/extensions/panoramiXproto.h> /* required */
/* I830 Video BIOS support */
/*
@ -102,7 +109,6 @@ typedef struct _VESARec {
int statePage, stateSize, stateMode, stateRefresh;
CARD32 *savedPal;
int savedScanlinePitch;
xf86MonPtr monitor;
/* Don't try to set the refresh rate for any modes. */
Bool useDefaultRefresh;
/* display start */
@ -150,7 +156,7 @@ typedef struct {
} I830RingBuffer;
typedef struct {
unsigned int Fence[8];
unsigned int Fence[FENCE_NEW_NR * 2];
} I830RegRec, *I830RegPtr;
typedef struct {
@ -164,6 +170,29 @@ typedef struct {
#endif
} I830EntRec, *I830EntPtr;
typedef struct _MergedDisplayModeRec {
DisplayModePtr First;
DisplayModePtr Second;
int SecondPosition;
} I830MergedDisplayModeRec, *I830MergedDisplayModePtr;
typedef struct _I830XineramaData {
int x;
int y;
int width;
int height;
} I830XineramaData;
typedef struct _ModePrivateRec {
I830MergedDisplayModeRec merged;
VbeModeInfoData vbeData;
} I830ModePrivateRec, *I830ModePrivatePtr;
typedef struct _region {
int x0,x1,y0,y1;
} region;
typedef struct _I830Rec {
unsigned char *MMIOBase;
unsigned char *FbBase;
@ -229,7 +258,25 @@ typedef struct _I830Rec {
I830MemRange *OverlayMem;
I830MemRange LinearMem;
#endif
unsigned int LinearAlloc;
int LinearAlloc;
Bool MergedFB;
ScrnInfoPtr pScrn_2;
char *SecondHSync;
char *SecondVRefresh;
char *MetaModes;
int SecondPosition;
int FirstXOffs, FirstYOffs, SecondXOffs, SecondYOffs;
int FirstframeX0, FirstframeX1, FirstframeY0, FirstframeY1;
int MBXNR1XMAX, MBXNR1YMAX, MBXNR2XMAX, MBXNR2YMAX;
Bool NonRect, HaveNonRect, HaveOffsRegions, MouseRestrictions;
int maxFirst_X1, maxFirst_X2, maxFirst_Y1, maxFirst_Y2;
int maxSecond_X1, maxSecond_X2, maxSecond_Y1, maxSecond_Y2;
region NonRectDead, OffDead1, OffDead2;
Bool IntelXinerama;
Bool SecondIsScrn0;
ExtensionEntry *XineramaExtEntry;
int I830XineramaVX, I830XineramaVY;
XF86ModReqInfo shadowReq; /* to test for later libshadow */
I830MemRange RotatedMem;
@ -249,6 +296,12 @@ typedef struct _I830Rec {
int TexGranularity;
int drmMinor;
Bool have3DWindows;
unsigned int front_tiled;
unsigned int back_tiled;
unsigned int depth_tiled;
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
#endif
Bool NeedRingBufferLow;
@ -397,6 +450,9 @@ typedef struct _I830Rec {
Bool devicePresence;
OsTimerPtr devicesTimer;
CARD32 savedAsurf;
CARD32 savedBsurf;
} I830Rec;
#define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
@ -411,6 +467,7 @@ extern int I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis);
extern void I830SetPIOAccess(I830Ptr pI830);
extern void I830SetMMIOAccess(I830Ptr pI830);
extern void I830PrintErrorState(ScrnInfoPtr pScrn);
extern void I965PrintErrorState(ScrnInfoPtr pScrn);
extern void I830Sync(ScrnInfoPtr pScrn);
extern void I830InitHWCursor(ScrnInfoPtr pScrn);
extern Bool I830CursorInit(ScreenPtr pScreen);
@ -471,8 +528,8 @@ extern long I830GetExcessMemoryAllocations(ScrnInfoPtr pScrn);
extern Bool I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags);
extern Bool I830DoPoolAllocation(ScrnInfoPtr pScrn, I830MemPool *pool);
extern Bool I830FixupOffsets(ScrnInfoPtr pScrn);
extern Bool I830BindGARTMemory(ScrnInfoPtr pScrn);
extern Bool I830UnbindGARTMemory(ScrnInfoPtr pScrn);
extern Bool I830BindAGPMemory(ScrnInfoPtr pScrn);
extern Bool I830UnbindAGPMemory(ScrnInfoPtr pScrn);
extern unsigned long I830AllocVidMem(ScrnInfoPtr pScrn, I830MemRange *result,
I830MemPool *pool, long size,
unsigned long alignment, int flags);

1
src/i830_3d.c
View File

@ -29,6 +29,7 @@
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i830_reg.h"

14
src/i830_accel.c
View File

@ -134,6 +134,7 @@ void
I830Sync(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
@ -148,13 +149,17 @@ I830Sync(ScrnInfoPtr pScrn)
if (pI830->entityPrivate && !pI830->entityPrivate->RingRunning) return;
if (IS_I965G(pI830))
flags = 0;
/* Send a flush instruction and then wait till the ring is empty.
* This is stronger than waiting for the blitter to finish as it also
* flushes the internal graphics caches.
*/
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@ -169,9 +174,13 @@ void
I830EmitFlush(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (IS_I965G(pI830))
flags = 0;
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@ -233,4 +242,3 @@ I830AccelInit(ScreenPtr pScreen)
#endif
return FALSE;
}

8
src/i830_common.h
View File

@ -84,7 +84,7 @@ typedef struct {
drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
int last_upload; /* last time texture was uploaded */
int last_enqueue; /* last time a buffer was enqueued */
int last_dispatch; /* age of the most recently dispatched buffer */
volatile int last_dispatch; /* age of the most recently dispatched buffer */
int ctxOwner; /* last context to upload state */
int texAge;
int pf_enabled; /* is pageflipping allowed? */
@ -115,6 +115,12 @@ typedef struct {
int rotated_size;
int rotated_pitch;
int virtualX, virtualY;
unsigned int front_tiled;
unsigned int back_tiled;
unsigned int depth_tiled;
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
} drmI830Sarea;
/* Flags for perf_boxes

218
src/i830_cursor.c
View File

@ -93,30 +93,47 @@ I830InitHWCursor(ScrnInfoPtr pScrn)
MCURSOR_PIPE_SELECT);
temp |= CURSOR_MODE_DISABLE;
temp |= (pI830->pipe << 28);
if(pI830->CursorIsARGB)
temp |= MCURSOR_GAMMA_ENABLE;
if (pI830->CursorIsARGB)
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_MODE_64_4C_AX;
/* Need to set control, then address. */
OUTREG(CURSOR_A_CONTROL, temp);
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
if (pI830->Clone) {
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Start);
}
if (pI830->Clone || pI830->MergedFB) {
temp &= ~MCURSOR_PIPE_SELECT;
temp |= (!pI830->pipe << 28);
OUTREG(CURSOR_B_CONTROL, temp);
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Start);
}
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
CURSOR_ENABLE | CURSOR_STRIDE_MASK);
temp |= (CURSOR_FORMAT_3C);
if (pI830->CursorIsARGB)
temp |= CURSOR_GAMMA_ENABLE;
temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_FORMAT_3C;
/* This initialises the format and leave the cursor disabled. */
OUTREG(CURSOR_CONTROL, temp);
/* Need to set address and size after disabling. */
@ -357,6 +374,102 @@ static void I830LoadCursorARGB (ScrnInfoPtr pScrn, CursorPtr pCurs)
}
#endif
#define CDMPTR ((I830ModePrivatePtr)pI830->currentMode->Private)->merged
static void
I830SetCursorPositionMerged(ScrnInfoPtr pScrn, int x, int y)
{
I830Ptr pI830 = I830PTR(pScrn);
ScrnInfoPtr pScrn2 = pI830->pScrn_2;
DisplayModePtr mode1 = CDMPTR.First;
Bool hide = FALSE, show = FALSE;
DisplayModePtr mode2 = CDMPTR.Second;
int x1, y1, x2, y2;
int total_y1 = pScrn->frameY1 - pScrn->frameY0;
int total_y2 = pScrn2->frameY1 - pScrn2->frameY0;
CARD32 temp = 0, temp2 = 0;
x += pScrn->frameX0;
y += pScrn->frameY0;
x1 = x - pI830->FirstframeX0;
y1 = y - pI830->FirstframeY0;
x2 = x - pScrn2->frameX0;
y2 = y - pScrn2->frameY0;
if (y1 > total_y1)
y1 = total_y1;
if (y2 > total_y2)
y2 = total_y2;
/* move cursor offscreen */
if (y1 >= 0 && y2 >= mode2->VDisplay) {
y2 = -I810_CURSOR_Y;
} else if (y2 >= 0 && y1 >= mode1->VDisplay) {
y1 = -I810_CURSOR_Y;
}
if (x1 >= 0 && x2 >= mode2->HDisplay) {
x2 = -I810_CURSOR_X;
} else if (x2 >= 0 && x1 >= mode1->HDisplay) {
x1 = -I810_CURSOR_X;
}
/* Clamp the cursor position to the visible screen area */
if (x1 >= mode1->HDisplay) x1 = mode1->HDisplay - 1;
if (y1 >= mode1->VDisplay) y1 = mode1->VDisplay - 1;
if (x1 <= -I810_CURSOR_X) x1 = -I810_CURSOR_X + 1;
if (y1 <= -I810_CURSOR_Y) y1 = -I810_CURSOR_Y + 1;
if (x2 >= mode2->HDisplay) x2 = mode2->HDisplay - 1;
if (y2 >= mode2->VDisplay) y2 = mode2->VDisplay - 1;
if (x2 <= -I810_CURSOR_X) x2 = -I810_CURSOR_X + 1;
if (y2 <= -I810_CURSOR_Y) y2 = -I810_CURSOR_Y + 1;
if (x1 < 0) {
temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
x1 = -x1;
}
if (y1 < 0) {
temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
y1 = -y1;
}
if (x2 < 0) {
temp2 |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
x2 = -x2;
}
if (y2 < 0) {
temp2 |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
y2 = -y2;
}
temp |= ((x1 & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
temp |= ((y1 & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
temp2 |= ((x2 & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
temp2 |= ((y2 & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
OUTREG(CURSOR_A_POSITION, temp);
OUTREG(CURSOR_B_POSITION, temp2);
if (pI830->cursorOn) {
if (hide)
pI830->CursorInfoRec->HideCursor(pScrn);
else if (show)
pI830->CursorInfoRec->ShowCursor(pScrn);
pI830->cursorOn = TRUE;
}
/* have to upload the base for the new position */
if (IS_I9XX(pI830)) {
if (pI830->CursorIsARGB) {
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
} else {
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
}
}
}
static void
I830SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
{
@ -369,6 +482,11 @@ I830SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
static Bool outsideViewport = FALSE;
#endif
if (pI830->MergedFB) {
I830SetCursorPositionMerged(pScrn, x, y);
return;
}
oldx += pScrn->frameX0; /* undo what xf86HWCurs did */
oldy += pScrn->frameY0;
@ -451,15 +569,29 @@ I830SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
/* have to upload the base for the new position */
if (IS_I9XX(pI830)) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
if (pI830->Clone) {
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Start);
}
if (pI830->Clone) {
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Start);
}
}
}
}
@ -483,7 +615,7 @@ I830ShowCursor(ScrnInfoPtr pScrn)
pI830->cursorOn = TRUE;
if (IS_MOBILE(pI830) || IS_I9XX(pI830)) {
temp = INREG(CURSOR_A_CONTROL);
temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT | MCURSOR_GAMMA_ENABLE);
if (pI830->CursorIsARGB)
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
else
@ -491,25 +623,39 @@ I830ShowCursor(ScrnInfoPtr pScrn)
temp |= (pI830->pipe << 28); /* Connect to correct pipe */
/* Need to set mode, then address. */
OUTREG(CURSOR_A_CONTROL, temp);
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
if (pI830->Clone) {
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Start);
}
if (pI830->Clone || pI830->MergedFB) {
temp &= ~MCURSOR_PIPE_SELECT;
temp |= (!pI830->pipe << 28);
OUTREG(CURSOR_B_CONTROL, temp);
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Start);
else
OUTREG(CURSOR_B_BASE, pI830->CursorMem->Start);
}
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_FORMAT_MASK);
temp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE);
temp |= CURSOR_ENABLE;
if (pI830->CursorIsARGB)
temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
temp |= CURSOR_FORMAT_ARGB;
else
temp |= CURSOR_FORMAT_3C;
OUTREG(CURSOR_CONTROL, temp);
@ -531,7 +677,7 @@ I830HideCursor(ScrnInfoPtr pScrn)
pI830->cursorOn = FALSE;
if (IS_MOBILE(pI830) || IS_I9XX(pI830)) {
temp = INREG(CURSOR_A_CONTROL);
temp &= ~(CURSOR_MODE|MCURSOR_GAMMA_ENABLE);
temp &= ~CURSOR_MODE;
temp |= CURSOR_MODE_DISABLE;
OUTREG(CURSOR_A_CONTROL, temp);
/* This is needed to flush the above change. */
@ -539,7 +685,7 @@ I830HideCursor(ScrnInfoPtr pScrn)
OUTREG(CURSOR_A_BASE, pI830->CursorMemARGB->Physical);
else
OUTREG(CURSOR_A_BASE, pI830->CursorMem->Physical);
if (pI830->Clone) {
if (pI830->Clone || pI830->MergedFB) {
OUTREG(CURSOR_B_CONTROL, temp);
if (pI830->CursorIsARGB)
OUTREG(CURSOR_B_BASE, pI830->CursorMemARGB->Physical);
@ -548,7 +694,7 @@ I830HideCursor(ScrnInfoPtr pScrn)
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_ENABLE|CURSOR_GAMMA_ENABLE);
temp &= ~CURSOR_ENABLE;
OUTREG(CURSOR_CONTROL, temp);
}
}
@ -570,7 +716,7 @@ I830SetCursorColors(ScrnInfoPtr pScrn, int bg, int fg)
OUTREG(CURSOR_A_PALETTE1, fg & 0x00ffffff);
OUTREG(CURSOR_A_PALETTE2, fg & 0x00ffffff);
OUTREG(CURSOR_A_PALETTE3, bg & 0x00ffffff);
if (pI830->Clone) {
if (pI830->Clone || pI830->MergedFB) {
OUTREG(CURSOR_B_PALETTE0, bg & 0x00ffffff);
OUTREG(CURSOR_B_PALETTE1, fg & 0x00ffffff);
OUTREG(CURSOR_B_PALETTE2, fg & 0x00ffffff);

47
src/i830_dga.c
View File

@ -99,6 +99,31 @@ I830DGAInit(ScreenPtr pScreen)
while (pMode) {
if(pI830->MergedFB) {
Bool nogood = FALSE;
/* Filter out all meta modes that would require driver-side panning */
switch(((I830ModePrivatePtr)pMode->Private)->merged.SecondPosition) {
case PosRightOf:
case PosLeftOf:
if( (((I830ModePrivatePtr)pMode->Private)->merged.First->VDisplay !=
((I830ModePrivatePtr)pMode->Private)->merged.Second->VDisplay) ||
(((I830ModePrivatePtr)pMode->Private)->merged.First->VDisplay != pMode->VDisplay) )
nogood = TRUE;
break;
default:
if( (((I830ModePrivatePtr)pMode->Private)->merged.First->HDisplay !=
((I830ModePrivatePtr)pMode->Private)->merged.Second->HDisplay) ||
(((I830ModePrivatePtr)pMode->Private)->merged.First->HDisplay != pMode->HDisplay) )
nogood = TRUE;
}
if(nogood) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"DGA: MetaMode %dx%d not suitable for DGA, skipping\n",
pMode->HDisplay, pMode->VDisplay);
goto mode_nogood;
}
}
newmodes = xrealloc(modes, (num + 1) * sizeof(DGAModeRec));
if (!newmodes) {
@ -155,6 +180,7 @@ I830DGAInit(ScreenPtr pScreen)
currentMode->maxViewportY = currentMode->imageHeight -
currentMode->viewportHeight;
mode_nogood:
pMode = pMode->next;
if (pMode == firstMode)
break;
@ -254,15 +280,26 @@ I830_FillRect(ScrnInfoPtr pScrn,
static void
I830_Sync(ScrnInfoPtr pScrn)
{
#ifdef I830_USE_XAA
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
MARKER();
if (pI830->AccelInfoRec) {
(*pI830->AccelInfoRec->Sync) (pScrn);
}
#endif
if (pI830->noAccel)
return;
if (IS_I965G(pI830))
flags = 0;
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
I830WaitLpRing(pScrn, pI830->LpRing->mem.Size - 8, 0);
pI830->LpRing->space = pI830->LpRing->mem.Size - 8;
pI830->nextColorExpandBuf = 0;
}
static void

118
src/i830_dri.c
View File

@ -81,8 +81,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830.h"
#include "i830_dri.h"
#include "dristruct.h"
static char I830KernelDriverName[] = "i915";
static char I830ClientDriverName[] = "i915";
static char I965ClientDriverName[] = "i965";
static Bool I830InitVisualConfigs(ScreenPtr pScreen);
static Bool I830CreateContext(ScreenPtr pScreen, VisualPtr visual,
@ -424,11 +427,13 @@ I830CheckDRIAvailable(ScrnInfoPtr pScrn)
* for known symbols in each module. */
if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs"))
return FALSE;
if (!xf86LoaderCheckSymbol("DRIScreenInit"))
return FALSE;
if (!xf86LoaderCheckSymbol("drmAvailable"))
return FALSE;
if (!xf86LoaderCheckSymbol("DRIQueryVersion")) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] %s failed (libdri.a too old)\n", "I830DRIScreenInit");
"[dri] %s failed (libdri.a too old)\n", "I830CheckDRIAvailable");
return FALSE;
}
@ -440,10 +445,10 @@ I830CheckDRIAvailable(ScrnInfoPtr pScrn)
if (major != DRIINFO_MAJOR_VERSION || minor < DRIINFO_MINOR_VERSION) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] %s failed because of a version mismatch.\n"
"[dri] libdri version is %d.%d.%d bug version %d.%d.x is needed.\n"
"[dri] libDRI version is %d.%d.%d but version %d.%d.x is needed.\n"
"[dri] Disabling DRI.\n",
"I830DRIScreenInit", major, minor, patch,
DRIINFO_MAJOR_VERSION, DRIINFO_MINOR_VERSION);
"I830CheckDRIAvailable", major, minor, patch,
DRIINFO_MAJOR_VERSION, DRIINFO_MINOR_VERSION);
return FALSE;
}
}
@ -475,7 +480,11 @@ I830DRIScreenInit(ScreenPtr pScreen)
pI830->LockHeld = 0;
pDRIInfo->drmDriverName = I830KernelDriverName;
pDRIInfo->clientDriverName = I830ClientDriverName;
if (IS_I965G(pI830))
pDRIInfo->clientDriverName = I965ClientDriverName;
else
pDRIInfo->clientDriverName = I830ClientDriverName;
if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
pDRIInfo->busIdString = DRICreatePCIBusID(pI830->PciInfo);
} else {
@ -488,13 +497,16 @@ I830DRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = I830_MAJOR_VERSION;
pDRIInfo->ddxDriverMinorVersion = I830_MINOR_VERSION;
pDRIInfo->ddxDriverPatchVersion = I830_PATCHLEVEL;
#if 1 /* temporary until this gets removed from the libdri layer */
#if 1 /* Remove this soon - see bug 5714 */
pDRIInfo->frameBufferPhysicalAddress = (char *) pI830->LinearAddr +
pI830->FrontBuffer.Start;
pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth *
pScrn->virtualY * pI830->cpp);
pDRIInfo->frameBufferStride = pScrn->displayWidth * pI830->cpp;
#else
/* For rotation we map a 0 length framebuffer as we remap ourselves later */
pDRIInfo->frameBufferSize = 0;
#endif
pDRIInfo->frameBufferStride = pScrn->displayWidth * pI830->cpp;
pDRIInfo->ddxDrawableTableEntry = I830_MAX_DRAWABLES;
if (SAREA_MAX_DRAWABLES < I830_MAX_DRAWABLES)
@ -534,6 +546,7 @@ I830DRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionSingleToMulti3D = I830DRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = I830DRITransitionMultiToSingle3d;
/* do driver-independent DRI screen initialization here */
if (!DRIScreenInit(pScreen, pDRIInfo, &pI830->drmSubFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
@ -544,6 +557,27 @@ I830DRIScreenInit(ScreenPtr pScreen)
return FALSE;
}
#if 0 /* disabled now, see frameBufferSize above being set to 0 */
/* for this driver, get rid of the front buffer mapping now */
if (xf86LoaderCheckSymbol("DRIGetScreenPrivate")) {
DRIScreenPrivPtr pDRIPriv
= (DRIScreenPrivPtr) DRIGetScreenPrivate(pScreen);
if (pDRIPriv && pDRIPriv->drmFD && pDRIPriv->hFrameBuffer) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] removing original screen mapping\n");
drmRmMap(pDRIPriv->drmFD, pDRIPriv->hFrameBuffer);
pDRIPriv->hFrameBuffer = 0;
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] done removing original screen mapping\n");
}
}
else {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] DRIGetScreenPrivate not found!!!!\n");
}
#endif
/* Check the i915 DRM versioning */
{
drmVersionPtr version;
@ -589,11 +623,11 @@ I830DRIScreenInit(ScreenPtr pScreen)
/* Check the i915 DRM version */
version = drmGetVersion(pI830->drmSubFD);
if (version) {
if (version->version_major != 1 || version->version_minor < 4) {
if (version->version_major != 1 || version->version_minor < 3) {
/* incompatible drm version */
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] %s failed because of a version mismatch.\n"
"[dri] i915 kernel module version is %d.%d.%d but version 1.4 or greater is needed.\n"
"[dri] i915 kernel module version is %d.%d.%d but version 1.3 or greater is needed.\n"
"[dri] Disabling DRI.\n",
"I830DRIScreenInit",
version->version_major,
@ -623,21 +657,31 @@ I830DRIMapScreenRegions(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
ScreenPtr pScreen = pScrn->pScreen;
I830Ptr pI830 = I830PTR(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] Mapping front buffer\n");
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
sarea->front_size,
DRM_FRAME_BUFFER, /*DRM_AGP,*/
0,
(drmAddress) &sarea->front_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
#if 1 /* Remove this soon - see bug 5714 */
pI830->pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth *
pScrn->virtualY * pI830->cpp);
#endif
/* The I965G isn't ready for the front buffer mapping to be moved around,
* because of issues with rmmap, it seems.
*/
if (!IS_I965G(pI830)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] Mapping front buffer\n");
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
sarea->front_size,
DRM_AGP,
0,
(drmAddress) &sarea->front_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[drm] Front Buffer = 0x%08x\n",
(int)sarea->front_handle);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[drm] Front Buffer = 0x%08x\n",
(int)sarea->front_handle);
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->back_offset + pI830->LinearAddr),
@ -684,12 +728,10 @@ I830DRIUnmapScreenRegions(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
{
I830Ptr pI830 = I830PTR(pScrn);
#if 1
if (sarea->front_handle) {
drmRmMap(pI830->drmSubFD, sarea->front_handle);
sarea->front_handle = 0;
}
#endif
if (sarea->back_handle) {
drmRmMap(pI830->drmSubFD, sarea->back_handle);
sarea->back_handle = 0;
@ -785,7 +827,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
/* screen mappings probably failed */
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] drmAddMap(screen mappings) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
}
@ -824,9 +865,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
pI830DRI->mem = pScrn->videoRam * 1024;
pI830DRI->cpp = pI830->cpp;
pI830DRI->fbOffset = pI830->FrontBuffer.Start;
pI830DRI->fbStride = pI830->backPitch;
pI830DRI->bitsPerPixel = pScrn->bitsPerPixel;
pI830DRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
@ -1032,6 +1070,7 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
{
ScreenPtr pScreen = pParent->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
BoxPtr pboxTmp, pboxNext, pboxBase;
DDXPointPtr pptTmp, pptNew2;
int xdir, ydir;
@ -1164,8 +1203,10 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
I830SelectBuffer(pScrn, I830_SELECT_BACK);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
if (!IS_I965G(pI830)) {
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
}
}
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
I830EmitFlush(pScrn);
@ -1204,6 +1245,7 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
* might be faster, but seems like a lot more work...
*/
#if 0
/* This should be done *before* XAA syncs,
* Otherwise will have to sync again???
@ -1213,7 +1255,7 @@ I830DRIShadowUpdate (ScreenPtr pScreen, shadowBufPtr pBuf)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
RegionPtr damage = (RegionPtr) shadowDamage(pBuf);
RegionPtr damage = &pBuf->damage;
int i, num = REGION_NUM_RECTS(damage);
BoxPtr pbox = REGION_RECTS(damage);
drmI830Sarea *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
@ -1343,6 +1385,7 @@ I830DRITransitionTo2d(ScreenPtr pScreen)
}
pI830->have3DWindows = 0;
}
@ -1359,6 +1402,14 @@ I830UpdateDRIBuffers(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
I830DRIUnmapScreenRegions(pScrn, sarea);
sarea->front_tiled = pI830->front_tiled;
sarea->back_tiled = pI830->back_tiled;
sarea->depth_tiled = pI830->depth_tiled;
sarea->rotated_tiled = pI830->rotated_tiled;
#if 0
sarea->rotated2_tiled = pI830->rotated2_tiled;
#endif
if (pI830->rotation == RR_Rotate_0) {
sarea->front_offset = pI830->FrontBuffer.Start;
/* Don't use FrontBuffer.Size here as it includes the pixmap cache area
@ -1418,7 +1469,8 @@ I830UpdateDRIBuffers(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
success = I830DRIMapScreenRegions(pScrn, sarea);
I830InitTextureHeap(pScrn, sarea);
if (success)
I830InitTextureHeap(pScrn, sarea);
return success;
}

38
src/i830_dri.h
View File

@ -10,7 +10,7 @@
#define I830_MAJOR_VERSION 1
#define I830_MINOR_VERSION 6
#define I830_PATCHLEVEL 0
#define I830_PATCHLEVEL 4
#define I830_REG_SIZE 0x80000
@ -18,20 +18,20 @@ typedef struct _I830DRIRec {
drm_handle_t regs;
drmSize regsSize;
drmSize backbufferSize;
drm_handle_t backbuffer;
drmSize unused1; /* backbufferSize */
drm_handle_t unused2; /* backbuffer */
drmSize depthbufferSize;
drm_handle_t depthbuffer;
drmSize unused3; /* depthbufferSize */
drm_handle_t unused4; /* depthbuffer */
drmSize rotatedSize;
drm_handle_t rotatedbuffer;
drmSize unused5; /* rotatedSize /*/
drm_handle_t unused6; /* rotatedbuffer */
drm_handle_t textures;
int textureSize;
drm_handle_t unused7; /* textures */
int unused8; /* textureSize */
drm_handle_t agp_buffers;
drmSize agp_buf_size;
drm_handle_t unused9; /* agp_buffers */
drmSize unused10; /* agp_buf_size */
int deviceID;
int width;
@ -40,20 +40,10 @@ typedef struct _I830DRIRec {
int cpp;
int bitsPerPixel;
int fbOffset;
int fbStride;
int unused11[8]; /* was front/back/depth/rotated offset/pitch */
int backOffset;
int backPitch;
int depthOffset;
int depthPitch;
int rotatedOffset;
int rotatedPitch;
int logTextureGranularity;
int textureOffset;
int unused12; /* logTextureGranularity */
int unused13; /* textureOffset */
int irq;
int sarea_priv_offset;

2678
src/i830_driver.c
View File

File diff suppressed because it is too large Load Diff

111
src/i830_memory.c
View File

@ -209,12 +209,12 @@ AllocFromAGP(ScrnInfoPtr pScrn, I830MemRange *result, long size,
if (newApStart > newApEnd)
return 0;
if (flags & NEED_PHYSICAL_ADDR) {
if (flags & NEED_PHYSICAL_ADDR)
result->Key = xf86AllocateGARTMemory(pScrn->scrnIndex, size, 2,
&(result->Physical));
} else {
else
result->Key = xf86AllocateGARTMemory(pScrn->scrnIndex, size, 0, NULL);
}
if (result->Key == -1)
return 0;
}
@ -498,7 +498,7 @@ I830AllocateRotatedBuffer(ScrnInfoPtr pScrn, int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->RotatedMem),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -563,7 +563,7 @@ I830AllocateRotated2Buffer(ScrnInfoPtr pScrn, int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->RotatedMem2),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -673,6 +673,7 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
memset(&(pI830->FrontBuffer2), 0, sizeof(pI830->FrontBuffer2));
pI830->FrontBuffer2.Key = -1;
#if 1 /* ROTATION */
pI830->FbMemBox2.x1 = 0;
pI830->FbMemBox2.x2 = pI830Ent->pScrn_2->displayWidth;
pI830->FbMemBox2.y1 = 0;
@ -680,6 +681,12 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualX;
else
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualY;
#else
pI830->FbMemBox2.x1 = 0;
pI830->FbMemBox2.x2 = pI830Ent->pScrn_2->displayWidth;
pI830->FbMemBox2.y1 = 0;
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualY;
#endif
/*
* Calculate how much framebuffer memory to allocate. For the
@ -731,19 +738,26 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI8302->allowPageFlip &&
IsTileable(pI830Ent->pScrn_2->displayWidth * pI8302->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
alignflags = 0;
}
#if 1 /* ROTATION */
if (pI830Ent->pScrn_2->virtualX > pI830Ent->pScrn_2->virtualY)
size = lineSize * (pI830Ent->pScrn_2->virtualX + cacheLines);
else
size = lineSize * (pI830Ent->pScrn_2->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#else
size = lineSize * (pI830Ent->pScrn_2->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sSecondary framebuffer allocation size: %ld kByte\n", s,
size / 1024);
@ -765,6 +779,7 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer));
pI830->FrontBuffer.Key = -1;
#if 1 /* ROTATION */
pI830->FbMemBox.x1 = 0;
pI830->FbMemBox.x2 = pScrn->displayWidth;
pI830->FbMemBox.y1 = 0;
@ -772,6 +787,12 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
pI830->FbMemBox.y2 = pScrn->virtualX;
else
pI830->FbMemBox.y2 = pScrn->virtualY;
#else
pI830->FbMemBox.x1 = 0;
pI830->FbMemBox.x2 = pScrn->displayWidth;
pI830->FbMemBox.y1 = 0;
pI830->FbMemBox.y2 = pScrn->virtualY;
#endif
/*
* Calculate how much framebuffer memory to allocate. For the
@ -823,19 +844,26 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
IsTileable(pScrn->displayWidth * pI830->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
alignflags = 0;
}
#if 1 /* ROTATION */
if (pScrn->virtualX > pScrn->virtualY)
size = lineSize * (pScrn->virtualX + cacheLines);
else
size = lineSize * (pScrn->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#else
size = lineSize * (pScrn->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sInitial framebuffer allocation size: %ld kByte\n", s,
size / 1024);
@ -937,7 +965,10 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
IsTileable(pScrn->displayWidth * pI830->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
@ -1175,7 +1206,7 @@ I830AllocateBackBuffer(ScrnInfoPtr pScrn, const int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->BackBuffer),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -1238,7 +1269,7 @@ I830AllocateDepthBuffer(ScrnInfoPtr pScrn, const int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->DepthBuffer),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -1672,7 +1703,7 @@ SetFence(ScrnInfoPtr pScrn, int nr, unsigned int start, unsigned int pitch,
}
static Bool
MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem)
MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem, unsigned int fence)
{
I830Ptr pI830 = I830PTR(pScrn);
int pitch, ntiles, i;
@ -1690,6 +1721,31 @@ MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem)
}
pitch = pScrn->displayWidth * pI830->cpp;
if (IS_I965G(pI830)) {
I830RegPtr i830Reg = &pI830->ModeReg;
switch (fence) {
case FENCE_XMAJOR:
i830Reg->Fence[nextTile] = (((pitch / 128) - 1) << 2) | pMem->Start | 1;
break;
case FENCE_YMAJOR:
/* YMajor can be 128B aligned but the current code dictates
* otherwise. This isn't a problem apart from memory waste.
* FIXME */
i830Reg->Fence[nextTile] = (((pitch / 128) - 1) << 2) | pMem->Start | 1;
i830Reg->Fence[nextTile] |= (1<<1);
break;
default:
case FENCE_LINEAR:
break;
}
i830Reg->Fence[nextTile+FENCE_NEW_NR] = pMem->End;
nextTile++;
return TRUE;
}
/*
* Simply try to break the region up into at most four pieces of size
* equal to the alignment.
@ -1731,20 +1787,27 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
return;
}
pI830->front_tiled = FENCE_LINEAR;
pI830->back_tiled = FENCE_LINEAR;
pI830->depth_tiled = FENCE_LINEAR;
pI830->rotated_tiled = FENCE_LINEAR;
pI830->rotated2_tiled = FENCE_LINEAR;
if (pI830->allowPageFlip) {
if (pI830->allowPageFlip && pI830->FrontBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->FrontBuffer))) {
if (MakeTiles(pScrn, &(pI830->FrontBuffer), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the FRONT buffer\n");
"Activating tiled memory for the front buffer\n");
pI830->front_tiled = FENCE_XMAJOR;
} else {
pI830->allowPageFlip = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the FRONT buffer\n");
"MakeTiles failed for the front buffer\n");
}
} else {
pI830->allowPageFlip = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Alignment bad for the FRONT buffer\n");
"Alignment bad for the front buffer\n");
}
}
@ -1755,9 +1818,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
* value.
*/
if (pI830->BackBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->BackBuffer))) {
if (MakeTiles(pScrn, &(pI830->BackBuffer), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the back buffer.\n");
pI830->back_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the back buffer.\n");
@ -1766,9 +1830,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
}
if (pI830->DepthBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->DepthBuffer))) {
if (MakeTiles(pScrn, &(pI830->DepthBuffer), FENCE_YMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the depth buffer.\n");
"Activating tiled memory for the depth buffer.\n");
pI830->depth_tiled = FENCE_YMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the depth buffer.\n");
@ -1776,9 +1841,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
}
if (pI830->RotatedMem.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem))) {
if (MakeTiles(pScrn, &(pI830->RotatedMem), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the rotated buffer.\n");
pI830->rotated_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the rotated buffer.\n");
@ -1787,9 +1853,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
#if 0
if (pI830->RotatedMem2.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem2))) {
if (MakeTiles(pScrn, &(pI830->RotatedMem2), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the rotated2 buffer.\n");
pI830->rotated2_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the rotated buffer.\n");

132
src/i830_modes.c
View File

@ -42,8 +42,6 @@
#include <string.h>
#include "xf86.h"
#include "vbe.h"
#include "vbeModes.h"
#include "i830.h"
#include <math.h>
@ -363,7 +361,11 @@ CheckMode(ScrnInfoPtr pScrn, vbeInfoPtr pVbe, VbeInfoBlock *vbe, int id,
CARD16 major, minor;
VbeModeInfoBlock *mode;
DisplayModePtr p = NULL, pMode = NULL;
#if 0
VbeModeInfoData *data;
#else
I830ModePrivatePtr data;
#endif
Bool modeOK = FALSE;
ModeStatus status = MODE_OK;
@ -602,12 +604,21 @@ CheckMode(ScrnInfoPtr pScrn, vbeInfoPtr pVbe, VbeInfoBlock *vbe, int id,
pMode->HDisplay = mode->XResolution;
pMode->VDisplay = mode->YResolution;
#if 0
data = xnfcalloc(sizeof(VbeModeInfoData), 1);
data->mode = id;
data->data = mode;
pMode->PrivSize = sizeof(VbeModeInfoData);
pMode->Private = (INT32*)data;
#else
data = xnfcalloc(sizeof(I830ModePrivateRec), 1);
data->vbeData.mode = id;
data->vbeData.data = mode;
pMode->PrivSize = sizeof(I830ModePrivateRec);
pMode->Private = (INT32*)data;
#endif
pMode->next = NULL;
return pMode;
}
@ -663,54 +674,113 @@ I830GetModePool(ScrnInfoPtr pScrn, vbeInfoPtr pVbe, VbeInfoBlock *vbe)
void
I830SetModeParameters(ScrnInfoPtr pScrn, vbeInfoPtr pVbe)
{
DisplayModePtr pMode;
VbeModeInfoData *data;
I830Ptr pI830 = I830PTR(pScrn);
DisplayModePtr pMode = pScrn->modes;
DisplayModePtr ppMode = pScrn->modes;
I830ModePrivatePtr mp = NULL;
pMode = pScrn->modes;
do {
int clock;
mp = (I830ModePrivatePtr) pMode->Private;
data = (VbeModeInfoData*)pMode->Private;
data->block = xcalloc(sizeof(VbeCRTCInfoBlock), 1);
data->block->HorizontalTotal = pMode->HTotal;
data->block->HorizontalSyncStart = pMode->HSyncStart;
data->block->HorizontalSyncEnd = pMode->HSyncEnd;
data->block->VerticalTotal = pMode->VTotal;
data->block->VerticalSyncStart = pMode->VSyncStart;
data->block->VerticalSyncEnd = pMode->VSyncEnd;
data->block->Flags = ((pMode->Flags & V_NHSYNC) ? CRTC_NHSYNC : 0) |
((pMode->Flags & V_NVSYNC) ? CRTC_NVSYNC : 0);
data->block->PixelClock = pMode->Clock * 1000;
if (pI830->MergedFB) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s\n", pScrn->monitor->id);
ppMode = (DisplayModePtr) mp->merged.First;
mp = (I830ModePrivatePtr) mp->merged.First->Private;
}
mp->vbeData.block = xcalloc(sizeof(VbeCRTCInfoBlock), 1);
mp->vbeData.block->HorizontalTotal = ppMode->HTotal;
mp->vbeData.block->HorizontalSyncStart = ppMode->HSyncStart;
mp->vbeData.block->HorizontalSyncEnd = ppMode->HSyncEnd;
mp->vbeData.block->VerticalTotal = ppMode->VTotal;
mp->vbeData.block->VerticalSyncStart = ppMode->VSyncStart;
mp->vbeData.block->VerticalSyncEnd = ppMode->VSyncEnd;
mp->vbeData.block->Flags = ((ppMode->Flags & V_NHSYNC) ? CRTC_NHSYNC : 0) |
((ppMode->Flags & V_NVSYNC) ? CRTC_NVSYNC : 0);
mp->vbeData.block->PixelClock = ppMode->Clock * 1000;
/* XXX May not have this. */
clock = VBEGetPixelClock(pVbe, data->mode, data->block->PixelClock);
clock = VBEGetPixelClock(pVbe, mp->vbeData.mode, mp->vbeData.block->PixelClock);
if (clock)
data->block->PixelClock = clock;
mp->vbeData.block->PixelClock = clock;
#ifdef DEBUG
ErrorF("Setting clock %.2fMHz, closest is %.2fMHz\n",
(double)data->block->PixelClock / 1000000.0,
(double)mp->vbeData.block->PixelClock / 1000000.0,
(double)clock / 1000000.0);
#endif
data->mode |= (1 << 11);
if (pMode->VRefresh != 0) {
data->block->RefreshRate = pMode->VRefresh * 100;
mp->vbeData.mode |= (1 << 11);
if (ppMode->VRefresh != 0) {
mp->vbeData.block->RefreshRate = ppMode->VRefresh * 100;
} else {
data->block->RefreshRate = (int)(((double)(data->block->PixelClock)/
(double)(pMode->HTotal * pMode->VTotal)) * 100);
mp->vbeData.block->RefreshRate = (int)(((double)(mp->vbeData.block->PixelClock)/
(double)(ppMode->HTotal * ppMode->VTotal)) * 100);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Attempting to use %2.2fHz refresh for mode \"%s\" (%x)\n",
(float)(((double)(data->block->PixelClock) / (double)(pMode->HTotal * pMode->VTotal))), pMode->name, data->mode);
(float)(((double)(mp->vbeData.block->PixelClock) / (double)(ppMode->HTotal * ppMode->VTotal))), ppMode->name, mp->vbeData.mode);
#ifdef DEBUG
ErrorF("Video Modeline: ID: 0x%x Name: %s %i %i %i %i - "
" %i %i %i %i %.2f MHz Refresh: %.2f Hz\n",
data->mode, pMode->name, pMode->HDisplay, pMode->HSyncStart,
pMode->HSyncEnd, pMode->HTotal, pMode->VDisplay,
pMode->VSyncStart,pMode->VSyncEnd,pMode->VTotal,
(double)data->block->PixelClock/1000000.0,
(double)data->block->RefreshRate/100);
mp->vbeData.mode, ppMode->name, ppMode->HDisplay, ppMode->HSyncStart,
ppMode->HSyncEnd, ppMode->HTotal, ppMode->VDisplay,
ppMode->VSyncStart,ppMode->VSyncEnd,ppMode->VTotal,
(double)mp->vbeData.block->PixelClock/1000000.0,
(double)mp->vbeData.block->RefreshRate/100);
#endif
pMode = pMode->next;
pMode = ppMode = pMode->next;
} while (pMode != pScrn->modes);
if (pI830->MergedFB) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "%s\n", pI830->pScrn_2->monitor->id);
pMode = pScrn->modes;
do {
int clock;
mp = (I830ModePrivatePtr) pMode->Private;
ppMode = (DisplayModePtr) mp->merged.Second;
mp = (I830ModePrivatePtr) mp->merged.Second->Private;
mp->vbeData.block = xcalloc(sizeof(VbeCRTCInfoBlock), 1);
mp->vbeData.block->HorizontalTotal = ppMode->HTotal;
mp->vbeData.block->HorizontalSyncStart = ppMode->HSyncStart;
mp->vbeData.block->HorizontalSyncEnd = ppMode->HSyncEnd;
mp->vbeData.block->VerticalTotal = ppMode->VTotal;
mp->vbeData.block->VerticalSyncStart = ppMode->VSyncStart;
mp->vbeData.block->VerticalSyncEnd = ppMode->VSyncEnd;
mp->vbeData.block->Flags = ((ppMode->Flags & V_NHSYNC) ? CRTC_NHSYNC : 0) |
((ppMode->Flags & V_NVSYNC) ? CRTC_NVSYNC : 0);
mp->vbeData.block->PixelClock = ppMode->Clock * 1000;
/* XXX May not have this. */
clock = VBEGetPixelClock(pVbe, mp->vbeData.mode, mp->vbeData.block->PixelClock);
if (clock)
mp->vbeData.block->PixelClock = clock;
#ifdef DEBUG
ErrorF("Setting clock %.2fMHz, closest is %.2fMHz\n",
(double)mp->vbeData.block->PixelClock / 1000000.0,
(double)clock / 1000000.0);
#endif
mp->vbeData.mode |= (1 << 11);
if (ppMode->VRefresh != 0) {
mp->vbeData.block->RefreshRate = ppMode->VRefresh * 100;
} else {
mp->vbeData.block->RefreshRate = (int)(((double)(mp->vbeData.block->PixelClock)/
(double)(ppMode->HTotal * ppMode->VTotal)) * 100);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Attempting to use %2.2fHz refresh for mode \"%s\" (%x)\n",
(float)(((double)(mp->vbeData.block->PixelClock) / (double)(ppMode->HTotal * ppMode->VTotal))), ppMode->name, mp->vbeData.mode);
#ifdef DEBUG
ErrorF("Video Modeline: ID: 0x%x Name: %s %i %i %i %i - "
" %i %i %i %i %.2f MHz Refresh: %.2f Hz\n",
mp->vbeData.mode, ppMode->name, ppMode->HDisplay, ppMode->HSyncStart,
ppMode->HSyncEnd, ppMode->HTotal, ppMode->VDisplay,
ppMode->VSyncStart,ppMode->VSyncEnd,ppMode->VTotal,
(double)mp->vbeData.block->PixelClock/1000000.0,
(double)mp->vbeData.block->RefreshRate/100);
#endif
pMode = ppMode = pMode->next;
} while (pMode != pScrn->modes);
}
}
void

40
src/i830_rotate.c
View File

@ -404,7 +404,7 @@ I915UpdateRotate (ScreenPtr pScreen,
if (pI830->disableTiling)
use_fence = 0;
else
use_fence = 4;
use_fence = MS3_USE_FENCE_REGS;
if (pI830->cpp == 1)
use_fence |= MAPSURF_8BIT;
@ -575,15 +575,15 @@ I830UpdateRotate (ScreenPtr pScreen,
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
/* draw rect */
OUT_RING(0x7d800003);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING((pScrn->virtualX - 1) | (pScrn->virtualY - 1) << 16);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DRAW_RECT_CMD);
OUT_RING(0x00000000); /* flags */
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING((pScrn->virtualX - 1) | (pScrn->virtualY - 1) << 16); /* ymax, xmax */
OUT_RING(0x00000000); /* yorigin, xorigin */
OUT_RING(MI_NOOP);
/* front buffer */
OUT_RING(0x7d8e0001);
OUT_RING(_3DSTATE_BUF_INFO_CMD);
OUT_RING(0x03800000 | (((pI830->displayWidth * pI830->cpp) / 4) << 2));
if (I830IsPrimary(pScrn))
OUT_RING(pI830->FrontBuffer.Start);
@ -736,12 +736,12 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
};
if (pI830->noAccel)
func = LoaderSymbol("shadowUpdateRotatePacked");
func = LoaderSymbol("shadowUpdateRotatePacked");
else
if (IS_I9XX(pI830))
func = I915UpdateRotate;
else
func = I830UpdateRotate;
if (IS_I9XX(pI830))
func = I915UpdateRotate;
else
func = I830UpdateRotate;
if (I830IsPrimary(pScrn)) {
pI8301 = pI830;
@ -771,6 +771,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
* We grab the DRI lock when reallocating buffers to avoid DRI clients
* getting bogus information.
*/
#ifdef XF86DRI
if (pI8301->directRenderingEnabled && reAllocate) {
didLock = I830DRILock(pScrn1);
@ -789,6 +790,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
}
}
if (pI8301->TexMem.Key != -1)
xf86UnbindGARTMemory(pScrn1->scrnIndex, pI8301->TexMem.Key);
I830FreeVidMem(pScrn1, &(pI8301->TexMem));
@ -891,7 +893,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
if (pI8301->rotation != RR_Rotate_0) {
if (!I830AllocateRotatedBuffer(pScrn1,
(pI8301->disableTiling ? ALLOC_NO_TILING : 0)))
pI8301->disableTiling ? ALLOC_NO_TILING : 0))
goto BAIL1;
I830FixOffset(pScrn1, &(pI8301->RotatedMem));
@ -903,8 +905,8 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
shadowRemove (pScrn->pScreen, NULL);
if (pI830->rotation != RR_Rotate_0)
shadowAdd (pScrn->pScreen,
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
if (I830IsPrimary(pScrn)) {
if (pI830->rotation != RR_Rotate_0)
@ -1105,7 +1107,7 @@ BAIL0:
if (pI8301->rotation != RR_Rotate_0) {
if (!I830AllocateRotatedBuffer(pScrn1,
(pI8301->disableTiling ? ALLOC_NO_TILING : 0)))
pI8301->disableTiling ? ALLOC_NO_TILING : 0))
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Oh dear, the rotated buffer failed - badness\n");
@ -1117,8 +1119,8 @@ BAIL0:
shadowRemove (pScrn->pScreen, NULL);
if (pI830->rotation != RR_Rotate_0)
shadowAdd (pScrn->pScreen,
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
if (I830IsPrimary(pScrn)) {
if (pI830->rotation != RR_Rotate_0)

1546
src/i830_video.c
View File

File diff suppressed because it is too large Load Diff

76
src/i830_video.h Normal file
View File

@ -0,0 +1,76 @@
/***************************************************************************
Copyright 2000 Intel Corporation. All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL INTEL, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#include "xf86.h"
#include "xf86_OSproc.h"
typedef struct {
CARD32 YBuf0offset;
CARD32 UBuf0offset;
CARD32 VBuf0offset;
CARD32 YBuf1offset;
CARD32 UBuf1offset;
CARD32 VBuf1offset;
unsigned char currentBuf;
int brightness;
int contrast;
int pipe;
int doubleBuffer;
RegionRec clip;
CARD32 colorKey;
CARD32 gamma0;
CARD32 gamma1;
CARD32 gamma2;
CARD32 gamma3;
CARD32 gamma4;
CARD32 gamma5;
CARD32 videoStatus;
Time offTime;
Time freeTime;
FBLinearPtr linear;
Bool overlayOK;
int oneLineMode;
int scaleRatio;
Bool textured;
} I830PortPrivRec, *I830PortPrivPtr;
#define GET_PORT_PRIVATE(pScrn) \
(I830PortPrivPtr)((I830PTR(pScrn))->adaptor->pPortPrivates[0].ptr)
void I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int id, RegionPtr dstRegion, short width,
short height, int video_pitch,
int x1, int y1, int x2, int y2,
short src_w, short src_h,
short drw_w, short drw_h,
DrawablePtr pDraw);

76
src/i830_xaa.c
View File

@ -230,6 +230,32 @@ I830XAAInit(ScreenPtr pScreen)
return XAAInit(pScreen, infoPtr);
}
#ifdef XF86DRI
static unsigned int
CheckTiling(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = 0;
/* Check tiling */
if (IS_I965G(pI830)) {
if (pI830->bufferOffset == pScrn->fbOffset && pI830->front_tiled == FENCE_XMAJOR)
tiled = 1;
if (pI830->bufferOffset == pI830->RotatedMem.Start && pI830->rotated_tiled == FENCE_XMAJOR)
tiled = 1;
if (pI830->bufferOffset == pI830->BackBuffer.Start && pI830->back_tiled == FENCE_XMAJOR)
tiled = 1;
/* not really supported as it's always YMajor tiled */
if (pI830->bufferOffset == pI830->DepthBuffer.Start && pI830->depth_tiled == FENCE_XMAJOR)
tiled = 1;
}
return tiled;
}
#else
#define CheckTiling(pScrn) 0
#endif
void
I830SetupForSolidFill(ScrnInfoPtr pScrn, int color, int rop,
unsigned int planemask)
@ -292,6 +318,9 @@ I830SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, int w, int h)
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
void
@ -334,6 +363,7 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
{
I830Ptr pI830 = I830PTR(pScrn);
int dst_x2, dst_y2;
unsigned int tiled = CheckTiling(pScrn);
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
ErrorF("I830SubsequentScreenToScreenCopy %d,%d - %d,%d %dx%d\n",
@ -342,14 +372,18 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
dst_x2 = dst_x1 + w;
dst_y2 = dst_y1 + h;
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(8);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
XY_SRC_COPY_BLT_WRITE_RGB | tiled << 15 | tiled << 11);
} else {
OUT_RING(XY_SRC_COPY_BLT_CMD);
OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 15 | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING((dst_y1 << 16) | (dst_x1 & 0xffff));
@ -361,6 +395,9 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
static void
@ -402,6 +439,7 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
{
I830Ptr pI830 = I830PTR(pScrn);
int x1, x2, y1, y2;
unsigned int tiled = CheckTiling(pScrn);
x1 = x;
x2 = x + w;
@ -411,16 +449,20 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
ErrorF("I830SubsequentMono8x8PatternFillRect\n");
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(10);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_MONO_PAT_BLT_CMD | XY_MONO_PAT_BLT_WRITE_ALPHA |
XY_MONO_PAT_BLT_WRITE_RGB |
XY_MONO_PAT_BLT_WRITE_RGB | tiled << 11 |
((patty << 8) & XY_MONO_PAT_VERT_SEED) |
((pattx << 12) & XY_MONO_PAT_HORT_SEED));
} else {
OUT_RING(XY_MONO_PAT_BLT_CMD |
OUT_RING(XY_MONO_PAT_BLT_CMD | tiled << 11 |
((patty << 8) & XY_MONO_PAT_VERT_SEED) |
((pattx << 12) & XY_MONO_PAT_HORT_SEED));
}
@ -435,6 +477,9 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
OUT_RING(0);
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
static void
@ -510,6 +555,7 @@ static void
I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = CheckTiling(pScrn);
if (pI830->init == 0) {
pI830->BR[12] = (pI830->AccelInfoRec->ScanlineColorExpandBuffers[0] -
@ -527,14 +573,18 @@ I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
ErrorF("I830SubsequentColorExpandScanline %d (addr %x)\n",
bufno, pI830->BR[12]);
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(8);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_MONO_SRC_BLT_CMD | XY_MONO_SRC_BLT_WRITE_ALPHA |
XY_MONO_SRC_BLT_WRITE_RGB);
tiled << 11 | XY_MONO_SRC_BLT_WRITE_RGB);
} else {
OUT_RING(XY_MONO_SRC_BLT_CMD);
OUT_RING(XY_MONO_SRC_BLT_CMD | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING(0); /* x1 = 0, y1 = 0 */
@ -551,6 +601,9 @@ I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
*/
pI830->BR[9] += pScrn->displayWidth * pI830->cpp;
I830GetNextScanlineColorExpandBuffer(pScrn);
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
#if DO_SCANLINE_IMAGE_WRITE
@ -602,6 +655,7 @@ static void
I830SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = CheckTiling(pScrn);
if (pI830->init == 0) {
pI830->BR[12] = (pI830->AccelInfoRec->ScanlineColorExpandBuffers[0] -
@ -624,15 +678,15 @@ I830SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
tiled << 11 | XY_SRC_COPY_BLT_WRITE_RGB);
} else {
OUT_RING(XY_SRC_COPY_BLT_CMD);
OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING(0); /* x1 = 0, y1 = 0 */
OUT_RING(0); /* x1 = 0, y1 = 0 */
OUT_RING(pI830->BR[11]); /* x2 = w, y2 = 1 */
OUT_RING(pI830->BR[9]); /* dst addr */
OUT_RING(0); /* source origin (0,0) */
OUT_RING(pI830->BR[9]); /* dst addr */
OUT_RING(0); /* source origin (0,0) */
OUT_RING(pI830->BR[11] & 0xffff); /* source pitch */
OUT_RING(pI830->BR[12]); /* src addr */

1
src/i915_3d.c
View File

@ -29,6 +29,7 @@
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i915_reg.h"

467
src/i915_video.c Normal file
View File

@ -0,0 +1,467 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86xv.h"
#include "fourcc.h"
#include "i830.h"
#include "i830_video.h"
#include "i915_reg.h"
#include "i915_3d.h"
union intfloat {
CARD32 ui;
float f;
};
#define OUT_RING_F(x) do { \
union intfloat _tmp; \
_tmp.f = x; \
OUT_RING(_tmp.ui); \
} while (0)
void
I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
RegionPtr dstRegion,
short width, short height, int video_pitch,
int x1, int y1, int x2, int y2,
short src_w, short src_h, short drw_w, short drw_h,
DrawablePtr pDraw)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 format, ms3, s2;
BoxPtr pbox;
int nbox, dxo, dyo;
Bool planar;
ErrorF("I915DisplayVideo: %dx%d (pitch %d)\n", width, height,
video_pitch);
switch (id) {
case FOURCC_UYVY:
case FOURCC_YUY2:
planar = FALSE;
break;
case FOURCC_YV12:
case FOURCC_I420:
planar = TRUE;
break;
default:
ErrorF("Unknown format 0x%x\n", id);
planar = FALSE;
break;
}
/* Tell the rotation code that we have stomped its invariant state by
* setting a high bit. We don't use any invariant 3D state for video, so we
* don't have to worry about it ourselves.
*/
*pI830->used3D |= 1 << 30;
BEGIN_LP_RING(44);
/* invarient state */
OUT_RING(MI_NOOP);
OUT_RING(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE | AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DFLT_Z_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_COORD_SET_BINDINGS | CSB_TCB(0, 0) | CSB_TCB(1, 1) |
CSB_TCB(2,2) | CSB_TCB(3,3) | CSB_TCB(4,4) | CSB_TCB(5,5) |
CSB_TCB(6,6) | CSB_TCB(7,7));
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_TRI_FAN_PROVOKE_VRTX | TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_LINE_STRIP_PROVOKE_VRTX | LINE_STRIP_PROVOKE_VRTX(1) |
ENABLE_TEXKILL_3D_4D | TEXKILL_4D |
ENABLE_POINT_RASTER_RULE | OGL_POINT_RASTER_RULE);
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 1);
OUT_RING(0x00000000); /* texture coordinate wrap */
/* flush map & render cache */
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
/* draw rect -- just clipping */
OUT_RING(_3DSTATE_DRAW_RECT_CMD);
OUT_RING(0x00000000); /* flags */
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING((pScrn->virtualX - 1) |
(pScrn->virtualY - 1) << 16); /* ymax, xmax */
OUT_RING(0x00000000); /* yorigin, xorigin */
OUT_RING(MI_NOOP);
/* scissor */
OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING(0x00000000); /* ymax, xmax */
OUT_RING(0x7c000003); /* unknown command */
OUT_RING(0x7d070000);
OUT_RING(0x00000000);
OUT_RING(0x68000002);
/* context setup */
OUT_RING(_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 4);
s2 = S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D);
if (planar)
s2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_2D);
else
s2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT);
s2 |= S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT);
OUT_RING(s2);
OUT_RING((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE | S4_VFMT_XY);
OUT_RING(0x00000000); /* S5 - enable bits */
OUT_RING((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
(2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
(1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
(2 << S6_TRISTRIP_PV_SHIFT));
OUT_RING(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
if (pI830->cpp == 2)
format = COLR_BUF_RGB565;
else
format = COLR_BUF_ARGB8888 | DEPTH_FRMT_24_FIXED_8_OTHER;
OUT_RING(LOD_PRECLAMP_OGL |
DSTORG_HORT_BIAS(0x80) | DSTORG_VERT_BIAS(0x80) | format);
OUT_RING(_3DSTATE_STIPPLE);
OUT_RING(0x00000000);
/* front buffer, pitch, offset */
OUT_RING(_3DSTATE_BUF_INFO_CMD);
OUT_RING(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
(((pI830->displayWidth * pI830->cpp) / 4) << 2));
OUT_RING(pI830->bufferOffset);
ADVANCE_LP_RING();
if (!planar) {
FS_LOCALS(3);
BEGIN_LP_RING(10);
OUT_RING(_3DSTATE_SAMPLER_STATE | 3);
OUT_RING(0x00000001);
OUT_RING(SS2_COLORSPACE_CONVERSION |
(FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_MAP_STATE | 3);
OUT_RING(0x00000001); /* texture map #1 */
OUT_RING(pPriv->YBuf0offset);
ms3 = MAPSURF_422;
switch (id) {
case FOURCC_YUY2:
ms3 |= MT_422_YCRCB_NORMAL;
break;
case FOURCC_UYVY:
ms3 |= MT_422_YCRCB_SWAPY;
break;
}
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
if (!pI830->disableTiling)
ms3 |= MS3_USE_FENCE_REGS;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
ADVANCE_LP_RING();
FS_BEGIN();
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_T0);
i915_fs_texld(FS_OC, FS_S0, FS_T0);
FS_END();
} else {
FS_LOCALS(16);
BEGIN_LP_RING(1 + 18 + 11 + 11);
OUT_RING(MI_NOOP);
/* For the planar formats, we set up three samplers -- one for each plane,
* in a Y8 format. Because I couldn't get the special PLANAR_TO_PACKED
* shader setup to work, I did the manual pixel shader:
*
* y' = y - .0625
* u' = u - .5
* v' = v - .5;
*
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
*
* register assignment:
* r0 = (y',u',v',0)
* r1 = (y,y,y,y)
* r2 = (u,u,u,u)
* r3 = (v,v,v,v)
* OC = (r,g,b,1)
*/
OUT_RING(_3DSTATE_PIXEL_SHADER_CONSTANTS | 16);
OUT_RING(0x000000f); /* constants 0-3 */
/* constant 0: normalization offsets */
OUT_RING_F(-0.0625);
OUT_RING_F(-0.5);
OUT_RING_F(-0.5);
OUT_RING_F(0.0);
/* constant 1: r coefficients*/
OUT_RING_F(1.1643);
OUT_RING_F(0.0);
OUT_RING_F(1.5958);
OUT_RING_F(0.0);
/* constant 2: g coefficients */
OUT_RING_F(1.1643);
OUT_RING_F(-0.39173);
OUT_RING_F(-0.81290);
OUT_RING_F(0.0);
/* constant 3: b coefficients */
OUT_RING_F(1.1643);
OUT_RING_F(2.017);
OUT_RING_F(0.0);
OUT_RING_F(0.0);
OUT_RING(_3DSTATE_SAMPLER_STATE | 9);
OUT_RING(0x00000007);
/* sampler 0 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
/* sampler 1 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
/* sampler 2 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
OUT_RING(_3DSTATE_MAP_STATE | 9);
OUT_RING(0x00000007);
OUT_RING(pPriv->YBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch * 2 / 4) - 1) << 21);
OUT_RING(pPriv->UBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
OUT_RING(pPriv->VBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
ADVANCE_LP_RING();
FS_BEGIN();
/* Declare samplers */
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_S1);
i915_fs_dcl(FS_S2);
i915_fs_dcl(FS_T0);
i915_fs_dcl(FS_T1);
/* Load samplers to temporaries. Y (sampler 0) gets the un-halved coords-
* from t1.
*/
i915_fs_texld(FS_R1, FS_S0, FS_T1);
i915_fs_texld(FS_R2, FS_S1, FS_T0);
i915_fs_texld(FS_R3, FS_S2, FS_T0);
/* Move the sampled YUV data in R[123] to the first 3 channels of R0. */
i915_fs_mov_masked(FS_R0, MASK_X, i915_fs_operand_reg(FS_R1));
i915_fs_mov_masked(FS_R0, MASK_Y, i915_fs_operand_reg(FS_R2));
i915_fs_mov_masked(FS_R0, MASK_Z, i915_fs_operand_reg(FS_R3));
/* Normalize the YUV data */
i915_fs_add(FS_R0, i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C0));
/* dot-product the YUV data in R0 by the vectors of coefficients for
* calculating R, G, and B, storing the results in the R, G, or B channels
* of the output color.
*/
i915_fs_dp3_masked(FS_OC, MASK_X | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C1));
i915_fs_dp3_masked(FS_OC, MASK_Y | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C2));
i915_fs_dp3_masked(FS_OC, MASK_Z | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C3));
/* Set alpha of the output to 1.0, by wiring W to 1 and not actually using
* the source.
*/
i915_fs_mov_masked(FS_OC, MASK_W, i915_fs_operand_one());
FS_END();
}
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
ADVANCE_LP_RING();
}
dxo = dstRegion->extents.x1;
dyo = dstRegion->extents.y1;
pbox = REGION_RECTS(dstRegion);
nbox = REGION_NUM_RECTS(dstRegion);
while (nbox--)
{
int box_x1 = pbox->x1;
int box_y1 = pbox->y1;
int box_x2 = pbox->x2;
int box_y2 = pbox->y2;
float src_scale_x, src_scale_y;
int vert_data_count;
pbox++;
src_scale_x = (float)src_w / (float)drw_w;
src_scale_y = (float)src_h / (float)drw_h;
if (!planar)
vert_data_count = 12;
else
vert_data_count = 18;
BEGIN_LP_RING(vert_data_count + 8);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
/* vertex data - rect list consists of bottom right, bottom left, and top
* left vertices.
*/
OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST |
(vert_data_count - 1));
/* bottom right */
OUT_RING_F(box_x2);
OUT_RING_F(box_y2);
if (!planar) {
OUT_RING_F((box_x2 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x2 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y2 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x2 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
}
/* bottom left */
OUT_RING_F(box_x1);
OUT_RING_F(box_y2);
if (!planar) {
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x1 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y2 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
}
/* top left */
OUT_RING_F(box_x1);
OUT_RING_F(box_y1);
if (!planar) {
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y1 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x1 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y1 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y1 - dyo) * src_scale_y);
}
ADVANCE_LP_RING();
}
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
}

166
src/wm_prog.h Normal file
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@ -0,0 +1,166 @@
/* wm_program */
/* mov (1) g4<1>F g1.8<0,1,0>UW { align1 + } */
{ 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
/* add (1) g4.4<1>F g1.8<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
/* mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 + } */
{ 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
/* add (1) g4.12<1>F g1.8<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
/* mov (1) g6<1>F g1.10<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
/* mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
/* add (1) g6.8<1>F g1.10<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
/* add (1) g6.12<1>F g1.10<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
/* mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 + } */
{ 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
/* add (1) g4.20<1>F g1.12<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
/* mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 + } */
{ 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
/* add (1) g4.28<1>F g1.12<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
/* mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
/* mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
/* add (1) g6.24<1>F g1.14<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
/* add (1) g6.28<1>F g1.14<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
/* mov (1) g5<1>F g1.16<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
/* add (1) g5.4<1>F g1.16<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
/* mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
/* add (1) g5.12<1>F g1.16<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
/* mov (1) g7<1>F g1.18<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
/* mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
/* add (1) g7.8<1>F g1.18<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
/* add (1) g7.12<1>F g1.18<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
/* mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
/* add (1) g5.20<1>F g1.20<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
/* mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
/* add (1) g5.28<1>F g1.20<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
/* mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
/* mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 + } */
{ 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
/* add (1) g7.24<1>F g1.22<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
/* add (1) g7.28<1>F g1.22<0,1,0>UW 1 { align1 + } */
{ 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
/* add (8) g4<1>F g4<8,8,1>F g1<0,1,0>F { align1 + } */
{ 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
/* add (8) g5<1>F g5<8,8,1>F g1<0,1,0>F { align1 + } */
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
/* mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 + } */
{ 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
/* mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 + } */
{ 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
/* add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 + } */
{ 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
/* add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 + } */
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
/* add (8) g6<1>F g6<8,8,1>F g1.4<0,1,0>F { align1 + } */
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
/* add (8) g7<1>F g7<8,8,1>F g1.4<0,1,0>F { align1 + } */
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
/* mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 + } */
{ 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
/* mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 + } */
{ 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
/* add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 + } */
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
/* add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 + } */
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
/* mov (8) m1<1>F g4<8,8,1>F { align1 + } */
{ 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
/* mov (8) m2<1>F g5<8,8,1>F { align1 + } */
{ 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
/* mov (8) m3<1>F g6<8,8,1>F { align1 + } */
{ 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
/* mov (8) m4<1>F g7<8,8,1>F { align1 + } */
{ 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
/* send 0 (16) g12<1>UW g0<8,8,1>UW sampler mlen 5 rlen 8 { align1 + } */
{ 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
/* mov (8) g19<1>UW g19<8,8,1>UW { align1 + } */
{ 0x00600001, 0x22600129, 0x008d0260, 0x00000000 },
/* add (8) g14<1>F g14<8,8,1>F -0.0627451{ align1 + } */
{ 0x00600040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
/* add (8) g12<1>F g12<8,8,1>F -0.501961{ align1 + } */
{ 0x00600040, 0x21807fbd, 0x008d0180, 0xbf008081 },
/* add (8) g16<1>F g16<8,8,1>F -0.501961{ align1 + } */
{ 0x00600040, 0x22007fbd, 0x008d0200, 0xbf008081 },
/* mul (8) g14<1>F g14<8,8,1>F 1.164{ align1 + } */
{ 0x00600041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
/* mul (8) a0<1>F g12<8,8,1>F 1.596{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
/* mac (8) m2<1>F g14<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
/* mul (8) a0<1>F g12<8,8,1>F -0.813{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
/* mac (8) a0<1>F g16<8,8,1>F -0.392{ align1 + } */
{ 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
/* mac (8) m3<1>F g14<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
/* mul (8) a0<1>F g16<8,8,1>F 2.017{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
/* mac (8) m4<1>F g14<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
/* add (8) g15<1>F g15<8,8,1>F -0.0627451{ align1 + } */
{ 0x00600040, 0x21e07fbd, 0x008d01e0, 0xbd808081 },
/* add (8) g13<1>F g13<8,8,1>F -0.501961{ align1 + } */
{ 0x00600040, 0x21a07fbd, 0x008d01a0, 0xbf008081 },
/* add (8) g17<1>F g17<8,8,1>F -0.501961{ align1 + } */
{ 0x00600040, 0x22207fbd, 0x008d0220, 0xbf008081 },
/* mul (8) g15<1>F g15<8,8,1>F 1.164{ align1 + } */
{ 0x00600041, 0x21e07fbd, 0x008d01e0, 0x3f94fdf4 },
/* mul (8) a0<1>F g13<8,8,1>F 1.596{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
/* mac (8) m6<1>F g15<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
/* mul (8) a0<1>F g13<8,8,1>F -0.813{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
/* mac (8) a0<1>F g17<8,8,1>F -0.392{ align1 + } */
{ 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
/* mac (8) m7<1>F g15<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
/* mul (8) a0<1>F g17<8,8,1>F 2.017{ align1 + } */
{ 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
/* mac (8) m8<1>F g15<8,8,1>F 1{ align1 + Saturate } */
{ 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
/* mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable + } */
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
/* send 0 (16) a0<1>UW g0<8,8,1>UW write mlen 10 rlen 0 EOT{ align1 + } */
{ 0x00800031, 0x20001d28, 0x008d0000, 0x85a04800 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },