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Set some mask bits to try and get yuv conversion working

This commit is contained in:
Keith Packard 2008-04-12 11:01:14 -07:00
parent 91d3e19786
commit 0fec42b64e
4 changed files with 27 additions and 11 deletions
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16
src/exa_wm.g4i
View File

@ -103,23 +103,39 @@ define(`mask_w_1', `src_w_1')
/* sample src to these registers */
define(`src_sample_base', `g14')
define(`src_sample_r', `g14')
define(`src_sample_r_01', `g14')
define(`src_sample_r_23', `g15')
define(`src_sample_g', `g16')
define(`src_sample_g_01', `g16')
define(`src_sample_g_23', `g17')
define(`src_sample_b', `g18')
define(`src_sample_b_01', `g18')
define(`src_sample_b_23', `g19')
define(`src_sample_a', `g20')
define(`src_sample_a_01', `g20')
define(`src_sample_a_23', `g21')
/* sample mask to these registers */
define(`mask_sample_base', `g22')
define(`mask_sample_r', `g22')
define(`mask_sample_r_01', `g22')
define(`mask_sample_r_23', `g23')
define(`mask_sample_g', `g24')
define(`mask_sample_g_01', `g24')
define(`mask_sample_g_23', `g25')
define(`mask_sample_b', `g26')
define(`mask_sample_b_01', `g26')
define(`mask_sample_b_23', `g27')
define(`mask_sample_a', `g28')
define(`mask_sample_a_01', `g28')
define(`mask_sample_a_23', `g29')

2
src/exa_wm_projective.g4i
View File

@ -32,7 +32,7 @@ mul (16) temp_y<1>F dst_y<8,8,1>F dw_dy { compr align1 };
add (16) temp_x<1>F temp_x<8,8,1>F temp_y<8,8,1>F { compr align1 };
add (16) temp_x<1>F temp_x<8,8,1>F wo { compr align1 };
send (8) 0 w_0<1>F temp_x_0<8,8,1>F math inv mlen 1 rlen 1 { align1 };
send (8) 0 w_1<1>F temp_x_1<8,8,1>F math inv mlen 1 rlen 1 { align1 };
send (8) 0 w_1<1>F temp_x_1<8,8,1>F math inv mlen 1 rlen 1 { sechalf align1 };
/********** Compute u *************/

10
src/exa_wm_write.g4a
View File

@ -40,13 +40,13 @@ mov (8) data_port_g_01<1>F src_sample_g_01<8,8,1>F { align1 };
mov (8) data_port_b_01<1>F src_sample_b_01<8,8,1>F { align1 };
mov (8) data_port_a_01<1>F src_sample_a_01<8,8,1>F { align1 };
mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { align1 };
mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { align1 };
mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { align1 };
mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { align1 };
mov (8) data_port_r_23<1>F src_sample_r_23<8,8,1>F { sechalf align1 };
mov (8) data_port_g_23<1>F src_sample_g_23<8,8,1>F { sechalf align1 };
mov (8) data_port_b_23<1>F src_sample_b_23<8,8,1>F { sechalf align1 };
mov (8) data_port_a_23<1>F src_sample_a_23<8,8,1>F { sechalf align1 };
/* m0, m1 are all direct passed by PS thread payload */
mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { align1 };
mov (8) data_port_msg_1<1>UD g1<8,8,1>UD { mask_disable align1 };
/* write */
send (16)

10
src/exa_wm_write.g4b
View File

@ -2,11 +2,11 @@
{ 0x00600001, 0x206003be, 0x008d0200, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 },
{ 0x00600001, 0x20c003be, 0x008d01e0, 0x00000000 },
{ 0x00600001, 0x20e003be, 0x008d0220, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
{ 0x00600001, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00601001, 0x20c003be, 0x008d01e0, 0x00000000 },
{ 0x00601001, 0x20e003be, 0x008d0220, 0x00000000 },
{ 0x00601001, 0x210003be, 0x008d0260, 0x00000000 },
{ 0x00601001, 0x212003be, 0x008d02a0, 0x00000000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },