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Use dri_bo for all object allocations, including pixmaps under uxa

This commit is contained in:
Keith Packard 2008-08-04 01:43:44 -07:00
parent 4cc20b7f6e
commit 12df8f40d2
11 changed files with 258 additions and 175 deletions
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15
src/i830.h
View File

@ -80,15 +80,22 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#include "dri_bufmgr.h"
#include "intel_bufmgr.h"
#include "i915_drm.h"
#ifdef I830_USE_EXA
#include "exa.h"
#include "uxa.h"
Bool I830EXAInit(ScreenPtr pScreen);
Bool i830_uxa_init(ScreenPtr pScreen);
unsigned long long I830TexOffsetStart(PixmapPtr pPix);
#endif
#ifdef I830_USE_UXA
#include "uxa.h"
Bool i830_uxa_init(ScreenPtr pScreen);
dri_bo *i830_uxa_get_pixmap_bo (PixmapPtr pixmap);
void i830_uxa_create_screen_resources(ScreenPtr pScreen);
void i830_uxa_block_handler (ScreenPtr pScreen);
#endif
#ifdef I830_USE_XAA
Bool I830XAAInit(ScreenPtr pScreen);
#endif
@ -194,7 +201,7 @@ struct _i830_memory {
i830_memory *prev;
/** @} */
uint32_t gem_handle;
dri_bo *bo;
uint32_t alignment;
uint32_t gem_name;
Bool lifetime_fixed_offset;
@ -530,6 +537,7 @@ typedef struct _I830Rec {
#endif
#ifdef I830_USE_UXA
uxa_driver_t *uxa_driver;
Bool need_flush;
#endif
#if defined(I830_USE_EXA) || defined(I830_USE_UXA)
PixmapPtr pSrcPixmap;
@ -818,6 +826,7 @@ Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn);
Bool i830_allocate_texture_memory(ScrnInfoPtr pScrn);
Bool i830_allocate_pwrctx(ScrnInfoPtr pScrn);
Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn);
void i830_init_bufmgr(ScrnInfoPtr pScrn);
#ifdef INTEL_XVMC
Bool i830_allocate_xvmc_buffer(ScrnInfoPtr pScrn, const char *name,
i830_memory **buffer, unsigned long size, int flags);

2
src/i830_accel.c
View File

@ -67,7 +67,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
unsigned long
intel_get_pixmap_offset(PixmapPtr pPix)
{
#ifdef I830_USE_EXA
#if defined(I830_USE_EXA) || defined(I830_USE_UXA)
ScreenPtr pScreen = pPix->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);

22
src/i830_batchbuffer.h
View File

@ -74,12 +74,24 @@ intel_batch_emit_reloc (I830Ptr pI830,
}
static inline void
intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap, uint32_t delta)
intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap,
uint32_t read_domains, uint32_t write_domain,
uint32_t delta)
{
#if I830_USE_UXA
dri_bo *bo = i830_uxa_get_pixmap_bo(pPixmap);
#endif
uint32_t offset;
assert(pI830->batch_ptr != NULL);
assert(intel_batch_space(pI830) >= 4);
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) =
intel_get_pixmap_offset(pPixmap) + delta;
#if I830_USE_UXA
if (bo) {
intel_batch_emit_reloc(pI830, bo, read_domains, write_domain, delta);
return;
}
#endif
offset = intel_get_pixmap_offset(pPixmap);
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = offset + delta;
pI830->batch_used += 4;
}
@ -88,8 +100,8 @@ intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap, uint32_t delta)
#define OUT_RELOC(bo, read_domains, write_domains, delta) \
intel_batch_emit_reloc (pI830, bo, read_domains, write_domains, delta)
#define OUT_RELOC_PIXMAP(pPixmap, delta) \
intel_batch_emit_reloc_pixmap(pI830, pPixmap, delta)
#define OUT_RELOC_PIXMAP(pPixmap, reads, write, delta) \
intel_batch_emit_reloc_pixmap(pI830, pPixmap, reads, write, delta)
union intfloat {
float f;

11
src/i830_dri.c
View File

@ -1514,23 +1514,18 @@ I830DRIClipNotify(ScreenPtr pScreen, WindowPtr *ppWin, int num)
static int
i830_name_buffer (ScrnInfoPtr pScrn, i830_memory *mem)
{
if (mem && mem->gem_handle)
if (mem && mem->bo)
{
I830Ptr pI830 = I830PTR(pScrn);
struct drm_gem_flink flink;
int ret;
if (!mem->gem_name)
{
flink.handle = mem->gem_handle;
ret = ioctl(pI830->drmSubFD, DRM_IOCTL_GEM_FLINK, &flink);
int ret;
ret = intel_bo_flink(mem->bo, &mem->gem_name);
if (ret != 0)
{
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] failed to name buffer %d\n", -errno);
return -1;
}
mem->gem_name = flink.name;
}
return mem->gem_name;
}

1
src/i830_dri.h
View File

@ -59,5 +59,4 @@ typedef struct {
int dummy;
} I830DRIContextRec, *I830DRIContextPtr;
#endif

18
src/i830_driver.c
View File

@ -849,7 +849,7 @@ i830_update_front_offset(ScrnInfoPtr pScrn)
/* If we are still in ScreenInit, there is no screen pixmap to be updated
* yet. We'll fix it up at CreateScreenResources.
*/
if (!pI830->starting) {
if (!pI830->starting && pI830->accel != ACCEL_UXA) {
if (!pScreen->ModifyPixmapHeader(pScreen->GetScreenPixmap(pScreen),
-1, -1, -1, -1, -1,
(pointer)(pI830->FbBase +
@ -876,6 +876,10 @@ i830CreateScreenResources(ScreenPtr pScreen)
i830_update_front_offset(pScrn);
#ifdef I830_USE_UXA
if (pI830->accel == ACCEL_UXA)
i830_uxa_create_screen_resources(pScreen);
#endif
return TRUE;
}
@ -2534,6 +2538,8 @@ I830BlockHandler(int i,
#endif
}
if (pI830->accel == ACCEL_UXA)
i830_uxa_block_handler (pScreen);
/*
* Check for FIFO underruns at block time (which amounts to just
* periodically). If this happens, it means our DSPARB or some other
@ -2774,12 +2780,13 @@ i830_fake_fence_wait(void *priv, unsigned int fence)
return 0;
}
static void
void
i830_init_bufmgr(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
assert(pI830->FbBase != NULL);
if (pI830->bufmgr) return;
if (pI830->memory_manager) {
int batch_size;
@ -2792,6 +2799,7 @@ i830_init_bufmgr(ScrnInfoPtr pScrn)
pI830->bufmgr = intel_bufmgr_gem_init(pI830->drmSubFD, batch_size);
intel_bufmgr_gem_enable_reuse(pI830->bufmgr);
} else {
assert(pI830->FbBase != NULL);
pI830->bufmgr = intel_bufmgr_fake_init(pI830->fake_bufmgr_mem->offset,
pI830->FbBase +
pI830->fake_bufmgr_mem->offset,
@ -3412,7 +3420,7 @@ I830LeaveVT(int scrnIndex, int flags)
}
#endif /* XF86DRI */
if (pI830->useEXA && IS_I965G(pI830))
if ((pI830->accel == ACCEL_EXA || pI830->accel == ACCEL_UXA) && IS_I965G(pI830))
gen4_render_state_cleanup(pScrn);
if (pI830->AccelInfoRec)
@ -3465,7 +3473,7 @@ I830EnterVT(int scrnIndex, int flags)
intel_batch_init(pScrn);
if (pI830->useEXA && IS_I965G(pI830))
if ((pI830->accel == ACCEL_EXA || pI830->accel == ACCEL_UXA) && IS_I965G(pI830))
gen4_render_state_init(pScrn);
if (i830_check_error_state(pScrn)) {

279
src/i830_exa.c
View File

@ -179,6 +179,7 @@ I830EXAPrepareSolid(PixmapPtr pPixmap, int alu, Pixel planemask, Pixel fg)
I830Ptr pI830 = I830PTR(pScrn);
unsigned long pitch;
I830FALLBACK("solid");
if (!EXA_PM_IS_SOLID(&pPixmap->drawable, planemask))
I830FALLBACK("planemask is not solid");
@ -238,7 +239,7 @@ I830EXASolid(PixmapPtr pPixmap, int x1, int y1, int x2, int y2)
OUT_BATCH(pI830->BR[13] | pitch);
OUT_BATCH((y1 << 16) | (x1 & 0xffff));
OUT_BATCH((y2 << 16) | (x2 & 0xffff));
OUT_RELOC_PIXMAP(pPixmap, 0);
OUT_RELOC_PIXMAP(pPixmap, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(pI830->BR[16]);
ADVANCE_BATCH();
}
@ -265,6 +266,7 @@ I830EXAPrepareCopy(PixmapPtr pSrcPixmap, PixmapPtr pDstPixmap, int xdir,
ScrnInfoPtr pScrn = xf86Screens[pDstPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
I830FALLBACK("copy");
if (!EXA_PM_IS_SOLID(&pSrcPixmap->drawable, planemask))
I830FALLBACK("planemask is not solid");
@ -331,10 +333,10 @@ I830EXACopy(PixmapPtr pDstPixmap, int src_x1, int src_y1, int dst_x1,
OUT_BATCH(pI830->BR[13] | dst_pitch);
OUT_BATCH((dst_y1 << 16) | (dst_x1 & 0xffff));
OUT_BATCH((dst_y2 << 16) | (dst_x2 & 0xffff));
OUT_RELOC_PIXMAP(pDstPixmap, 0);
OUT_RELOC_PIXMAP(pDstPixmap, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH((src_y1 << 16) | (src_x1 & 0xffff));
OUT_BATCH(src_pitch);
OUT_RELOC_PIXMAP(pI830->pSrcPixmap, 0);
OUT_RELOC_PIXMAP(pI830->pSrcPixmap, I915_GEM_DOMAIN_RENDER, 0, 0);
ADVANCE_BATCH();
}
@ -538,129 +540,212 @@ I830EXAInit(ScreenPtr pScreen)
return TRUE;
}
static Bool
i830_uxa_pixmap_is_offscreen(PixmapPtr pPixmap)
{
ScrnInfoPtr pScrn = xf86Screens[pPixmap->drawable.pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
static DevPrivateKey uxa_pixmap_key = &uxa_pixmap_key;
/* XXX for now, eventually we'll support 'real' off-screen pixmaps */
if ((void *)pPixmap->devPrivate.ptr >= (void *)pI830->FbBase &&
(void *)pPixmap->devPrivate.ptr <
(void *)(pI830->FbBase + pI830->FbMapSize))
{
return TRUE;
} else {
return FALSE;
static void
i830_uxa_set_pixmap_bo (PixmapPtr pixmap, dri_bo *bo)
{
dixSetPrivate(&pixmap->devPrivates, uxa_pixmap_key, bo);
}
dri_bo *
i830_uxa_get_pixmap_bo (PixmapPtr pixmap)
{
return dixLookupPrivate(&pixmap->devPrivates, uxa_pixmap_key);
}
static Bool
i830_uxa_prepare_access (PixmapPtr pixmap, int index)
{
dri_bo *bo = i830_uxa_get_pixmap_bo (pixmap);
if (bo) {
if (dri_bo_map (bo, index == UXA_PREPARE_DEST) != 0)
return FALSE;
assert (pixmap->devPrivate.ptr == bo->virtual);
pixmap->devPrivate.ptr = bo->virtual;
}
return TRUE;
}
void
i830_uxa_block_handler (ScreenPtr screen)
{
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
if (i830->need_flush) {
dri_bo_wait_rendering (i830->front_buffer->bo);
i830->need_flush = FALSE;
}
}
static void
i830_uxa_finish_access (PixmapPtr pixmap, int index)
{
dri_bo *bo = i830_uxa_get_pixmap_bo (pixmap);
if (bo) {
ScreenPtr screen = pixmap->drawable.pScreen;
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
dri_bo_unmap (bo);
if (bo == i830->front_buffer->bo)
i830->need_flush = TRUE;
}
}
static Bool
i830_uxa_pixmap_is_offscreen(PixmapPtr pPixmap)
{
return i830_uxa_get_pixmap_bo (pPixmap) != NULL;
}
static PixmapPtr
i830_uxa_create_pixmap (ScreenPtr screen, int w, int h, int depth, unsigned usage)
{
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
I830Ptr i830 = I830PTR(scrn);
dri_bo *bo;
int stride;
PixmapPtr pixmap;
if (w > 32767 || h > 32767)
return NullPixmap;
pixmap = fbCreatePixmap (screen, 0, 0, depth, usage);
if (w && h)
{
stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
i830->accel_pixmap_pitch_alignment);
bo = dri_bo_alloc (i830->bufmgr, "pixmap", stride * h,
i830->accel_pixmap_offset_alignment);
if (!bo) {
fbDestroyPixmap (pixmap);
return NullPixmap;
}
if (dri_bo_map (bo, FALSE) != 0) {
fbDestroyPixmap (pixmap);
dri_bo_unreference (bo);
return NullPixmap;
}
screen->ModifyPixmapHeader (pixmap, w, h, 0, 0, stride,
(pointer) bo->virtual);
dri_bo_unmap (bo);
i830_uxa_set_pixmap_bo (pixmap, bo);
}
return pixmap;
}
static Bool
i830_uxa_destroy_pixmap (PixmapPtr pixmap)
{
if (pixmap->refcnt == 1) {
dri_bo *bo = i830_uxa_get_pixmap_bo (pixmap);
if (bo) {
dri_bo_unmap (bo);
dri_bo_unreference (bo);
}
}
fbDestroyPixmap (pixmap);
return TRUE;
}
void i830_uxa_create_screen_resources(ScreenPtr pScreen)
{
ScrnInfoPtr scrn = xf86Screens[pScreen->myNum];
I830Ptr i830 = I830PTR(scrn);
dri_bo *bo = i830->front_buffer->bo;
if (bo != NULL) {
PixmapPtr pixmap = pScreen->GetScreenPixmap(pScreen);
dri_bo_map (bo, i830->front_buffer->alignment);
pixmap->devPrivate.ptr = bo->virtual;
dri_bo_unmap (bo);
i830_uxa_set_pixmap_bo (pixmap, bo);
}
}
Bool
i830_uxa_init (ScreenPtr pScreen)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
ScrnInfoPtr scrn = xf86Screens[pScreen->myNum];
I830Ptr i830 = I830PTR(scrn);
pI830->uxa_driver = uxa_driver_alloc();
if (pI830->uxa_driver == NULL) {
pI830->accel = ACCEL_NONE;
if (!dixRequestPrivate(uxa_pixmap_key, 0))
return FALSE;
i830->uxa_driver = uxa_driver_alloc();
if (i830->uxa_driver == NULL) {
i830->accel = ACCEL_NONE;
return FALSE;
}
memset(pI830->uxa_driver, 0, sizeof(*pI830->uxa_driver));
memset(i830->uxa_driver, 0, sizeof(*i830->uxa_driver));
pI830->bufferOffset = 0;
pI830->uxa_driver->uxa_major = 1;
pI830->uxa_driver->uxa_minor = 0;
i830->bufferOffset = 0;
i830->uxa_driver->uxa_major = 1;
i830->uxa_driver->uxa_minor = 0;
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 1 or 2 times the element size.
* i965 limits 3D surface pitch alignment to 512B if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so EXA doesn't need to worry.
*/
if (IS_I965G(pI830)) {
pI830->uxa_driver->maxX = 8192;
pI830->uxa_driver->maxY = 8192;
} else {
pI830->uxa_driver->maxX = 2048;
pI830->uxa_driver->maxY = 2048;
}
i830->uxa_driver->maxX = i830->accel_max_x;
i830->uxa_driver->maxY = i830->accel_max_y;
/* Sync */
pI830->uxa_driver->WaitMarker = I830EXASync;
i830->uxa_driver->WaitMarker = I830EXASync;
/* Solid fill */
pI830->uxa_driver->PrepareSolid = I830EXAPrepareSolid;
pI830->uxa_driver->Solid = I830EXASolid;
pI830->uxa_driver->DoneSolid = I830EXADoneSolid;
i830->uxa_driver->PrepareSolid = I830EXAPrepareSolid;
i830->uxa_driver->Solid = I830EXASolid;
i830->uxa_driver->DoneSolid = I830EXADoneSolid;
/* Copy */
pI830->uxa_driver->PrepareCopy = I830EXAPrepareCopy;
pI830->uxa_driver->Copy = I830EXACopy;
pI830->uxa_driver->DoneCopy = I830EXADoneCopy;
i830->uxa_driver->PrepareCopy = I830EXAPrepareCopy;
i830->uxa_driver->Copy = I830EXACopy;
i830->uxa_driver->DoneCopy = I830EXADoneCopy;
/* Composite */
if (!IS_I9XX(pI830)) {
pI830->uxa_driver->CheckComposite = i830_check_composite;
pI830->uxa_driver->PrepareComposite = i830_prepare_composite;
pI830->uxa_driver->Composite = i830_composite;
pI830->uxa_driver->DoneComposite = i830_done_composite;
} else if (IS_I915G(pI830) || IS_I915GM(pI830) ||
IS_I945G(pI830) || IS_I945GM(pI830) || IS_G33CLASS(pI830))
if (!IS_I9XX(i830)) {
i830->uxa_driver->CheckComposite = i830_check_composite;
i830->uxa_driver->PrepareComposite = i830_prepare_composite;
i830->uxa_driver->Composite = i830_composite;
i830->uxa_driver->DoneComposite = i830_done_composite;
} else if (IS_I915G(i830) || IS_I915GM(i830) ||
IS_I945G(i830) || IS_I945GM(i830) || IS_G33CLASS(i830))
{
pI830->uxa_driver->CheckComposite = i915_check_composite;
pI830->uxa_driver->PrepareComposite = i915_prepare_composite;
pI830->uxa_driver->Composite = i830_composite;
pI830->uxa_driver->DoneComposite = i830_done_composite;
i830->uxa_driver->CheckComposite = i915_check_composite;
i830->uxa_driver->PrepareComposite = i915_prepare_composite;
i830->uxa_driver->Composite = i830_composite;
i830->uxa_driver->DoneComposite = i830_done_composite;
} else {
pI830->uxa_driver->CheckComposite = i965_check_composite;
pI830->uxa_driver->PrepareComposite = i965_prepare_composite;
pI830->uxa_driver->Composite = i965_composite;
pI830->uxa_driver->DoneComposite = i830_done_composite;
i830->uxa_driver->CheckComposite = i965_check_composite;
i830->uxa_driver->PrepareComposite = i965_prepare_composite;
i830->uxa_driver->Composite = i965_composite;
i830->uxa_driver->DoneComposite = i830_done_composite;
}
pI830->uxa_driver->PixmapIsOffscreen = i830_uxa_pixmap_is_offscreen;
if(!uxa_driver_init(pScreen, pI830->uxa_driver)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
i830->uxa_driver->PrepareAccess = i830_uxa_prepare_access;
i830->uxa_driver->FinishAccess = i830_uxa_finish_access;
i830->uxa_driver->PixmapIsOffscreen = i830_uxa_pixmap_is_offscreen;
if(!uxa_driver_init(pScreen, i830->uxa_driver)) {
xf86DrvMsg(scrn->scrnIndex, X_INFO,
"UXA initialization failed\n");
xfree(pI830->uxa_driver);
pI830->accel = ACCEL_NONE;
xfree(i830->uxa_driver);
i830->accel = ACCEL_NONE;
return FALSE;
}
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
pScreen->CreatePixmap = i830_uxa_create_pixmap;
pScreen->DestroyPixmap = i830_uxa_destroy_pixmap;
I830SelectBuffer(scrn, I830_SELECT_FRONT);
return TRUE;
}

69
src/i830_memory.c
View File

@ -166,24 +166,16 @@ i830_bind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
return TRUE;
#ifdef XF86DRI
if (mem->gem_handle != 0) {
I830Ptr pI830 = I830PTR(pScrn);
struct drm_i915_gem_pin pin;
int ret;
pin.handle = mem->gem_handle;
pin.alignment = mem->alignment;
ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_PIN, &pin);
if (ret != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to pin %s: %s\n",
mem->name, strerror(errno));
if (mem->bo != NULL) {
if (intel_bo_pin (mem->bo, mem->alignment) != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to pin %s: %s\n",
mem->name, strerror(errno));
return FALSE;
}
mem->bound = TRUE;
mem->offset = pin.offset;
mem->offset = mem->bo->offset;
mem->end = mem->offset + mem->size;
}
#endif
@ -219,15 +211,8 @@ i830_unbind_memory(ScrnInfoPtr pScrn, i830_memory *mem)
i830_clear_tiling(pScrn, mem->fence_nr);
#ifdef XF86DRI
if (mem->gem_handle != 0) {
I830Ptr pI830 = I830PTR(pScrn);
struct drm_i915_gem_unpin unpin;
int ret;
unpin.handle = mem->gem_handle;
ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_UNPIN, &unpin);
if (ret == 0) {
if (mem->bo != NULL) {
if (intel_bo_unpin (mem->bo) == 0) {
mem->bound = FALSE;
/* Give buffer obviously wrong offset/end until it's re-pinned. */
mem->offset = -1;
@ -257,12 +242,9 @@ i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem)
i830_unbind_memory(pScrn, mem);
#ifdef XF86DRI
if (mem->gem_handle != 0) {
if (mem->bo != NULL) {
I830Ptr pI830 = I830PTR(pScrn);
struct drm_gem_close close;
close.handle = mem->gem_handle;
ioctl(pI830->drmSubFD, DRM_IOCTL_GEM_CLOSE, &close);
dri_bo_unreference (mem->bo);
if (pI830->bo_list == mem) {
pI830->bo_list = mem->next;
if (mem->next)
@ -493,6 +475,7 @@ i830_allocator_init(ScrnInfoPtr pScrn, unsigned long offset, unsigned long size)
i830_free_memory(pScrn, pI830->memory_manager);
pI830->memory_manager = NULL;
}
i830_init_bufmgr(pScrn);
} else {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to allocate space for kernel memory manager\n");
@ -735,8 +718,6 @@ i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
{
I830Ptr pI830 = I830PTR(pScrn);
i830_memory *mem;
int ret;
struct drm_i915_gem_create create;
assert((flags & NEED_PHYSICAL_ADDR) == 0);
@ -754,16 +735,13 @@ i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
return NULL;
}
memset(&create, 0, sizeof(create));
create.size = size;
mem->bo = dri_bo_alloc (pI830->bufmgr, name, size, align);
ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_CREATE, &create);
if (ret) {
if (!mem->bo) {
xfree(mem->name);
xfree(mem);
return NULL;
}
mem->gem_handle = create.handle;
/* Give buffer obviously wrong offset/end until it's pinned. */
mem->offset = -1;
@ -777,10 +755,7 @@ i830_allocate_memory_bo(ScrnInfoPtr pScrn, const char *name,
/* Bind it if we currently control the VT */
if (pScrn->vtSema) {
if (!i830_bind_memory(pScrn, mem)) {
struct drm_gem_close close;
close.handle = mem->gem_handle;
ioctl(pI830->drmSubFD, DRM_IOCTL_GEM_CLOSE, &close);
dri_bo_unreference (mem->bo);
xfree(mem->name);
xfree(mem);
return NULL;
@ -908,19 +883,17 @@ i830_allocate_memory_tiled(ScrnInfoPtr pScrn, const char *name,
mem->fence_nr = -1;
#ifdef XF86DRI
if (mem->gem_handle != 0) {
struct drm_i915_gem_set_tiling set_tiling;
int ret;
if (mem->bo != 0) {
uint32_t tiling_mode = I915_TILING_NONE;
int ret;
set_tiling.handle = mem->gem_handle;
if (tile_format == TILE_XMAJOR)
set_tiling.tiling_mode = I915_TILING_X;
tiling_mode = I915_TILING_X;
else
set_tiling.tiling_mode = I915_TILING_Y;
tiling_mode = I915_TILING_Y;
ret = ioctl(pI830->drmSubFD, DRM_IOCTL_I915_GEM_SET_TILING,
&set_tiling);
if (ret != 0 || set_tiling.tiling_mode == I915_TILING_NONE) {
ret = intel_bo_set_tiling (mem->bo, &tiling_mode);
if (ret != 0 || tiling_mode == I915_TILING_NONE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to set tiling on %s: %s\n",
mem->name,

4
src/i830_render.c
View File

@ -313,7 +313,7 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
BEGIN_BATCH(10);
OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 | LOAD_TEXTURE_MAP(unit) | 4);
OUT_RELOC_PIXMAP(pPix, TM0S0_USE_FENCE);
OUT_RELOC_PIXMAP(pPix, I915_GEM_DOMAIN_SAMPLER, 0, TM0S0_USE_FENCE);
OUT_BATCH(((pPix->drawable.height - 1) << TM0S1_HEIGHT_SHIFT) |
((pPix->drawable.width - 1) << TM0S1_WIDTH_SHIFT) | format);
OUT_BATCH((pitch/4 - 1) << TM0S2_PITCH_SHIFT | TM0S2_MAP_2D);
@ -444,7 +444,7 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
BUF_3D_PITCH(dst_pitch));
OUT_RELOC_PIXMAP(pDst, 0);
OUT_RELOC_PIXMAP(pDst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(MI_NOOP);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);

10
src/i915_render.c
View File

@ -322,6 +322,8 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
Bool is_affine_src, is_affine_mask;
Bool is_nearest = FALSE;
return FALSE;
i830_exa_check_pitch_3d(pSrc);
if (pMask)
i830_exa_check_pitch_3d(pMask);
@ -360,7 +362,7 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(10);
OUT_BATCH(_3DSTATE_MAP_STATE | 3);
OUT_BATCH(0x00000001); /* map 0 */
OUT_RELOC_PIXMAP(pSrc, 0);
OUT_RELOC_PIXMAP(pSrc, I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(pI830->mapstate[1]);
OUT_BATCH(pI830->mapstate[2]);
@ -374,10 +376,10 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
BEGIN_BATCH(16);
OUT_BATCH(_3DSTATE_MAP_STATE | 6);
OUT_BATCH(0x00000003); /* map 0,1 */
OUT_RELOC_PIXMAP(pSrc, 0);
OUT_RELOC_PIXMAP(pSrc, I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(pI830->mapstate[1]);
OUT_BATCH(pI830->mapstate[2]);
OUT_RELOC_PIXMAP(pMask, 0);
OUT_RELOC_PIXMAP(pMask, I915_GEM_DOMAIN_SAMPLER, 0, 0);
OUT_BATCH(pI830->mapstate[4]);
OUT_BATCH(pI830->mapstate[5]);
@ -398,7 +400,7 @@ i915_prepare_composite(int op, PicturePtr pSrcPicture,
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE|
BUF_3D_PITCH(dst_pitch));
OUT_RELOC_PIXMAP(pDst, 0);
OUT_RELOC_PIXMAP(pDst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
OUT_BATCH(dst_format);

2
src/i915_video.c
View File

@ -130,7 +130,7 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
BUF_3D_PITCH(intel_get_pixmap_pitch(pPixmap)));
OUT_RELOC_PIXMAP(pPixmap, 0);
OUT_RELOC_PIXMAP(pPixmap, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
ADVANCE_BATCH();
if (!planar) {