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sna/gen4+: Set read-write allocation mode for the target render cache 

As we often first clear the destination before performing a blend, we
get a performance boost if that first write populates the render cache.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2013-03-27 16:56:10 +00:00
parent d9b8c2039d
commit 19dfa72c28
3 changed files with 15 additions and 12 deletions
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9
src/sna/gen4_render.c
View File

@ -502,7 +502,7 @@ gen4_bind_bo(struct sna *sna,
assert(sna->kgem.gen != 040 || !kgem_bo_is_snoop(bo));
/* After the first bind, we manage the cache domains within the batch */
offset = kgem_bo_get_binding(bo, format);
offset = kgem_bo_get_binding(bo, format | is_dst << 31);
if (offset) {
if (is_dst)
kgem_bo_mark_dirty(bo);
@ -517,9 +517,10 @@ gen4_bind_bo(struct sna *sna,
GEN4_SURFACE_BLEND_ENABLED |
format << GEN4_SURFACE_FORMAT_SHIFT);
if (is_dst)
if (is_dst) {
ss[0] |= GEN4_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER;
else
} else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
@ -530,7 +531,7 @@ gen4_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = 0;
kgem_bo_set_binding(bo, format, offset);
kgem_bo_set_binding(bo, format | is_dst << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],

9
src/sna/gen5_render.c
View File

@ -490,7 +490,7 @@ gen5_bind_bo(struct sna *sna,
/* After the first bind, we manage the cache domains within the batch */
if (!DBG_NO_SURFACE_CACHE) {
offset = kgem_bo_get_binding(bo, format);
offset = kgem_bo_get_binding(bo, format | is_dst << 31);
if (offset) {
if (is_dst)
kgem_bo_mark_dirty(bo);
@ -506,9 +506,10 @@ gen5_bind_bo(struct sna *sna,
GEN5_SURFACE_BLEND_ENABLED |
format << GEN5_SURFACE_FORMAT_SHIFT);
if (is_dst)
if (is_dst) {
ss[0] |= GEN5_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 | I915_GEM_DOMAIN_RENDER;
else
} else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
@ -519,7 +520,7 @@ gen5_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = 0;
kgem_bo_set_binding(bo, format, offset);
kgem_bo_set_binding(bo, format | is_dst << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],

9
src/sna/gen6_render.c
View File

@ -1035,7 +1035,7 @@ gen6_bind_bo(struct sna *sna,
uint32_t is_scanout = is_dst && bo->scanout;
/* After the first bind, we manage the cache domains within the batch */
offset = kgem_bo_get_binding(bo, format | is_scanout << 31);
offset = kgem_bo_get_binding(bo, format | is_dst << 30 | is_scanout << 31);
if (offset) {
DBG(("[%x] bo(handle=%d), format=%d, reuse %s binding\n",
offset, bo->handle, format,
@ -1051,9 +1051,10 @@ gen6_bind_bo(struct sna *sna,
ss[0] = (GEN6_SURFACE_2D << GEN6_SURFACE_TYPE_SHIFT |
GEN6_SURFACE_BLEND_ENABLED |
format << GEN6_SURFACE_FORMAT_SHIFT);
if (is_dst)
if (is_dst) {
ss[0] |= GEN6_SURFACE_RC_READ_WRITE;
domains = I915_GEM_DOMAIN_RENDER << 16 |I915_GEM_DOMAIN_RENDER;
else
} else
domains = I915_GEM_DOMAIN_SAMPLER << 16;
ss[1] = kgem_add_reloc(&sna->kgem, offset + 1, bo, domains, 0);
ss[2] = ((width - 1) << GEN6_SURFACE_WIDTH_SHIFT |
@ -1064,7 +1065,7 @@ gen6_bind_bo(struct sna *sna,
ss[4] = 0;
ss[5] = is_scanout ? 0 : 3 << 16;
kgem_bo_set_binding(bo, format | is_scanout << 31, offset);
kgem_bo_set_binding(bo, format | is_dst << 30 | is_scanout << 31, offset);
DBG(("[%x] bind bo(handle=%d, addr=%d), format=%d, width=%d, height=%d, pitch=%d, tiling=%d -> %s\n",
offset, bo->handle, ss[1],