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sna/gen4,5: Fix setting pipe control cache flush bits 

Cache flush bits are on dword 0, not 1, on gen4 and gen5. Also texture
cache invalidate is only available from Cantiga onwards.
This commit is contained in:
Edward Sheldrake 2014-02-03 09:34:33 +00:00 committed by Chris Wilson
parent 7f08250a89
commit 1cbc59a917
3 changed files with 14 additions and 11 deletions
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17
src/sna/gen4_render.c
View File

@ -575,8 +575,10 @@ inline static void
gen4_emit_pipe_flush(struct sna *sna)
{
#if 1
OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2));
OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH);
OUT_BATCH(GEN4_PIPE_CONTROL |
GEN4_PIPE_CONTROL_WC_FLUSH |
(4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
#else
@ -600,14 +602,13 @@ gen4_emit_pipe_break(struct sna *sna)
inline static void
gen4_emit_pipe_invalidate(struct sna *sna)
{
#if 0
OUT_BATCH(GEN4_PIPE_CONTROL | (4 - 2));
OUT_BATCH(GEN4_PIPE_CONTROL_WC_FLUSH | GEN4_PIPE_CONTROL_TC_FLUSH);
OUT_BATCH(GEN4_PIPE_CONTROL |
GEN4_PIPE_CONTROL_WC_FLUSH |
(sna->kgem.gen >= 045 ? GEN4_PIPE_CONTROL_TC_FLUSH : 0) |
(4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
#else
OUT_BATCH(MI_FLUSH);
#endif
}
static void gen4_emit_primitive(struct sna *sna)

2
src/sna/gen4_render.h
View File

@ -112,7 +112,7 @@
#define GEN4_PIPE_CONTROL_DEPTH_STALL (1 << 13)
#define GEN4_PIPE_CONTROL_WC_FLUSH (1 << 12)
#define GEN4_PIPE_CONTROL_IS_FLUSH (1 << 11)
#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10)
#define GEN4_PIPE_CONTROL_TC_FLUSH (1 << 10) /* ctg+ */
#define GEN4_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
#define GEN4_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define GEN4_PIPE_CONTROL_LOCAL_PGTT (0 << 2)

6
src/sna/gen5_render.c
View File

@ -1016,8 +1016,10 @@ inline static void
gen5_emit_pipe_flush(struct sna *sna)
{
#if 0
OUT_BATCH(GEN5_PIPE_CONTROL | (4 - 2));
OUT_BATCH(GEN5_PIPE_CONTROL_WC_FLUSH);
OUT_BATCH(GEN5_PIPE_CONTROL |
GEN5_PIPE_CONTROL_WC_FLUSH |
(4 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
#else