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uxa: Simplify flush tracking 

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2012-03-10 09:26:10 +00:00
parent bd8fafe0c4
commit 219467ac8b
8 changed files with 13 additions and 35 deletions
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3
src/i830_render.c
View File

@ -563,8 +563,7 @@ i830_prepare_composite(int op, PicturePtr source_picture,
intel->s8_blendctl = blendctl;
}
if(intel_pixmap_is_dirty(source) ||
(mask && intel_pixmap_is_dirty(mask)))
if (intel_pixmap_is_dirty(source) || intel_pixmap_is_dirty(mask))
intel_batch_emit_flush(scrn);
intel->needs_render_state_emit = TRUE;

8
src/i915_render.c
View File

@ -743,11 +743,7 @@ i915_prepare_composite(int op, PicturePtr source_picture,
intel->i915_render_state.op = op;
/* BUF_INFO is an implicit flush */
if (dest != intel->render_current_dest)
intel_batch_do_flush(scrn);
else if((source && intel_pixmap_is_dirty(source)) ||
(mask && intel_pixmap_is_dirty(mask)))
if (intel_pixmap_is_dirty(source) || intel_pixmap_is_dirty(mask))
intel_batch_emit_flush(scrn);
intel->needs_render_state_emit = TRUE;
@ -906,8 +902,6 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
if (1 || dest != intel->render_current_dest) {
uint32_t tiling_bits;
intel_batch_do_flush(scrn);
if (intel_pixmap_tiled(dest)) {
tiling_bits = BUF_3D_TILED_SURFACE;
if (intel_get_pixmap_private(dest)->tiling

3
src/i965_render.c
View File

@ -2035,8 +2035,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
}
/* Flush any pending writes prior to relocating the textures. */
if (intel_pixmap_is_dirty(source) ||
(mask && intel_pixmap_is_dirty(mask)))
if (intel_pixmap_is_dirty(source) || intel_pixmap_is_dirty(mask))
intel_batch_emit_flush(scrn);
composite_op->op = op;

7
src/intel.h
View File

@ -82,12 +82,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
struct intel_pixmap {
dri_bo *bo;
struct list flush, batch;
struct list batch;
uint16_t stride;
uint8_t tiling;
int8_t busy :2;
int8_t batch_write :1;
int8_t dirty :1;
int8_t offscreen :1;
int8_t pinned :1;
};
@ -121,7 +121,7 @@ static inline void intel_set_pixmap_private(PixmapPtr pixmap, struct intel_pixma
static inline Bool intel_pixmap_is_dirty(PixmapPtr pixmap)
{
return !list_is_empty(&intel_get_pixmap_private(pixmap)->flush);
return pixmap && intel_get_pixmap_private(pixmap)->dirty;
}
static inline Bool intel_pixmap_tiled(PixmapPtr pixmap)
@ -188,7 +188,6 @@ typedef struct intel_screen_private {
/** Ending batch_used that was verified by intel_start_batch_atomic() */
int batch_atomic_limit;
struct list batch_pixmaps;
struct list flush_pixmaps;
drm_intel_bo *wa_scratch_bo;
OsTimerPtr cache_expire;

15
src/intel_batchbuffer.c
View File

@ -114,17 +114,15 @@ void intel_batch_teardown(ScrnInfoPtr scrn)
while (!list_is_empty(&intel->batch_pixmaps))
list_del(intel->batch_pixmaps.next);
while (!list_is_empty(&intel->flush_pixmaps))
list_del(intel->flush_pixmaps.next);
}
void intel_batch_do_flush(ScrnInfoPtr scrn)
static void intel_batch_do_flush(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct intel_pixmap *priv;
while (!list_is_empty(&intel->flush_pixmaps))
list_del(intel->flush_pixmaps.next);
list_for_each_entry(priv, &intel->batch_pixmaps, batch)
priv->dirty = 0;
}
static void intel_emit_post_sync_nonzero_flush(ScrnInfoPtr scrn)
@ -268,13 +266,10 @@ void intel_batch_submit(ScrnInfoPtr scrn)
batch);
entry->busy = -1;
entry->batch_write = 0;
entry->dirty = 0;
list_del(&entry->batch);
}
while (!list_is_empty(&intel->flush_pixmaps))
list_del(intel->flush_pixmaps.next);
if (intel->debug_flush & DEBUG_FLUSH_WAIT)
drm_intel_bo_wait_rendering(intel->batch_bo);

5
src/intel_batchbuffer.h
View File

@ -36,7 +36,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
void intel_batch_init(ScrnInfoPtr scrn);
void intel_batch_teardown(ScrnInfoPtr scrn);
void intel_batch_emit_flush(ScrnInfoPtr scrn);
void intel_batch_do_flush(ScrnInfoPtr scrn);
void intel_batch_submit(ScrnInfoPtr scrn);
static inline int intel_batch_space(intel_screen_private *intel)
@ -132,10 +131,8 @@ intel_batch_mark_pixmap_domains(intel_screen_private *intel,
if (list_is_empty(&priv->batch))
list_add(&priv->batch, &intel->batch_pixmaps);
if (write_domain && list_is_empty(&priv->flush))
list_add(&priv->flush, &intel->flush_pixmaps);
priv->batch_write |= write_domain != 0;
priv->dirty |= write_domain != 0;
priv->busy = 1;
intel->needs_flush |= write_domain != 0;

1
src/intel_driver.c
View File

@ -402,7 +402,6 @@ static int intel_init_bufmgr(intel_screen_private *intel)
drm_intel_bufmgr_gem_enable_fenced_relocs(intel->bufmgr);
list_init(&intel->batch_pixmaps);
list_init(&intel->flush_pixmaps);
if ((INTEL_INFO(intel)->gen == 60)) {
intel->wa_scratch_bo =

6
src/intel_uxa.c
View File

@ -643,7 +643,6 @@ void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
dri_bo_unreference(priv->bo);
list_del(&priv->batch);
list_del(&priv->flush);
if (intel->render_current_dest == pixmap)
intel->render_current_dest = NULL;
@ -660,7 +659,6 @@ void intel_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
goto BAIL;
list_init(&priv->batch);
list_init(&priv->flush);
}
dri_bo_reference(bo);
@ -710,8 +708,7 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
/* When falling back to swrast, flush all pending operations */
intel_glamor_flush(intel);
if (!list_is_empty(&priv->batch) &&
(access == UXA_ACCESS_RW || priv->batch_write))
if (access == UXA_ACCESS_RW || priv->dirty)
intel_batch_submit(scrn);
assert(bo->size <= intel->max_gtt_map_size);
@ -1105,7 +1102,6 @@ intel_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
priv->offscreen = 1;
list_init(&priv->batch);
list_init(&priv->flush);
intel_set_pixmap_private(pixmap, priv);
screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL);