batch: Track pixmap domains.
In order to detect when we require cache flushes we need to track which domains the pixmap currently belongs to. So to do so we create a device private structure to hold the extra information and hook it up. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
2c3aee2b57
commit
285f286597
83
src/i830.h
83
src/i830.h
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@ -77,6 +77,87 @@ void i830_uxa_block_handler(ScreenPtr pScreen);
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Bool i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table,
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int num_bos);
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/* classic doubly-link circular list */
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struct list {
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struct list *next, *prev;
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};
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static void
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list_init(struct list *list)
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{
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list->next = list->prev = list;
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}
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static inline void
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__list_add(struct list *entry,
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struct list *prev,
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struct list *next)
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{
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next->prev = entry;
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entry->next = next;
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entry->prev = prev;
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prev->next = entry;
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}
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static inline void
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list_add(struct list *entry, struct list *head)
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{
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__list_add(entry, head, head->next);
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}
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static inline void
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__list_del(struct list *prev, struct list *next)
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{
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next->prev = prev;
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prev->next = next;
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}
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static inline void
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list_del(struct list *entry)
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{
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__list_del(entry->prev, entry->next);
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list_init(entry);
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}
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static inline Bool
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list_is_empty(struct list *head)
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{
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return head->next == head;
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}
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#ifndef container_of
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#define container_of(ptr, type, member) \
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(type *)((char *)(ptr) - (char *) &((type *)0)->member)
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#endif
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#define list_entry(ptr, type, member) \
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container_of(ptr, type, member)
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#define list_first_entry(ptr, type, member) \
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list_entry((ptr)->next, type, member)
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struct intel_pixmap {
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dri_bo *bo;
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uint32_t tiling;
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uint32_t flush_write_domain;
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uint32_t flush_read_domains;
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uint32_t batch_write_domain;
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uint32_t batch_read_domains;
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struct list flush, batch;
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};
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struct intel_pixmap *i830_get_pixmap_intel(PixmapPtr pixmap);
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static inline Bool i830_uxa_pixmap_is_dirty(PixmapPtr pixmap)
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{
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return i830_get_pixmap_intel(pixmap)->flush_write_domain != 0;
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}
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static inline Bool i830_pixmap_tiled(PixmapPtr pixmap)
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{
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return i830_get_pixmap_intel(pixmap)->tiling != I915_TILING_NONE;
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}
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dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap);
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void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo);
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@ -194,6 +275,8 @@ typedef struct intel_screen_private {
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Bool in_batch_atomic;
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/** Ending batch_used that was verified by i830_start_batch_atomic() */
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int batch_atomic_limit;
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struct list batch_pixmaps;
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struct list flush_pixmaps;
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/* For Xvideo */
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Bool use_drmmode_overlay;
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@ -63,35 +63,16 @@ void I830Sync(ScrnInfoPtr scrn)
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if (!scrn->vtSema || !intel->batch_bo)
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return;
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I830EmitFlush(scrn);
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intel_batch_flush(scrn, TRUE);
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intel_batch_wait_last(scrn);
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}
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void I830EmitFlush(ScrnInfoPtr scrn)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
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if (IS_I965G(intel))
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flags = 0;
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{
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BEGIN_BATCH(1);
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OUT_BATCH(MI_FLUSH | flags);
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ADVANCE_BATCH();
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}
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}
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void i830_debug_flush(ScrnInfoPtr scrn)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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if (intel->debug_flush & DEBUG_FLUSH_BATCHES)
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if (intel->debug_flush & (DEBUG_FLUSH_BATCHES | DEBUG_FLUSH_CACHES))
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intel_batch_flush(scrn, FALSE);
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else if (intel->debug_flush & DEBUG_FLUSH_CACHES)
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I830EmitFlush(scrn);
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}
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/* The following function sets up the supported acceleration. Call it
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@ -90,17 +90,45 @@ void intel_batch_teardown(ScrnInfoPtr scrn)
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}
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}
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void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed)
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void intel_batch_pipelined_flush(ScrnInfoPtr scrn)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int ret;
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int flags;
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assert (!intel->in_batch_atomic);
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if (intel->batch_used == 0)
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return;
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if (intel->debug_flush & DEBUG_FLUSH_CACHES) {
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/* Big hammer, look to the pipelined flushes in future. */
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flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
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if (IS_I965G(intel))
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flags = 0;
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BEGIN_BATCH(1);
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OUT_BATCH(MI_FLUSH | flags);
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ADVANCE_BATCH();
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while (!list_is_empty(&intel->flush_pixmaps)) {
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struct intel_pixmap *entry;
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entry = list_first_entry(&intel->flush_pixmaps,
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struct intel_pixmap,
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flush);
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entry->flush_read_domains = entry->flush_write_domain = 0;
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list_del(&entry->flush);
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}
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}
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void intel_batch_flush(ScrnInfoPtr scrn, Bool flush)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int ret;
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assert (!intel->in_batch_atomic);
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if (flush || intel->debug_flush & DEBUG_FLUSH_CACHES) {
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int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
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if (IS_I965G(intel))
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@ -111,6 +139,9 @@ void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed)
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intel->batch_used += 4;
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}
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if (intel->batch_used == 0)
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return;
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/* Emit a padding dword if we aren't going to be quad-word aligned. */
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if ((intel->batch_used & 4) == 0) {
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*(uint32_t *) (intel->batch_ptr + intel->batch_used) = MI_NOOP;
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@ -132,6 +163,27 @@ void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed)
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FatalError("Failed to submit batchbuffer: %s\n",
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strerror(-ret));
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while (!list_is_empty(&intel->batch_pixmaps)) {
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struct intel_pixmap *entry;
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entry = list_first_entry(&intel->batch_pixmaps,
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struct intel_pixmap,
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batch);
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entry->batch_read_domains = entry->batch_write_domain = 0;
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list_del(&entry->batch);
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}
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while (!list_is_empty(&intel->flush_pixmaps)) {
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struct intel_pixmap *entry;
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entry = list_first_entry(&intel->flush_pixmaps,
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struct intel_pixmap,
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flush);
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entry->flush_read_domains = entry->flush_write_domain = 0;
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list_del(&entry->flush);
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}
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/* Save a ref to the last batch emitted, which we use for syncing
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* in debug code.
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*/
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@ -32,9 +32,11 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define BATCH_RESERVED 16
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void intel_batch_init(ScrnInfoPtr scrn);
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void intel_batch_teardown(ScrnInfoPtr scrn);
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void intel_batch_flush(ScrnInfoPtr scrn, Bool flushed);
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void intel_batch_pipelined_flush(ScrnInfoPtr scrn);
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void intel_batch_flush(ScrnInfoPtr scrn, Bool flush);
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void intel_batch_wait_last(ScrnInfoPtr scrn);
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static inline int intel_batch_space(intel_screen_private *intel)
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@ -92,15 +94,42 @@ intel_batch_emit_reloc(intel_screen_private *intel,
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intel->batch_used += 4;
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}
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static inline void
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intel_batch_mark_pixmap_domains(intel_screen_private *intel,
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struct intel_pixmap *priv,
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uint32_t read_domains, uint32_t write_domain)
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{
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assert (read_domains);
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assert (write_domain == 0 || write_domain == read_domains);
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assert (write_domain == 0 ||
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priv->flush_write_domain == 0 ||
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priv->flush_write_domain == write_domain);
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priv->flush_read_domains |= read_domains;
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priv->batch_read_domains |= read_domains;
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priv->flush_write_domain |= write_domain;
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priv->batch_write_domain |= write_domain;
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if (list_is_empty(&priv->batch))
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list_add(&priv->batch, &intel->batch_pixmaps);
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if (list_is_empty(&priv->flush))
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list_add(&priv->flush, &intel->flush_pixmaps);
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}
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static inline void
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intel_batch_emit_reloc_pixmap(intel_screen_private *intel, PixmapPtr pixmap,
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uint32_t read_domains, uint32_t write_domain,
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uint32_t delta)
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{
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dri_bo *bo = i830_get_pixmap_bo(pixmap);
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struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap);
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assert(intel->batch_ptr != NULL);
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assert(intel_batch_space(intel) >= 4);
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intel_batch_emit_reloc(intel, bo, read_domains, write_domain, delta);
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intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain);
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intel_batch_emit_reloc(intel, priv->bo,
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read_domains, write_domain,
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delta);
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}
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#define OUT_BATCH(dword) intel_batch_emit_dword(intel, dword)
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@ -349,12 +349,10 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion,
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/* Emit a flush of the rendering cache, or on the 965 and beyond
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* rendering results may not hit the framebuffer until significantly
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* later.
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*/
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I830EmitFlush(scrn);
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intel->need_mi_flush = FALSE;
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/* We can't rely on getting into the block handler before the DRI
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*
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* We can't rely on getting into the block handler before the DRI
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* client gets to run again so flush now. */
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intel->need_mi_flush = FALSE;
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intel_batch_flush(scrn, TRUE);
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#if ALWAYS_SYNC
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I830Sync(scrn);
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@ -985,20 +985,19 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
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screen->BlockHandler = I830BlockHandler;
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if (scrn->vtSema) {
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Bool flushed = FALSE;
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Bool flush = FALSE;
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/* Emit a flush of the rendering cache, or on the 965 and beyond
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* rendering results may not hit the framebuffer until significantly
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* later.
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*/
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if (intel->need_mi_flush || intel->batch_used) {
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flushed = TRUE;
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I830EmitFlush(scrn);
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}
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if (intel->need_mi_flush || intel->batch_used)
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flush = TRUE;
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/* Flush the batch, so that any rendering is executed in a timely
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* fashion.
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*/
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intel_batch_flush(scrn, flushed);
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intel_batch_flush(scrn, flush);
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drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE);
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intel->need_mi_flush = FALSE;
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@ -1138,6 +1137,9 @@ void i830_init_bufmgr(ScrnInfoPtr scrn)
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intel->bufmgr = intel_bufmgr_gem_init(intel->drmSubFD, batch_size);
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intel_bufmgr_gem_enable_reuse(intel->bufmgr);
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list_init(&intel->batch_pixmaps);
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list_init(&intel->flush_pixmaps);
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}
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Bool i830_crtc_on(xf86CrtcPtr crtc)
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235
src/i830_uxa.c
235
src/i830_uxa.c
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@ -79,31 +79,6 @@ const int I830PatternROP[16] = {
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static int uxa_pixmap_index;
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/**
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* Returns whether a given pixmap is tiled or not.
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*
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* Currently, we only have one pixmap that might be tiled, which is the front
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* buffer. At the point where we are tiling some pixmaps managed by the
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* general allocator, we should move this to using pixmap privates.
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*/
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Bool i830_pixmap_tiled(PixmapPtr pixmap)
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{
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dri_bo *bo;
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uint32_t tiling_mode, swizzle_mode;
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int ret;
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bo = i830_get_pixmap_bo(pixmap);
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assert(bo != NULL);
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ret = drm_intel_bo_get_tiling(bo, &tiling_mode, &swizzle_mode);
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if (ret != 0) {
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FatalError("Couldn't get tiling on bo %p: %s\n",
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bo, strerror(-ret));
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}
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return tiling_mode != I915_TILING_NONE;
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}
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Bool
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i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table,
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int num_bos)
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@ -143,6 +118,62 @@ static int i830_pixmap_pitch_is_aligned(PixmapPtr pixmap)
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intel->accel_pixmap_pitch_alignment == 0;
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}
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static unsigned int
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i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
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int w, int h,
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uint32_t *tiling,
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int *stride)
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{
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ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int pitch_align;
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int size;
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if (*tiling != I915_TILING_NONE) {
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/* First check whether tiling is necessary. */
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pitch_align = intel->accel_pixmap_pitch_alignment;
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size = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
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pitch_align) * ALIGN (h, 2);
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if (size < 4096)
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*tiling = I915_TILING_NONE;
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}
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if (*tiling == I915_TILING_NONE) {
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pitch_align = intel->accel_pixmap_pitch_alignment;
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} else {
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pitch_align = 512;
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}
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*stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
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pitch_align);
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if (*tiling == I915_TILING_NONE) {
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/* Round the height up so that the GPU's access to a 2x2 aligned
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* subspan doesn't address an invalid page offset beyond the
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* end of the GTT.
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*/
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size = *stride * ALIGN(h, 2);
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} else {
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int aligned_h = h;
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if (*tiling == I915_TILING_X)
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aligned_h = ALIGN(h, 8);
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else
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aligned_h = ALIGN(h, 32);
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*stride = i830_get_fence_pitch(intel, *stride, *tiling);
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/* Round the object up to the size of the fence it will live in
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* if necessary. We could potentially make the kernel allocate
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* a larger aperture space and just bind the subset of pages in,
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* but this is easier and also keeps us out of trouble (as much)
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* with drm_intel_bufmgr_check_aperture().
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*/
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size = i830_get_fence_size(intel, *stride * aligned_h);
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assert(size >= *stride * aligned_h);
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}
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return size;
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}
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/**
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* Sets up hardware state for a series of solid fills.
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*/
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@ -452,25 +483,71 @@ Bool i830_transform_is_affine(PictTransformPtr t)
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return t->matrix[2][0] == 0 && t->matrix[2][1] == 0;
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}
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dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap)
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struct intel_pixmap *i830_get_pixmap_intel(PixmapPtr pixmap)
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{
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return dixLookupPrivate(&pixmap->devPrivates, &uxa_pixmap_index);
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}
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void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
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static void i830_uxa_set_pixmap_intel(PixmapPtr pixmap, struct intel_pixmap *intel)
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{
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dri_bo *old_bo = i830_get_pixmap_bo(pixmap);
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if (old_bo)
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dri_bo_unreference(old_bo);
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if (bo != NULL)
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dri_bo_reference(bo);
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dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, bo);
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dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, intel);
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}
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static void i830_uxa_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
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dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap)
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{
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dixSetPrivate(&pixmap->devPrivates, &uxa_pixmap_index, bo);
|
||||
struct intel_pixmap *intel;
|
||||
|
||||
intel = i830_get_pixmap_intel(pixmap);
|
||||
if (intel == NULL)
|
||||
return NULL;
|
||||
|
||||
return intel->bo;
|
||||
}
|
||||
|
||||
void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
|
||||
{
|
||||
struct intel_pixmap *priv;
|
||||
|
||||
priv = i830_get_pixmap_intel(pixmap);
|
||||
|
||||
if (priv != NULL) {
|
||||
dri_bo_unreference(priv->bo);
|
||||
|
||||
priv->flush_read_domains = priv->flush_write_domain = 0;
|
||||
priv->batch_read_domains = priv->batch_write_domain = 0;
|
||||
list_del(&priv->batch);
|
||||
list_del(&priv->flush);
|
||||
}
|
||||
|
||||
if (bo != NULL) {
|
||||
uint32_t swizzle_mode;
|
||||
int ret;
|
||||
|
||||
if (priv == NULL) {
|
||||
priv = xcalloc(1, sizeof (struct intel_pixmap));
|
||||
if (priv == NULL)
|
||||
goto BAIL;
|
||||
}
|
||||
|
||||
dri_bo_reference(bo);
|
||||
priv->bo = bo;
|
||||
|
||||
ret = drm_intel_bo_get_tiling(bo,
|
||||
&priv->tiling,
|
||||
&swizzle_mode);
|
||||
if (ret != 0) {
|
||||
FatalError("Couldn't get tiling on bo %p: %s\n",
|
||||
bo, strerror(-ret));
|
||||
}
|
||||
} else {
|
||||
if (priv != NULL) {
|
||||
xfree(priv);
|
||||
priv = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
BAIL:
|
||||
i830_uxa_set_pixmap_intel(pixmap, priv);
|
||||
}
|
||||
|
||||
static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
|
||||
|
|
@ -562,8 +639,6 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
|
|||
{
|
||||
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
|
||||
intel_screen_private *intel = intel_get_screen_private(scrn);
|
||||
dri_bo *bo;
|
||||
int stride;
|
||||
PixmapPtr pixmap;
|
||||
|
||||
if (w > 32767 || h > 32767)
|
||||
|
|
@ -575,46 +650,25 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
|
|||
pixmap = fbCreatePixmap(screen, 0, 0, depth, usage);
|
||||
|
||||
if (w && h) {
|
||||
struct intel_pixmap *priv;
|
||||
unsigned int size;
|
||||
uint32_t tiling = I915_TILING_NONE;
|
||||
int pitch_align;
|
||||
int stride;
|
||||
|
||||
if (usage == INTEL_CREATE_PIXMAP_TILING_X) {
|
||||
tiling = I915_TILING_X;
|
||||
pitch_align = 512;
|
||||
} else if (usage == INTEL_CREATE_PIXMAP_TILING_Y) {
|
||||
tiling = I915_TILING_Y;
|
||||
pitch_align = 512;
|
||||
} else {
|
||||
pitch_align = intel->accel_pixmap_pitch_alignment;
|
||||
priv = xcalloc(1, sizeof (struct intel_pixmap));
|
||||
if (priv == NULL) {
|
||||
fbDestroyPixmap(pixmap);
|
||||
return NullPixmap;
|
||||
}
|
||||
|
||||
stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
|
||||
pitch_align);
|
||||
if (usage == INTEL_CREATE_PIXMAP_TILING_X)
|
||||
priv->tiling = I915_TILING_X;
|
||||
else if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
|
||||
priv->tiling = I915_TILING_Y;
|
||||
else
|
||||
priv->tiling = I915_TILING_NONE;
|
||||
|
||||
if (tiling == I915_TILING_NONE) {
|
||||
/* Round the height up so that the GPU's access to a 2x2 aligned
|
||||
* subspan doesn't address an invalid page offset beyond the
|
||||
* end of the GTT.
|
||||
*/
|
||||
size = stride * ALIGN(h, 2);
|
||||
} else {
|
||||
int aligned_h = h;
|
||||
if (tiling == I915_TILING_X)
|
||||
aligned_h = ALIGN(h, 8);
|
||||
else
|
||||
aligned_h = ALIGN(h, 32);
|
||||
|
||||
stride = i830_get_fence_pitch(intel, stride, tiling);
|
||||
/* Round the object up to the size of the fence it will live in
|
||||
* if necessary. We could potentially make the kernel allocate
|
||||
* a larger aperture space and just bind the subset of pages in,
|
||||
* but this is easier and also keeps us out of trouble (as much)
|
||||
* with drm_intel_bufmgr_check_aperture().
|
||||
*/
|
||||
size = i830_get_fence_size(intel, stride * aligned_h);
|
||||
assert(size >= stride * aligned_h);
|
||||
}
|
||||
size = i830_uxa_pixmap_compute_size(pixmap, w, h,
|
||||
&priv->tiling, &stride);
|
||||
|
||||
/* Fail very large allocations on 32-bit systems. Large BOs will
|
||||
* tend to hit SW fallbacks frequently, and also will tend to fail
|
||||
|
|
@ -626,27 +680,34 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
|
|||
*/
|
||||
if (sizeof(unsigned long) == 4 &&
|
||||
size > (unsigned int)(1024 * 1024 * 1024)) {
|
||||
xfree(priv);
|
||||
fbDestroyPixmap(pixmap);
|
||||
return NullPixmap;
|
||||
}
|
||||
|
||||
if (usage == UXA_CREATE_PIXMAP_FOR_MAP)
|
||||
bo = drm_intel_bo_alloc(intel->bufmgr, "pixmap", size,
|
||||
0);
|
||||
priv->bo = drm_intel_bo_alloc(intel->bufmgr,
|
||||
"pixmap", size, 0);
|
||||
else
|
||||
bo = drm_intel_bo_alloc_for_render(intel->bufmgr,
|
||||
"pixmap", size, 0);
|
||||
if (!bo) {
|
||||
priv->bo = drm_intel_bo_alloc_for_render(intel->bufmgr,
|
||||
"pixmap",
|
||||
size, 0);
|
||||
if (!priv->bo) {
|
||||
xfree(priv);
|
||||
fbDestroyPixmap(pixmap);
|
||||
return NullPixmap;
|
||||
}
|
||||
|
||||
if (tiling != I915_TILING_NONE)
|
||||
drm_intel_bo_set_tiling(bo, &tiling, stride);
|
||||
if (priv->tiling != I915_TILING_NONE)
|
||||
drm_intel_bo_set_tiling(priv->bo,
|
||||
&priv->tiling,
|
||||
stride);
|
||||
|
||||
screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, stride, NULL);
|
||||
|
||||
i830_uxa_set_pixmap_bo(pixmap, bo);
|
||||
list_init(&priv->batch);
|
||||
list_init(&priv->flush);
|
||||
i830_uxa_set_pixmap_intel(pixmap, priv);
|
||||
}
|
||||
|
||||
return pixmap;
|
||||
|
|
@ -654,16 +715,13 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
|
|||
|
||||
static Bool i830_uxa_destroy_pixmap(PixmapPtr pixmap)
|
||||
{
|
||||
if (pixmap->refcnt == 1) {
|
||||
dri_bo *bo = i830_get_pixmap_bo(pixmap);
|
||||
|
||||
if (bo)
|
||||
dri_bo_unreference(bo);
|
||||
}
|
||||
if (pixmap->refcnt == 1)
|
||||
i830_set_pixmap_bo(pixmap, NULL);
|
||||
fbDestroyPixmap(pixmap);
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
|
||||
void i830_uxa_create_screen_resources(ScreenPtr screen)
|
||||
{
|
||||
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
|
||||
|
|
@ -672,8 +730,7 @@ void i830_uxa_create_screen_resources(ScreenPtr screen)
|
|||
|
||||
if (bo != NULL) {
|
||||
PixmapPtr pixmap = screen->GetScreenPixmap(screen);
|
||||
i830_uxa_set_pixmap_bo(pixmap, bo);
|
||||
dri_bo_reference(bo);
|
||||
i830_set_pixmap_bo(pixmap, bo);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -1046,13 +1046,14 @@ static sampler_state_extend_t sampler_state_extend_from_picture(int repeat_type)
|
|||
* picture in the given surface state buffer.
|
||||
*/
|
||||
static void
|
||||
i965_set_picture_surface_state(dri_bo * ss_bo, int ss_index,
|
||||
i965_set_picture_surface_state(intel_screen_private *intel,
|
||||
dri_bo * ss_bo, int ss_index,
|
||||
PicturePtr picture, PixmapPtr pixmap,
|
||||
Bool is_dst)
|
||||
{
|
||||
struct brw_surface_state_padded *ss;
|
||||
struct brw_surface_state local_ss;
|
||||
dri_bo *pixmap_bo = i830_get_pixmap_bo(pixmap);
|
||||
struct intel_pixmap *priv = i830_get_pixmap_intel(pixmap);
|
||||
|
||||
ss = (struct brw_surface_state_padded *)ss_bo->virtual + ss_index;
|
||||
|
||||
|
|
@ -1082,7 +1083,7 @@ i965_set_picture_surface_state(dri_bo * ss_bo, int ss_index,
|
|||
local_ss.ss0.vert_line_stride_ofs = 0;
|
||||
local_ss.ss0.mipmap_layout_mode = 0;
|
||||
local_ss.ss0.render_cache_read_mode = 0;
|
||||
local_ss.ss1.base_addr = pixmap_bo->offset;
|
||||
local_ss.ss1.base_addr = priv->bo->offset;
|
||||
|
||||
local_ss.ss2.mip_count = 0;
|
||||
local_ss.ss2.render_target_rotation = 0;
|
||||
|
|
@ -1094,7 +1095,7 @@ i965_set_picture_surface_state(dri_bo * ss_bo, int ss_index,
|
|||
|
||||
memcpy(ss, &local_ss, sizeof(local_ss));
|
||||
|
||||
if (pixmap_bo != NULL) {
|
||||
if (priv->bo != NULL) {
|
||||
uint32_t write_domain, read_domains;
|
||||
|
||||
if (is_dst) {
|
||||
|
|
@ -1104,11 +1105,13 @@ i965_set_picture_surface_state(dri_bo * ss_bo, int ss_index,
|
|||
write_domain = 0;
|
||||
read_domains = I915_GEM_DOMAIN_SAMPLER;
|
||||
}
|
||||
|
||||
intel_batch_mark_pixmap_domains(intel, priv, read_domains, write_domain);
|
||||
dri_bo_emit_reloc(ss_bo, read_domains, write_domain,
|
||||
0,
|
||||
ss_index * sizeof(*ss) +
|
||||
offsetof(struct brw_surface_state, ss1),
|
||||
pixmap_bo);
|
||||
priv->bo);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -1508,14 +1511,14 @@ i965_prepare_composite(int op, PicturePtr source_picture,
|
|||
return FALSE;
|
||||
}
|
||||
/* Set up the state buffer for the destination surface */
|
||||
i965_set_picture_surface_state(surface_state_bo, 0,
|
||||
i965_set_picture_surface_state(intel, surface_state_bo, 0,
|
||||
dest_picture, dest, TRUE);
|
||||
/* Set up the source surface state buffer */
|
||||
i965_set_picture_surface_state(surface_state_bo, 1,
|
||||
i965_set_picture_surface_state(intel, surface_state_bo, 1,
|
||||
source_picture, source, FALSE);
|
||||
if (mask) {
|
||||
/* Set up the mask surface state buffer */
|
||||
i965_set_picture_surface_state(surface_state_bo, 2,
|
||||
i965_set_picture_surface_state(intel, surface_state_bo, 2,
|
||||
mask_picture, mask, FALSE);
|
||||
}
|
||||
dri_bo_unmap(surface_state_bo);
|
||||
|
|
|
|||
Loading…
Reference in New Issue