Aurelien
/
xf86-video-intel
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of ssh://git.freedesktop.org/git/xorg/driver/xf86-video-intel 

Conflicts:

	src/i830_display.c
This commit is contained in:
Jesse Barnes 2008-07-31 13:10:19 -07:00 committed by Jesse Barnes
parent 2049ba211e 76eb8e6f1f
commit 2aaa207db2
5 changed files with 17 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/common.h
View File

@ -374,6 +374,8 @@ extern int I810_DEBUG;
/* chipsets require status page in non stolen memory */
#define HWS_NEED_NONSTOLEN(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_GM45(pI810) || IS_G4X(pI810))
/* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_GM45(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))

3
src/i830_display.c
View File

@ -1477,7 +1477,8 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
/* Wait for the clocks to stabilize. */
usleep(150);
i830_update_dsparb(pScrn);
if (!DSPARB_HWCONTROL(pI830))
i830_update_dsparb(pScrn);
OUTREG(htot_reg, (adjusted_mode->CrtcHDisplay - 1) |
((adjusted_mode->CrtcHTotal - 1) << 16));

8
src/i830_driver.c
View File

@ -2018,7 +2018,8 @@ SaveHWState(ScrnInfoPtr pScrn)
}
/* Save video mode information for native mode-setting. */
pI830->saveDSPARB = INREG(DSPARB);
if (!DSPARB_HWCONTROL(pI830))
pI830->saveDSPARB = INREG(DSPARB);
pI830->saveDSPACNTR = INREG(DSPACNTR);
pI830->savePIPEACONF = INREG(PIPEACONF);
@ -2161,7 +2162,8 @@ RestoreHWState(ScrnInfoPtr pScrn)
if (!IS_I830(pI830) && !IS_845G(pI830))
OUTREG(PFIT_CONTROL, pI830->savePFIT_CONTROL);
OUTREG(DSPARB, pI830->saveDSPARB);
if (!DSPARB_HWCONTROL(pI830))
OUTREG(DSPARB, pI830->saveDSPARB);
OUTREG(DSPCLK_GATE_D, pI830->saveDSPCLK_GATE_D);
OUTREG(RENCLK_GATE_D1, pI830->saveRENCLK_GATE_D1);
@ -2512,7 +2514,7 @@ I830BlockHandler(int i,
* (except for mode setting, where it may occur naturally).
* Check & ack the condition.
*/
if (pScrn->vtSema) {
if (pScrn->vtSema && !DSPARB_HWCONTROL(pI830)) {
if (xf86_config->crtc[0]->enabled &&
(INREG(PIPEASTAT) & FIFO_UNDERRUN)) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "underrun on pipe A!\n");

9
src/i830_sdvo.c
View File

@ -228,23 +228,30 @@ const static struct _sdvo_cmd_name {
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
/* HDMI op code */
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
};
static I2CSlaveAddr slaveAddr;

2
src/i830_sdvo_regs.h
View File

@ -503,8 +503,6 @@ struct i830_sdvo_enhancements_arg {
# define SDVO_DITHER_ON (1 << 0)
# define SDVO_DITHER_DEFAULT_ON (1 << 1)
#define SDVO_CMD_SET_TV_RESOLUTION_SUPPORT 0x93
#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
# define SDVO_CONTROL_BUS_PROM (1 << 0)
# define SDVO_CONTROL_BUS_DDC1 (1 << 1)