Remove error state dumping code.
This is replaced by intel_gpu_dump, and would no longer be used once UMS is gone.
This commit is contained in:
Eric Anholt
parent
2370af32fe
commit
33c488e836
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@ -105,10 +105,6 @@ I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis)
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} else if (now - start > timeout_millis) {
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ErrorF("Error in I830WaitLpRing(), timeout for %d seconds\n",
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timeout_millis/1000);
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if (IS_I965G(pI830))
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i965_dump_error_state(pScrn);
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else
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i830_dump_error_state(pScrn);
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ErrorF("space: %d wanted %d\n", ring->space, n);
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pI830->uxa_driver = NULL;
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FatalError("lockup\n");
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784
src/i830_debug.c
784
src/i830_debug.c
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@ -1754,787 +1754,3 @@ void i830DumpRegs (ScrnInfoPtr pScrn)
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}
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xf86DrvMsg (pScrn->scrnIndex, X_INFO, "DumpRegsEnd\n");
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}
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#ifndef REG_DUMPER
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static char *mi_cmds[0x40] = {
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"MI_NOOP", /* 00 */
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"Reserved 01",
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"MI_USER_INTERRUPT",
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"MI_WAIT_FOR_EVENT",
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"MI_FLUSH", /* 04 */
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"MI_ARB_CHECK",
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NULL,
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"MI_REPORT_HEAD",
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NULL, /* 08 */
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NULL,
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"MI_BATCH_BUFFER_END",
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NULL,
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NULL, /* 0c */
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NULL,
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NULL,
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NULL,
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NULL, /* 10 */
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"MI_OVERLAY_FLIP",
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"MI_LOAD_SCAN_LINES_INCL",
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"MI_LOAD_SCAN_LINES_EXCL",
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"MI_DISPLAY_BUFFER_INFO", /* 14 */
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NULL,
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NULL,
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NULL,
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"MI_SET_CONTEXT", /* 18 */
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NULL,
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NULL,
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NULL,
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NULL, /* 1c */
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NULL,
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NULL,
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NULL,
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"MI_STORE_DATA_IMM", /* 20 */
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"MI_STORE_DATA_INDEX",
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"MI_LOAD_REGISTER_IMM",
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NULL,
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"MI_STORE_REGISTER_MEM", /* 24 */
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NULL,
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NULL,
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NULL,
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NULL, /* 28 */
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NULL,
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NULL,
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NULL,
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NULL, /* 2c */
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NULL,
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NULL,
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NULL,
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NULL, /* 30 */
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"MI_BATCH_BUFFER_START",
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NULL,
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NULL,
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NULL, /* 34 */
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NULL,
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NULL,
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NULL,
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NULL, /* 38 */
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NULL,
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NULL,
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NULL,
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NULL, /* 3c */
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NULL,
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NULL,
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NULL,
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};
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static char *_2d_cmds[0x80] = {
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NULL, /* 00 */
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"XY_SETUP_BLT",
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NULL,
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"XY_SETUP_CLIP_BLT",
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NULL, /* 04 */
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NULL,
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NULL,
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NULL,
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NULL, /* 08 */
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NULL,
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NULL,
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NULL,
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NULL, /* 0c */
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NULL,
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NULL,
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NULL,
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NULL, /* 10 */
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"XY_SETUP_MONO_PATTERN_SL_BLT",
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NULL,
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NULL,
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NULL, /* 14 */
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NULL,
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NULL,
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NULL,
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NULL, /* 18 */
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NULL,
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NULL,
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NULL,
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NULL, /* 1c */
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NULL,
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NULL,
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NULL,
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NULL, /* 20 */
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NULL,
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NULL,
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NULL,
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"XY_PIXEL_BLT", /* 24 */
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"XY_SCANLINE_BLT",
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"XY_TEXT_BLT",
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NULL,
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NULL, /* 28 */
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NULL,
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NULL,
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NULL,
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NULL, /* 2c */
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NULL,
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NULL,
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NULL,
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NULL, /* 30 */
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"XY_TEXT_IMMEDIATE_BLT",
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NULL,
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NULL,
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NULL, /* 34 */
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NULL,
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NULL,
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NULL,
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NULL, /* 38 */
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NULL,
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NULL,
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NULL,
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NULL, /* 3c */
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NULL,
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NULL,
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NULL,
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"COLOR_BLT", /* 40 */
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NULL,
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NULL,
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"SRC_COPY_BLT",
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NULL, /* 44 */
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NULL,
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NULL,
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NULL,
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NULL, /* 48 */
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NULL,
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NULL,
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NULL,
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NULL, /* 4c */
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NULL,
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NULL,
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NULL,
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"XY_COLOR_BLT", /* 50 */
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"XY_PAT_BLT",
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"XY_MONO_PAT_BLT",
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"XY_SRC_COPY_BLT",
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"XY_MONO_SRC_COPY_BLT", /* 54 */
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"XY_FULL_BLT",
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"XY_FULL_MONO_SRC_BLT",
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"XY_FULL_MONO_PATTERN_BLT",
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"XY_FULL_MONO_PATTERN_MONO_SRC_BLT", /* 58 */
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"XY_MONO_PAT_FIXED_BLT",
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NULL,
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NULL,
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NULL, /* 5c */
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NULL,
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NULL,
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NULL,
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NULL, /* 60 */
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NULL,
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NULL,
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NULL,
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NULL, /* 64 */
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NULL,
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NULL,
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NULL,
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NULL, /* 68 */
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NULL,
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NULL,
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NULL,
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NULL, /* 6c */
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NULL,
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NULL,
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NULL,
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NULL, /* 70 */
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"XY_MONO_SRC_COPY_IMMEDIATE_BLT",
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"XY_PAT_BLT_IMMEDIATE",
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"XY_SRC_COPY_CHROMA_BLT",
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"XY_FULL_IMMEDIATE_PATTERN_BLT", /* 74 */
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"XY_FULL_MONO_SRC_IMMEDIATE_PATTERN_BLT",
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"XY_PAT_CHROMA_BLT",
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"XY_PAT_CHROMA_BLT_IMMEDIATE",
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NULL, /* 78 */
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NULL,
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NULL,
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NULL,
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NULL, /* 7c */
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NULL,
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NULL,
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NULL,
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};
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#define _3D_ONE_WORD 1
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static struct {
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char *name;
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int flags;
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} _3d_cmds[0x4][0x8][0x100] = {
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{ /* Pipeline Type 00 (Common) */
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{ /* Opcode 0 */
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{ "URB_FENCE", 0 }, /* 00 */
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{ "CS_URB_STATE", 0 },
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{ "CONSTANT_BUFFER", 0 },
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{ "STATE_PREFETCH", 0 },
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},
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{ /* Opcode 1 */
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{ NULL, 0 }, /* 00 */
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{ "STATE_BASE_ADDRESS", 0 },
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{ "STATE_SIP", 0 },
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{ NULL, 0 },
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{ "PIPELINE_SELECT", _3D_ONE_WORD }, /* 04 */
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},
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},
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{ /* Pipeline Type 01 (Single DW) */
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{ /* Opcode 0 */
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},
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{ /* Opcode 1 */
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{ NULL, 0 }, /* 00 */
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{ NULL, 0 },
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{ NULL, 0 },
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{ NULL, 0 },
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{ "PIPELINE_SELECT", 0 }, /* 04 */
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{ NULL, 0 },
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{ NULL, 0 },
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{ NULL, 0 },
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},
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},
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{ /* Pipeline Type 02 (Media) */
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{ /* Opcode 0 */
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{ "MEDIA_STATE_POINTERS", 0 }, /* 00 */
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},
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{ /* Opcode 1 */
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{ "MEDIA_OBJECT", 0 }, /* 00 */
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{ "MEDIA_OBJECT_EX", 0 },
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{ "MEDIA_OBJECT_PTR", 0 },
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},
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},
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{ /* Pipeline Type 03 (3D) */
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{ /* Opcode 0 */
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{ "3DSTATE_PIPELINED_POINTERS", 0 }, /* 00 */
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{ "3DSTATE_BINDING_TABLE_POINTERS", 0 },
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{ NULL, 0 },
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{ NULL, 0 },
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{ NULL, 0 }, /* 04 */
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{ "3DSTATE_URB", 0 },
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{ NULL, 0 },
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{ NULL, 0 },
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{ "3DSTATE_VERTEX_BUFFERS", 0 }, /* 08 */
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{ "3DSTATE_VERTEX_ELEMENTS", 0 },
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{ "3DSTATE_INDEX_BUFFER", 0 },
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{ "3DSTATE_VF_STATISTICS", _3D_ONE_WORD },
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{ NULL, 0 }, /* 0c */
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{ "3DSTATE_VIEWPORT_STATE_POINTERS", 0 },
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},
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{ /* Opcode 1 */
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{ "3DSTATE_DRAWING_RECTANGLE", 0 }, /* 00 */
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{ "3DSTATE_CONSTANT_COLOR", 0 },
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{ "3DSTATE_SAMPLER_PALETTE_LOAD0", 0 },
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{ NULL, 0 },
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{ "3DSTATE_CHROMA_KEY", 0 }, /* 04 */
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{ "3DSTATE_DEPTH_BUFFER", 0 },
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{ "3DSTATE_POLY_STIPPLE_OFFSET", 0 },
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{ "3DSTATE_POLY_STIPPLE_PATTERN", 0 },
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{ "3DSTATE_LINE_STIPPLE", 0 }, /* 08 */
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{ "3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP", 0 },
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},
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{ /* Opcode 2 */
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{ "PIPE_CONTROL", 0 }, /* 00 */
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},
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{ /* Opcode 3 */
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{ "3DPRIMITIVE", 0 }, /* 00 */
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},
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},
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};
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static int
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i830_valid_command (uint32_t cmd)
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{
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uint32_t type = (cmd >> 29) & 0x7;
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uint32_t pipeline_type;
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uint32_t opcode;
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uint32_t subopcode;
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uint32_t count;
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switch (type) {
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case 0: /* Memory Interface */
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opcode = (cmd >> 23) & 0x3f;
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if (opcode < 0x10)
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count = 1;
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else
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count = (cmd & 0x3f) + 2;
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if (opcode == 0x00 && cmd != 0x00000000)
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return -1;
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if (!mi_cmds[opcode])
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return -1;
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break;
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case 1:
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return -1;
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case 2: /* 2D */
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count = (cmd & 0x1f) + 2;
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opcode = (cmd >> 22) & 0x7f;
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if (!_2d_cmds[opcode])
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return -1;
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break;
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case 3: /* 3D */
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pipeline_type = (cmd >> 27) & 0x3;
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opcode = (cmd >> 24) & 0x7;
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subopcode = (cmd >> 16) & 0xff;
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if (_3d_cmds[pipeline_type][opcode][subopcode].flags & _3D_ONE_WORD)
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count = 1;
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else
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count = (cmd & 0xff) + 2;
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if (!_3d_cmds[pipeline_type][opcode][subopcode].name)
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return -1;
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break;
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default:
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return -1;
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}
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return count;
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}
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static int
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i830_dump_cmd (uint32_t cmd, int count)
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{
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uint32_t type = (cmd >> 29) & 0x7;
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uint32_t pipeline_type;
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uint32_t opcode;
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uint32_t subopcode;
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int ret = 1;
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ErrorF ("\t");
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switch (type) {
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case 0: /* Memory Interface */
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opcode = (cmd >> 23) & 0x3f;
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if (mi_cmds[opcode])
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ErrorF ("%-40.40s %d\n", mi_cmds[opcode], count);
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else
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ErrorF ("Memory Interface Reserved\n");
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break;
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case 1:
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break;
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case 2: /* 2D */
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opcode = (cmd >> 22) & 0x7f;
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if (_2d_cmds[opcode])
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ErrorF ("%-40.40s %d\n", _2d_cmds[opcode], count);
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else
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ErrorF ("2D Reserved\n");
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break;
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case 3: /* 3D */
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pipeline_type = (cmd >> 27) & 0x3;
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opcode = (cmd >> 24) & 0x7;
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subopcode = (cmd >> 16) & 0xff;
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if (_3d_cmds[pipeline_type][opcode][subopcode].name) {
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ErrorF ("%-40.40s %d\n",
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_3d_cmds[pipeline_type][opcode][subopcode].name,
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count);
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} else {
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ErrorF ("3D/Media Reserved (pipe %d op %d sub %d)\n", pipeline_type, opcode, subopcode);
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}
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break;
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default:
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ErrorF ("Reserved\n");
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break;
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}
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return ret;
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}
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static int
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i830_valid_chain (ScrnInfoPtr pScrn, unsigned int ring, unsigned int end)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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unsigned int head, tail, mask;
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volatile unsigned char *virt;
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uint32_t data;
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int count;
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volatile uint32_t *ptr;
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head = (INREG (LP_RING + RING_HEAD)) & I830_HEAD_MASK;
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tail = INREG (LP_RING + RING_TAIL) & I830_TAIL_MASK;
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mask = pI830->ring.tail_mask;
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virt = pI830->ring.virtual_start;
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ErrorF ("Ring at virtual %p head 0x%x tail 0x%x count %d\n",
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virt, head, tail, (((tail + mask + 1) - head) & mask) >> 2);
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for (;;)
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{
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ptr = (volatile uint32_t *) (virt + ring);
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data = *ptr;
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count = i830_valid_command (data);
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if (count < 0)
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return 0;
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while (count > 0 && ring != end)
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{
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ring = (ring + 4) & mask;
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count--;
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}
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if (ring == end) {
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if (count == 0)
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return 1;
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else
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return 0;
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}
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}
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}
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static void
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i830_dump_cmds (ScrnInfoPtr pScrn,
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volatile unsigned char *virt,
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uint32_t start,
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uint32_t stop,
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uint32_t mask,
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uint32_t acthd)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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uint32_t ring = start;
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uint32_t cmd = start;
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uint32_t data;
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uint32_t batch_start_mask = ((0x7 << 29) |
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(0x3f << 23) |
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(0x7ff << 12) |
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(1 << 11) |
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(1 << 7) |
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(1 << 6) |
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(0x3f << 0));
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uint32_t batch_start_cmd = ((0x0 << 29) |
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(0x31 << 23) |
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(0x00 << 12) |
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(0 << 11) |
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(1 << 7) |
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(0 << 6) |
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(0 << 0));
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int count;
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volatile uint32_t *ptr;
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while (ring != stop)
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{
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if (ring == acthd)
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ErrorF ("****");
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ErrorF ("\t%08x: %08x", ring, *(volatile unsigned int *) (virt + ring));
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if (ring == cmd)
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{
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ptr = (volatile uint32_t *) (virt + ring);
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data = *ptr;
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count = i830_valid_command (data);
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i830_dump_cmd (data, count);
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/* check for MI_BATCH_BUFFER_END */
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if (data == (0x0a << 23))
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stop = (ring + 4) & mask;
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/* check for MI_BATCH_BUFFER_START */
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if ((data & batch_start_mask) == batch_start_cmd)
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{
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uint32_t batch = ptr[1] & ~3;
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if (batch < pI830->FbMapSize) {
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ErrorF ("\t%08x: %08x\n", (ring + 4) & mask, batch);
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ErrorF ("Batch buffer at 0x%08x {\n", batch);
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i830_dump_cmds (pScrn, pI830->FbBase, batch,
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batch + 256, 0xffffffff, acthd);
|
||||
ErrorF ("}\n");
|
||||
ring = (ring + (count - 1) * 4) & mask;
|
||||
}
|
||||
}
|
||||
cmd = (cmd + count * 4) & mask;
|
||||
} else
|
||||
ErrorF ("\n");
|
||||
ring = (ring + 4) & mask;
|
||||
}
|
||||
}
|
||||
|
||||
static void
|
||||
i830_dump_ring(ScrnInfoPtr pScrn, uint32_t acthd)
|
||||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
unsigned int head, tail, mask, cmd;
|
||||
volatile unsigned char *virt;
|
||||
|
||||
head = (INREG (LP_RING + RING_HEAD)) & I830_HEAD_MASK;
|
||||
tail = INREG (LP_RING + RING_TAIL) & I830_TAIL_MASK;
|
||||
mask = pI830->ring.tail_mask;
|
||||
|
||||
virt = pI830->ring.virtual_start;
|
||||
ErrorF ("Ring at virtual %p head 0x%x tail 0x%x count %d acthd 0x%x\n",
|
||||
virt, head, tail, (((tail + mask + 1) - head) & mask) >> 2, acthd);
|
||||
|
||||
/* walk back by instructions */
|
||||
for (cmd = (head - 256) & mask;
|
||||
cmd != (head & mask);
|
||||
cmd = (cmd + 4) & mask)
|
||||
{
|
||||
if (i830_valid_chain (pScrn, cmd, (head & mask)))
|
||||
break;
|
||||
}
|
||||
|
||||
i830_dump_cmds (pScrn, virt, cmd, head, mask, acthd);
|
||||
|
||||
ErrorF ("Ring end\n");
|
||||
}
|
||||
|
||||
/* Famous last words
|
||||
*/
|
||||
void
|
||||
i830_dump_error_state(ScrnInfoPtr pScrn)
|
||||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
|
||||
ErrorF("pgetbl_ctl: 0x%08x getbl_err: 0x%08x\n",
|
||||
INREG(PGETBL_CTL), INREG(PGE_ERR));
|
||||
|
||||
ErrorF("ipeir: 0x%08x iphdr: 0x%08x\n", INREG(IPEIR), INREG(IPEHR));
|
||||
|
||||
ErrorF("LP ring tail: 0x%08x head: 0x%08x len: 0x%08x start 0x%08x\n",
|
||||
INREG(LP_RING + RING_TAIL),
|
||||
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
|
||||
INREG(LP_RING + RING_LEN),
|
||||
INREG(LP_RING + RING_START));
|
||||
|
||||
ErrorF("eir: 0x%04x esr: 0x%04x emr: 0x%04x\n",
|
||||
INREG16(EIR), INREG16(ESR), INREG16(EMR));
|
||||
|
||||
ErrorF("instdone: 0x%04x instpm: 0x%04x\n",
|
||||
INREG16(INST_DONE), INREG8(INST_PM));
|
||||
|
||||
ErrorF("memmode: 0x%08x instps: 0x%08x\n",
|
||||
INREG(MEMMODE), INREG(INST_PS));
|
||||
|
||||
ErrorF("hwstam: 0x%04x ier: 0x%04x imr: 0x%04x iir: 0x%04x\n",
|
||||
INREG16(HWSTAM), INREG16(IER), INREG16(IMR), INREG16(IIR));
|
||||
i830_dump_ring (pScrn, INREG(ACTHD));
|
||||
}
|
||||
|
||||
void
|
||||
i965_dump_error_state(ScrnInfoPtr pScrn)
|
||||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
uint32_t acthd;
|
||||
|
||||
ErrorF("pgetbl_ctl: 0x%08x pgetbl_err: 0x%08x\n",
|
||||
INREG(PGETBL_CTL), INREG(PGE_ERR));
|
||||
|
||||
ErrorF("ipeir: 0x%08x iphdr: 0x%08x\n",
|
||||
INREG(IPEIR_I965), INREG(IPEHR_I965));
|
||||
|
||||
ErrorF("LP ring tail: 0x%08x head: %x len: 0x%08x start 0x%08x\n",
|
||||
INREG(LP_RING + RING_TAIL),
|
||||
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
|
||||
INREG(LP_RING + RING_LEN),
|
||||
INREG(LP_RING + RING_START));
|
||||
|
||||
ErrorF("Err ID (eir): 0x%08x\n"
|
||||
"Err Status (esr): 0x%08x\n"
|
||||
"Err Mask (emr): 0x%08x\n",
|
||||
INREG(EIR), INREG(ESR), INREG(EMR));
|
||||
|
||||
ErrorF("instdone: 0x%08x instdone_1: 0x%08x\n",
|
||||
INREG(INST_DONE_I965), INREG(INST_DONE_1));
|
||||
ErrorF("instpm: 0x%08x\n", INREG(INST_PM));
|
||||
|
||||
ErrorF("memmode: 0x%08x instps: 0x%08x\n",
|
||||
INREG(MEMMODE), INREG(INST_PS_I965));
|
||||
|
||||
ErrorF("HW Status mask (hwstam): 0x%08x\nIRQ enable (ier): 0x%08x "
|
||||
"imr: 0x%08x iir: 0x%08x\n",
|
||||
INREG(HWSTAM), INREG(IER), INREG(IMR), INREG(IIR));
|
||||
|
||||
acthd = INREG(ACTHD_I965);
|
||||
ErrorF("acthd: 0x%08x dma_fadd_p: 0x%08x\n",
|
||||
acthd, INREG(DMA_FADD_P));
|
||||
ErrorF("ecoskpd: 0x%08x excc: 0x%08x\n",
|
||||
INREG(ECOSKPD), INREG(EXCC));
|
||||
|
||||
ErrorF("cache_mode: 0x%08x/0x%08x\n", INREG(CACHE_MODE_0),
|
||||
INREG(CACHE_MODE_1));
|
||||
ErrorF("mi_arb_state: 0x%08x\n", INREG(MI_ARB_STATE));
|
||||
|
||||
ErrorF("IA_VERTICES_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(IA_VERTICES_COUNT_QW),
|
||||
INREG(IA_VERTICES_COUNT_QW+4));
|
||||
ErrorF("IA_PRIMITIVES_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(IA_PRIMITIVES_COUNT_QW),
|
||||
INREG(IA_PRIMITIVES_COUNT_QW+4));
|
||||
|
||||
ErrorF("VS_INVOCATION_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(VS_INVOCATION_COUNT_QW),
|
||||
INREG(VS_INVOCATION_COUNT_QW+4));
|
||||
|
||||
ErrorF("GS_INVOCATION_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(GS_INVOCATION_COUNT_QW),
|
||||
INREG(GS_INVOCATION_COUNT_QW+4));
|
||||
ErrorF("GS_PRIMITIVES_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(GS_PRIMITIVES_COUNT_QW),
|
||||
INREG(GS_PRIMITIVES_COUNT_QW+4));
|
||||
|
||||
ErrorF("CL_INVOCATION_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(CL_INVOCATION_COUNT_QW),
|
||||
INREG(CL_INVOCATION_COUNT_QW+4));
|
||||
ErrorF("CL_PRIMITIVES_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(CL_PRIMITIVES_COUNT_QW),
|
||||
INREG(CL_PRIMITIVES_COUNT_QW+4));
|
||||
|
||||
ErrorF("PS_INVOCATION_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(PS_INVOCATION_COUNT_QW),
|
||||
INREG(PS_INVOCATION_COUNT_QW+4));
|
||||
ErrorF("PS_DEPTH_COUNT_QW 0x%08x/0x%08x\n",
|
||||
INREG(PS_DEPTH_COUNT_QW),
|
||||
INREG(PS_DEPTH_COUNT_QW+4));
|
||||
|
||||
ErrorF("WIZ_CTL 0x%08x\n", INREG(WIZ_CTL));
|
||||
ErrorF("TS_CTL 0x%08x TS_DEBUG_DATA 0x%08x\n", INREG(TS_CTL),
|
||||
INREG(TS_DEBUG_DATA));
|
||||
ErrorF("TD_CTL 0x%08x / 0x%08x\n",
|
||||
INREG(TD_CTL), INREG(TD_CTL2));
|
||||
i830_dump_ring (pScrn, acthd);
|
||||
}
|
||||
|
||||
/**
|
||||
* Checks the hardware error state bits.
|
||||
*
|
||||
* \return TRUE if any errors were found.
|
||||
*/
|
||||
Bool
|
||||
i830_check_error_state(ScrnInfoPtr pScrn)
|
||||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
int errors = 0;
|
||||
unsigned long temp, head, tail;
|
||||
|
||||
temp = INREG16(ESR);
|
||||
if (temp != 0) {
|
||||
Bool vertex_max = !IS_I965G(pI830) && (temp & ERR_VERTEX_MAX);
|
||||
Bool pgtbl = temp & ERR_PGTBL_ERROR;
|
||||
Bool underrun = !IS_I965G(pI830) &&
|
||||
(temp & ERR_DISPLAY_OVERLAY_UNDERRUN);
|
||||
Bool instruction = !IS_I965G(pI830) && (temp & ERR_INSTRUCTION_ERROR);
|
||||
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"ESR is 0x%08lx%s%s%s%s\n", temp,
|
||||
vertex_max ? ", max vertices exceeded" : "",
|
||||
pgtbl ? ", page table error" : "",
|
||||
underrun ? ", display/overlay underrun" : "",
|
||||
instruction ? ", instruction error" : "");
|
||||
errors++;
|
||||
}
|
||||
/* Check first for page table errors */
|
||||
if (!IS_I9XX(pI830)) {
|
||||
temp = INREG(PGE_ERR);
|
||||
if (temp != 0) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"PGTBL_ER is 0x%08lx\n", temp);
|
||||
errors++;
|
||||
}
|
||||
} else {
|
||||
temp = INREG(PGTBL_ER);
|
||||
if (temp != 0) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"PGTBL_ER is 0x%08lx"
|
||||
"%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", temp,
|
||||
temp & PGTBL_ERR_HOST_GTT_PTE ? ", host gtt pte" : "",
|
||||
temp & PGTBL_ERR_HOST_PTE_DATA ? ", host pte data" : "",
|
||||
temp & PGTBL_ERR_DISPA_GTT_PTE ? ", display A pte" : "",
|
||||
temp & PGTBL_ERR_DISPA_TILING ?
|
||||
", display A tiling" : "",
|
||||
temp & PGTBL_ERR_DISPB_GTT_PTE ? ", display B pte" : "",
|
||||
temp & PGTBL_ERR_DISPB_TILING ?
|
||||
", display B tiling" : "",
|
||||
temp & PGTBL_ERR_DISPC_GTT_PTE ? ", display C pte" : "",
|
||||
temp & PGTBL_ERR_DISPC_TILING ?
|
||||
", display C tiling" : "",
|
||||
temp & PGTBL_ERR_OVERLAY_GTT_PTE ?
|
||||
", overlay GTT PTE" : "",
|
||||
temp & PGTBL_ERR_OVERLAY_TILING ?
|
||||
", overlay tiling" : "",
|
||||
temp & PGTBL_ERR_CS_GTT ? ", CS GTT" : "",
|
||||
temp & PGTBL_ERR_CS_INSTRUCTION_GTT_PTE ?
|
||||
", CS instruction GTT PTE" : "",
|
||||
temp & PGTBL_ERR_CS_VERTEXDATA_GTT_PTE ?
|
||||
", CS vertex data GTT PTE" : "",
|
||||
temp & PGTBL_ERR_BIN_INSTRUCTION_GTT_PTE ?
|
||||
", BIN instruction GTT PTE" : "",
|
||||
temp & PGTBL_ERR_BIN_VERTEXDATA_GTT_PTE ?
|
||||
", BIN vertex data GTT PTE" : "",
|
||||
temp & PGTBL_ERR_LC_GTT_PTE ? ", LC pte" : "",
|
||||
temp & PGTBL_ERR_LC_TILING ? ", LC tiling" : "",
|
||||
temp & PGTBL_ERR_MT_GTT_PTE ? ", MT pte" : "",
|
||||
temp & PGTBL_ERR_MT_TILING ? ", MT tiling" : "");
|
||||
errors++;
|
||||
}
|
||||
}
|
||||
temp = INREG(PGETBL_CTL);
|
||||
if (!(temp & 1)) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"PGTBL_CTL (0x%08lx) indicates GTT is disabled\n", temp);
|
||||
errors++;
|
||||
}
|
||||
temp = INREG(LP_RING + RING_LEN);
|
||||
if (!pI830->have_gem && (temp & 1)) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"PRB0_CTL (0x%08lx) indicates ring buffer enabled\n", temp);
|
||||
errors++;
|
||||
}
|
||||
head = INREG(LP_RING + RING_HEAD);
|
||||
tail = INREG(LP_RING + RING_TAIL);
|
||||
if ((tail & I830_TAIL_MASK) != (head & I830_HEAD_MASK)) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"PRB0_HEAD (0x%08lx) and PRB0_TAIL (0x%08lx) indicate "
|
||||
"ring buffer not flushed\n", head, tail);
|
||||
errors++;
|
||||
}
|
||||
|
||||
#if 0
|
||||
if (errors) {
|
||||
if (IS_I965G(pI830))
|
||||
i965_dump_error_state(pScrn);
|
||||
else
|
||||
i830_dump_error_state(pScrn);
|
||||
}
|
||||
#endif
|
||||
|
||||
return (errors != 0);
|
||||
}
|
||||
#endif /* !REG_DUMPER */
|
||||
|
|
|
|||
|
|
@ -28,7 +28,4 @@
|
|||
void i830TakeRegSnapshot(ScrnInfoPtr pScrn);
|
||||
void i830CompareRegsToSnapshot(ScrnInfoPtr pScrn, char *where);
|
||||
void i830DumpRegs (ScrnInfoPtr pScrn);
|
||||
void i830_dump_error_state(ScrnInfoPtr pScrn);
|
||||
void i965_dump_error_state(ScrnInfoPtr pScrn);
|
||||
Bool i830_check_error_state(ScrnInfoPtr pScrn);
|
||||
|
||||
|
|
|
|||
|
|
@ -2992,11 +2992,6 @@ I830EnterVT(int scrnIndex, int flags)
|
|||
gen4_render_state_init(pScrn);
|
||||
|
||||
if (!pI830->use_drm_mode) {
|
||||
if (i830_check_error_state(pScrn)) {
|
||||
xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
|
||||
"Existing errors found in hardware state.\n");
|
||||
}
|
||||
|
||||
/* Re-set up the ring. */
|
||||
if (!pI830->have_gem) {
|
||||
i830_stop_ring(pScrn, FALSE);
|
||||
|
|
|
|||
|
|
@ -1242,7 +1242,7 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
|
|||
drm_intel_bo_unreference(bind_bo);
|
||||
|
||||
#if WATCH_STATS
|
||||
i830_dump_error_state(pScrn);
|
||||
/* i830_dump_error_state(pScrn); */
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue