i830_driver.c changes for libpciaccess.
Change to use libpciaccess APIs, including computing and using BAR indices for various mapping activities.
This commit is contained in:
Keith Packard
parent
387fed6daa
commit
3411eb0dba
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@ -201,6 +201,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
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#include "dri.h"
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#include <sys/ioctl.h>
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#include <errno.h>
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#ifdef XF86DRI_MM
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#include "xf86mm.h"
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#endif
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#endif
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#ifdef I830_USE_EXA
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@ -418,16 +421,23 @@ static int
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I830DetectMemory(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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#if !XSERVER_LIBPCIACCESS
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PCITAG bridge;
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CARD16 gmch_ctrl;
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#endif
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uint16_t gmch_ctrl;
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int memsize = 0, gtt_size;
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int range;
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#if 0
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VbeInfoBlock *vbeInfo;
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#endif
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#if XSERVER_LIBPCIACCESS
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struct pci_device *bridge = intel_host_bridge ();
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pci_device_cfg_read_u16(bridge, & gmch_ctrl, I830_GMCH_CTRL);
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#else
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bridge = pciTag(0, 0, 0); /* This is always the host bridge */
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gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
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#endif
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if (IS_I965G(pI830)) {
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/* The 965 may have a GTT that is actually larger than is necessary
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@ -543,9 +553,52 @@ I830DetectMemory(ScrnInfoPtr pScrn)
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static Bool
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I830MapMMIO(ScrnInfoPtr pScrn)
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{
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#if XSERVER_LIBPCIACCESS
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int err;
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struct pci_device *device;
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#else
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int mmioFlags;
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#endif
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I830Ptr pI830 = I830PTR(pScrn);
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#if XSERVER_LIBPCIACCESS
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pI830->GTTBase = NULL;
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device = pI830->PciInfo;
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err = pci_device_map_region (device, pI830->mmio_bar, TRUE);
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if (err)
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{
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xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
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"Unable to map mmio BAR. %s (%d)\n",
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strerror (err), err);
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return FALSE;
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}
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pI830->MMIOBase = device->regions[pI830->mmio_bar].memory;
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pI830->gtt_bar = -1;
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/* XXX GTT aperture base needs figuring out */
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if (IS_I9XX(pI830))
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{
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if (IS_I965G(pI830))
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{
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pI830->GTTBase = (unsigned char *) pI830->MMIOBase + (512 * 1024);
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}
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else
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{
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pI830->gtt_bar = 3;
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err = pci_device_map_region (device, pI830->gtt_bar, TRUE);
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if (err)
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{
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xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
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"Unable to map GTT BAR. %s (%d)\n",
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strerror (err), err);
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pI830->GTTBase = NULL;
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}
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else
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pI830->GTTBase = device->regions[pI830->gtt_bar].memory;
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}
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}
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#else
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#if !defined(__alpha__)
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mmioFlags = VIDMEM_MMIO | VIDMEM_READSIDEEFFECT;
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#else
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@ -585,6 +638,7 @@ I830MapMMIO(ScrnInfoPtr pScrn)
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*/
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pI830->GTTBase = NULL;
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}
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#endif /* else HAVE_PCI_ACCESS */
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return TRUE;
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}
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@ -594,6 +648,10 @@ I830MapMem(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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long i;
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#if XSERVER_LIBPCIACCESS
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struct pci_device *const device = pI830->PciInfo;
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int err;
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#endif
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for (i = 2; i < pI830->FbMapSize; i <<= 1) ;
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pI830->FbMapSize = i;
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@ -601,11 +659,24 @@ I830MapMem(ScrnInfoPtr pScrn)
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if (!I830MapMMIO(pScrn))
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return FALSE;
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#if XSERVER_LIBPCIACCESS
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err = pci_device_map_region (device, pI830->fb_bar, TRUE);
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if (err)
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{
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xf86DrvMsg (pScrn->scrnIndex, X_ERROR,
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"Unable to map frame buffer BAR. %s (%d)\n",
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strerror (err), err);
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return FALSE;
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}
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pI830->FbBase = device->regions[pI830->fb_bar].memory;
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pI830->FbMapSize = device->regions[pI830->fb_bar].size;
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#else
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pI830->FbBase = xf86MapPciMem(pScrn->scrnIndex, VIDMEM_FRAMEBUFFER,
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pI830->PciTag,
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pI830->LinearAddr, pI830->FbMapSize);
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if (!pI830->FbBase)
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return FALSE;
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#endif
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if (I830IsPrimary(pScrn) && pI830->LpRing->mem != NULL) {
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pI830->LpRing->virtual_start =
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@ -620,16 +691,31 @@ I830UnmapMMIO(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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#if XSERVER_LIBPCIACCESS
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pci_device_unmap_region (pI830->PciInfo, pI830->mmio_bar);
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#else
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xf86UnMapVidMem(pScrn->scrnIndex, (pointer) pI830->MMIOBase,
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I810_REG_SIZE);
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#endif
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pI830->MMIOBase = NULL;
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if (IS_I9XX(pI830)) {
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if (IS_I965G(pI830))
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{
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#if XSERVER_LIBPCIACCESS
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;
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#else
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xf86UnMapVidMem(pScrn->scrnIndex, pI830->GTTBase, 512 * 1024);
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else {
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#endif
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}
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else
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{
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#if XSERVER_LIBPCIACCESS
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pci_device_unmap_region (pI830->PciInfo, pI830->gtt_bar);
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#else
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xf86UnMapVidMem(pScrn->scrnIndex, pI830->GTTBase,
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pI830->FbMapSize / 1024);
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#endif
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}
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}
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}
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@ -927,6 +1013,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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const char *chipname;
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int num_pipe;
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int max_width, max_height;
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uint32_t capid;
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if (pScrn->numEntities != 1)
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return FALSE;
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@ -971,8 +1058,10 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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return FALSE;
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pI830->PciInfo = xf86GetPciInfoForEntity(pI830->pEnt->index);
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#if !XSERVER_LIBPCIACCESS
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pI830->PciTag = pciTag(pI830->PciInfo->bus, pI830->PciInfo->device,
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pI830->PciInfo->func);
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#endif
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/* Allocate an entity private if necessary */
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if (xf86IsEntityShared(pScrn->entityList[0])) {
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@ -1061,7 +1150,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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/* We have to use PIO to probe, because we haven't mapped yet. */
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I830SetPIOAccess(pI830);
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switch (pI830->PciInfo->chipType) {
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switch (DEVICE_ID(pI830->PciInfo)) {
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case PCI_CHIP_I830_M:
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chipname = "830M";
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break;
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@ -1070,8 +1159,12 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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break;
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case PCI_CHIP_I855_GM:
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/* Check capid register to find the chipset variant */
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pI830->variant = (pciReadLong(pI830->PciTag, I85X_CAPID)
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>> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
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#if XSERVER_LIBPCIACCESS
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pci_device_cfg_read_u32 (pI830->PciInfo, &capid, I85X_CAPID);
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#else
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capid = pciReadLong (pI830->PciTag, I85X_CAPID);
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#endif
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pI830->variant = (capid >> I85X_VARIANT_SHIFT) & I85X_VARIANT_MASK;
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switch (pI830->variant) {
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case I855_GM:
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chipname = "855GM";
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@ -1155,11 +1248,11 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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from = X_CONFIG;
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xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
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pI830->pEnt->device->chipID);
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pI830->PciInfo->chipType = pI830->pEnt->device->chipID;
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DEVICE_ID(pI830->PciInfo) = pI830->pEnt->device->chipID;
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} else {
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from = X_PROBED;
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pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
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pI830->PciInfo->chipType);
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DEVICE_ID(pI830->PciInfo));
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}
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if (pI830->pEnt->device->chipRev >= 0) {
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@ -1170,6 +1263,13 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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xf86DrvMsg(pScrn->scrnIndex, from, "Chipset: \"%s\"\n",
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(pScrn->chipset != NULL) ? pScrn->chipset : "Unknown i8xx");
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#if XSERVER_LIBPCIACCESS
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if (IS_I9XX(pI830))
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pI830->fb_bar = 2;
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else
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pI830->fb_bar = 0;
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pI830->LinearAddr = pI830->PciInfo->regions[pI830->fb_bar].base_addr;
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#else
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if (pI830->pEnt->device->MemBase != 0) {
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pI830->LinearAddr = pI830->pEnt->device->MemBase;
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from = X_CONFIG;
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@ -1188,10 +1288,18 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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return FALSE;
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}
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}
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#endif
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xf86DrvMsg(pScrn->scrnIndex, from, "Linear framebuffer at 0x%lX\n",
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(unsigned long)pI830->LinearAddr);
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#if XSERVER_LIBPCIACCESS
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if (IS_I9XX(pI830))
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pI830->mmio_bar = 0;
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else
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pI830->mmio_bar = 1;
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pI830->MMIOAddr = pI830->PciInfo->regions[pI830->mmio_bar].base_addr;
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#else
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if (pI830->pEnt->device->IOBase != 0) {
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pI830->MMIOAddr = pI830->pEnt->device->IOBase;
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from = X_CONFIG;
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@ -1209,6 +1317,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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return FALSE;
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}
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}
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#endif
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xf86DrvMsg(pScrn->scrnIndex, from, "IO registers at addr 0x%lX\n",
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(unsigned long)pI830->MMIOAddr);
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@ -1232,11 +1341,19 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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xf86CrtcSetSizeRange (pScrn, 320, 200, max_width, max_height);
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if (IS_I830(pI830) || IS_845G(pI830)) {
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#if XSERVER_LIBPCIACCESS
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uint16_t gmch_ctrl;
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struct pci_device *bridge;
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bridge = intel_host_bridge ();
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pci_device_cfg_read_u16 (bridge, &gmch_ctrl, I830_GMCH_CTRL);
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#else
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PCITAG bridge;
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CARD16 gmch_ctrl;
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bridge = pciTag(0, 0, 0); /* This is always the host bridge */
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gmch_ctrl = pciReadWord(bridge, I830_GMCH_CTRL);
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#endif
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if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_128M) {
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pI830->FbMapSize = 0x8000000;
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} else {
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@ -1244,8 +1361,12 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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}
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} else {
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if (IS_I9XX(pI830)) {
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#if XSERVER_LIBPCIACCESS
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pI830->FbMapSize = pI830->PciInfo->regions[pI830->fb_bar].size;
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#else
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pI830->FbMapSize = 1UL << pciGetBaseSize(pI830->PciTag, 2, TRUE,
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NULL);
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#endif
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} else {
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/* 128MB aperture for later i8xx series. */
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pI830->FbMapSize = 0x8000000;
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@ -1275,7 +1396,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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(1 << 23) | (2 << 16));
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#endif
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if (pI830->PciInfo->chipType == PCI_CHIP_E7221_G)
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if (DEVICE_ID(pI830->PciInfo) == PCI_CHIP_E7221_G)
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num_pipe = 1;
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else
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if (IS_MOBILE(pI830) || IS_I9XX(pI830))
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