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Merge branch 'modesetting' of git://proxy01.pd.intel.com:9419/git/xorg/driver/xf86-video-intel into crestline

This commit is contained in:
Nian Wu 2007-01-25 13:37:05 -08:00
parent 566e1d3977 effe579e69
commit 3cc583ec8e
18 changed files with 354 additions and 170 deletions
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7
man/i810.man
View File

@ -84,9 +84,12 @@ This allows the user to change the amount of graphics memory used for
2D acceleration and video. Decreasing this amount leaves more for 3D
textures. Increasing it can improve 2D performance at the expense of
3D performance.
.TP
This option only takes effect when XAA acceleration is enabled.
.TP
Default: depends on the resolution, depth, and available video memory. The
driver attempts to allocate at least enough to hold two DVD-sized YUV buffers
by default. The default used for a specific configuration can be found
driver attempts to allocate space for at 3 screenfuls of pixmaps plus an
HD-sized XV video. The default used for a specific configuration can be found
by examining the __xservername__ log file.
.TP
.BI "Option \*qDRI\*q \*q" boolean \*q

8
src/ch7xxx/ch7xxx.c
View File

@ -182,7 +182,13 @@ out:
static xf86OutputStatus
ch7xxx_detect(I2CDevPtr d)
{
return XF86OutputStatusUnknown;
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
CARD8 cdet;
ch7xxx_read(dev_priv, CH7xxx_CONNECTION_DETECT, &cdet);
if (cdet & CH7xxx_CDET_DVI)
return XF86OutputStatusConnected;
return XF86OutputStatusDisconnected;
}
static ModeStatus

4
src/ch7xxx/ch7xxx_reg.h
View File

@ -49,7 +49,9 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#define CH7xxx_IDF_HSP (1<<3)
#define CH7xxx_IDF_VSP (1<<4)
#define CH7301_CONNECTION_DETECT 0x20
#define CH7xxx_CONNECTION_DETECT 0x20
#define CH7xxx_CDET_DVI (1<<5)
#define CH7301_DAC_CNTL 0x21
#define CH7301_HOTPLUG 0x23
#define CH7xxx_TCTL 0x31

4
src/common.h
View File

@ -345,10 +345,6 @@ extern int I810_DEBUG;
#define I810_CURSOR_X 64
#define I810_CURSOR_Y I810_CURSOR_X
/* XXX Need to check if these are reasonable. */
#define MAX_DISPLAY_PITCH 2048
#define MAX_DISPLAY_HEIGHT 2048
#define PIPE_NAME(n) ('A' + (n))
#endif /* _INTEL_COMMON_H_ */

13
src/i810_reg.h
View File

@ -937,8 +937,21 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define BLC_PWM_CTL 0x61254
#define BACKLIGHT_MODULATION_FREQ_SHIFT (17)
/**
* This is the most significant 15 bits of the number of backlight cycles in a
* complete cycle of the modulated backlight control.
*
* The actual value is this field multiplied by two.
*/
#define BACKLIGHT_MODULATION_FREQ_MASK (0x7fff << 17)
#define BLM_LEGACY_MODE (1 << 16)
/**
* This is the number of cycles out of the backlight modulation cycle for which
* the backlight is on.
*
* This field must be no greater than the number of cycles in the complete
* backlight modulation cycle.
*/
#define BACKLIGHT_DUTY_CYCLE_SHIFT (0)
#define BACKLIGHT_DUTY_CYCLE_MASK (0xffff)

74
src/i830_driver.c
View File

@ -318,7 +318,6 @@ const char *i830_output_type_names[] = {
static void i830AdjustFrame(int scrnIndex, int x, int y, int flags);
static Bool I830CloseScreen(int scrnIndex, ScreenPtr pScreen);
static Bool I830SaveScreen(ScreenPtr pScreen, int unblack);
static Bool I830EnterVT(int scrnIndex, int flags);
static CARD32 I830CheckDevicesTimer(OsTimerPtr timer, CARD32 now, pointer arg);
static Bool SaveHWState(ScrnInfoPtr pScrn);
@ -1144,14 +1143,13 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
/* Allocate an xf86CrtcConfig */
xf86CrtcConfigInit (pScrn);
xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
if (IS_I965G(pI830))
{
max_width = 16384;
max_height = 4096;
}
else
{
/* See i830_exa.c comments for why we limit the framebuffer size like this.
*/
if (IS_I965G(pI830)) {
max_width = 8192;
max_height = 8192;
} else {
max_width = 2048;
max_height = 2048;
}
@ -2897,7 +2895,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "direct rendering: Not available\n");
#endif
pScreen->SaveScreen = I830SaveScreen;
pScreen->SaveScreen = xf86SaveScreen;
pI830->CloseScreen = pScreen->CloseScreen;
pScreen->CloseScreen = I830CloseScreen;
@ -3021,10 +3019,7 @@ i830AdjustFrame(int scrnIndex, int x, int y, int flags)
if (crtc && crtc->enabled)
{
/* Sync the engine before adjust frame */
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
i830PipeSetBase(crtc, output->initial_x + x, output->initial_y + y);
}
}
@ -3271,57 +3266,6 @@ I830SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
return ret;
}
static Bool
I830SaveScreen(ScreenPtr pScreen, int mode)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
Bool on = xf86IsUnblank(mode);
CARD32 temp, ctrl, base, surf;
int i;
DPRINTF(PFX, "I830SaveScreen: %d, on is %s\n", mode, BOOLTOSTRING(on));
if (pScrn->vtSema) {
for (i = 0; i < xf86_config->num_crtc; i++) {
if (i == 0) {
ctrl = DSPACNTR;
base = DSPABASE;
surf = DSPASURF;
} else {
ctrl = DSPBCNTR;
base = DSPBADDR;
surf = DSPBSURF;
}
if (xf86_config->crtc[i]->enabled) {
temp = INREG(ctrl);
if (on)
temp |= DISPLAY_PLANE_ENABLE;
else
temp &= ~DISPLAY_PLANE_ENABLE;
OUTREG(ctrl, temp);
/* Flush changes */
temp = INREG(base);
OUTREG(base, temp);
if (IS_I965G(pI830)) {
temp = INREG(surf);
OUTREG(surf, temp);
}
}
}
if (pI830->CursorInfoRec && !pI830->SWCursor && pI830->cursorOn) {
if (on)
pI830->CursorInfoRec->ShowCursor(pScrn);
else
pI830->CursorInfoRec->HideCursor(pScrn);
pI830->cursorOn = TRUE;
}
}
return TRUE;
}
static Bool
I830CloseScreen(int scrnIndex, ScreenPtr pScreen)
{

22
src/i830_edid_modes.c
View File

@ -52,6 +52,8 @@ typedef enum {
DDC_QUIRK_DT_SYNC_HM_VP = 1 << 0,
/* First detailed mode is bogus, prefer largest mode at 60hz */
DDC_QUIRK_PREFER_LARGE_60 = 1 << 1,
/* 135MHz clock is too high, drop a bit */
DDC_QUIRK_135_CLOCK_TOO_HIGH = 1 << 2
} ddc_quirk_t;
static Bool quirk_dt_sync_hm_vp (int scrnIndex, xf86MonPtr DDC)
@ -78,6 +80,16 @@ static Bool quirk_prefer_large_60 (int scrnIndex, xf86MonPtr DDC)
return FALSE;
}
static Bool quirk_135_clock_too_high (int scrnIndex, xf86MonPtr DDC)
{
/* Envision Peripherals, Inc. EN-7100e. See bug #9550. */
if (memcmp (DDC->vendor.name, "EPI", 4) == 0 &&
DDC->vendor.prod_id == 59264)
return TRUE;
return FALSE;
}
typedef struct {
Bool (*detect) (int scrnIndex, xf86MonPtr DDC);
ddc_quirk_t quirk;
@ -93,6 +105,10 @@ static const ddc_quirk_map_t ddc_quirks[] = {
quirk_prefer_large_60, DDC_QUIRK_PREFER_LARGE_60,
"Detailed timing is not preferred, use largest mode at 60Hz"
},
{
quirk_135_clock_too_high, DDC_QUIRK_135_CLOCK_TOO_HIGH,
"Recommended 135MHz pixel clock is too high"
},
{
NULL, DDC_QUIRK_NONE,
"No known quirks"
@ -197,7 +213,11 @@ DDCModeFromDetailedTiming(int scrnIndex, struct detailed_timings *timing,
if (preferred)
Mode->type |= M_T_PREFERRED;
Mode->Clock = timing->clock / 1000.0;
if( ( quirks & DDC_QUIRK_135_CLOCK_TOO_HIGH ) &&
timing->clock == 135000000 )
Mode->Clock = 108880;
else
Mode->Clock = timing->clock / 1000.0;
Mode->HDisplay = timing->h_active;
Mode->HSyncStart = timing->h_active + timing->h_sync_off;

69
src/i830_exa.c
View File

@ -345,9 +345,9 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
int vertex_count;
if (pMask)
vertex_count = 4*6;
vertex_count = 3*6;
else
vertex_count = 4*4;
vertex_count = 3*4;
BEGIN_LP_RING(6+vertex_count);
@ -357,7 +357,7 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(PRIM3D_INLINE | PRIM3D_TRIFAN | (vertex_count-1));
OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST | (vertex_count-1));
OUT_RING_F(dstX);
OUT_RING_F(dstY);
@ -385,15 +385,6 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING_F(maskXend / pI830->scale_units[1][0]);
OUT_RING_F(maskYend / pI830->scale_units[1][1]);
}
OUT_RING_F(dstX + w);
OUT_RING_F(dstY);
OUT_RING_F(srcXend / pI830->scale_units[0][0]);
OUT_RING_F(srcY / pI830->scale_units[0][1]);
if (pMask) {
OUT_RING_F(maskXend / pI830->scale_units[1][0]);
OUT_RING_F(maskY / pI830->scale_units[1][1]);
}
ADVANCE_LP_RING();
}
}
@ -447,13 +438,53 @@ I830EXAInit(ScreenPtr pScreen)
/* disable Xv here... */
}
/* i915 3D requires 16 byte alignment (4k if tiled) */
pI830->EXADriverPtr->pixmapOffsetAlign = 256;
pI830->EXADriverPtr->pixmapPitchAlign = 64;
/* i845 and i945 2D limits rendering to 65536 lines and pitch of 32768. */
pI830->EXADriverPtr->maxX = 4095;
pI830->EXADriverPtr->maxY = 4095;
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 512B, only if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so EXA doesn't need to worry.
*/
if (IS_I965G(pI830)) {
pI830->EXADriverPtr->pixmapOffsetAlign = 4 * 2;
pI830->EXADriverPtr->pixmapPitchAlign = 1;
pI830->EXADriverPtr->maxX = 8192;
pI830->EXADriverPtr->maxY = 8192;
} else {
pI830->EXADriverPtr->pixmapOffsetAlign = 4;
pI830->EXADriverPtr->pixmapPitchAlign = 16;
pI830->EXADriverPtr->maxX = 2048;
pI830->EXADriverPtr->maxY = 2048;
}
/* Sync */
pI830->EXADriverPtr->WaitMarker = I830EXASync;

128
src/i830_lvds.c
View File

@ -32,6 +32,34 @@
#include "xf86.h"
#include "i830.h"
#include "i830_bios.h"
#include "X11/Xatom.h"
/**
* Sets the backlight level.
*
* \param level backlight level, from 0 to i830_lvds_get_max_backlight().
*/
static void
i830_lvds_set_backlight(ScrnInfoPtr pScrn, int level)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 blc_pwm_ctl;
blc_pwm_ctl = INREG(BLC_PWM_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
OUTREG(BLC_PWM_CTL, blc_pwm_ctl | (level << BACKLIGHT_DUTY_CYCLE_SHIFT));
}
/**
* Returns the maximum level of the backlight duty cycle field.
*/
static CARD32
i830_lvds_get_max_backlight(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
return ((INREG(BLC_PWM_CTL) & BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
}
/**
* Sets the power state for the panel.
@ -41,25 +69,16 @@ i830SetLVDSPanelPower(ScrnInfoPtr pScrn, Bool on)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 pp_status;
CARD32 blc_pwm_ctl;
int backlight_duty_cycle;
blc_pwm_ctl = INREG (BLC_PWM_CTL);
backlight_duty_cycle = blc_pwm_ctl & BACKLIGHT_DUTY_CYCLE_MASK;
if (backlight_duty_cycle)
pI830->backlight_duty_cycle = backlight_duty_cycle;
if (on) {
OUTREG(PP_CONTROL, INREG(PP_CONTROL) | POWER_TARGET_ON);
do {
pp_status = INREG(PP_STATUS);
} while ((pp_status & PP_ON) == 0);
OUTREG(BLC_PWM_CTL,
(blc_pwm_ctl & ~BACKLIGHT_DUTY_CYCLE_MASK) |
pI830->backlight_duty_cycle);
i830_lvds_set_backlight(pScrn, pI830->backlight_duty_cycle);
} else {
OUTREG(BLC_PWM_CTL,
(blc_pwm_ctl & ~BACKLIGHT_DUTY_CYCLE_MASK));
i830_lvds_set_backlight(pScrn, 0);
OUTREG(PP_CONTROL, INREG(PP_CONTROL) & ~POWER_TARGET_ON);
do {
@ -99,11 +118,8 @@ i830_lvds_save (xf86OutputPtr output)
/*
* If the light is off at server startup, just make it full brightness
*/
if (pI830->backlight_duty_cycle == 0) {
pI830->backlight_duty_cycle =
(pI830->saveBLC_PWM_CTL & BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT;
}
if (pI830->backlight_duty_cycle == 0)
pI830->backlight_duty_cycle = i830_lvds_get_max_backlight(pScrn);
}
static void
@ -294,7 +310,82 @@ i830_lvds_destroy (xf86OutputPtr output)
xfree (intel_output);
}
#ifdef RANDR_12_INTERFACE
#define BACKLIGHT_NAME "BACKLIGHT"
static Atom backlight_atom;
#endif /* RANDR_12_INTERFACE */
static void
i830_lvds_create_resources(xf86OutputPtr output)
{
#ifdef RANDR_12_INTERFACE
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
INT32 range[2];
int data, err;
/* Set up the backlight property, which takes effect immediately
* and accepts values only within the range.
*
* XXX: Currently, RandR doesn't verify that properties set are
* within the range.
*/
backlight_atom = MakeAtom(BACKLIGHT_NAME, sizeof(BACKLIGHT_NAME) - 1,
TRUE);
range[0] = 0;
range[1] = i830_lvds_get_max_backlight(pScrn);
err = RRConfigureOutputProperty(output->randr_output, backlight_atom,
FALSE, TRUE, FALSE, 2, range);
if (err != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRConfigureOutputProperty error, %d\n", err);
}
/* Set the current value of the backlight property */
data = pI830->backlight_duty_cycle;
err = RRChangeOutputProperty(output->randr_output, backlight_atom,
XA_INTEGER, 32, PropModeReplace, 4, &data,
FALSE);
if (err != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
}
#endif /* RANDR_12_INTERFACE */
}
#ifdef RANDR_12_INTERFACE
static Bool
i830_lvds_set_property(xf86OutputPtr output, Atom property,
RRPropertyValuePtr value)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
if (property == backlight_atom) {
INT32 val;
if (value->type != XA_INTEGER || value->format != 32 ||
value->size != 1)
{
return FALSE;
}
val = *(INT32 *)value->data;
if (val < 0 || val > i830_lvds_get_max_backlight(pScrn))
return FALSE;
i830_lvds_set_backlight(pScrn, val);
pI830->backlight_duty_cycle = val;
return TRUE;
}
return TRUE;
}
#endif /* RANDR_12_INTERFACE */
static const xf86OutputFuncsRec i830_lvds_output_funcs = {
.create_resources = i830_lvds_create_resources,
.dpms = i830_lvds_dpms,
.save = i830_lvds_save,
.restore = i830_lvds_restore,
@ -303,6 +394,9 @@ static const xf86OutputFuncsRec i830_lvds_output_funcs = {
.mode_set = i830_lvds_mode_set,
.detect = i830_lvds_detect,
.get_modes = i830_lvds_get_modes,
#ifdef RANDR_12_INTERFACE
.set_property = i830_lvds_set_property,
#endif
.destroy = i830_lvds_destroy
};

35
src/i830_memory.c
View File

@ -637,6 +637,13 @@ GetFreeSpace(ScrnInfoPtr pScrn)
return extra;
}
/* This is the 2D rendering vertical coordinate limit. We can ignore
* the 3D rendering limits in our 2d pixmap cache allocation, because XAA
* doesn't do any 3D rendering to/from the cache lines when using an offset
* at the start of framebuffer.
*/
#define MAX_2D_HEIGHT 65536
/**
* Allocates a framebuffer for a screen.
*
@ -698,25 +705,19 @@ I830AllocateFramebuffer(ScrnInfoPtr pScrn, I830Ptr pI830, BoxPtr FbMemBox,
"maxCacheLines < 0 in I830Allocate2DMemory()\n");
maxCacheLines = 0;
}
if (maxCacheLines > (MAX_DISPLAY_HEIGHT - pScrn->virtualY))
maxCacheLines = MAX_DISPLAY_HEIGHT - pScrn->virtualY;
if (maxCacheLines > (MAX_2D_HEIGHT - pScrn->virtualY))
maxCacheLines = MAX_2D_HEIGHT - pScrn->virtualY;
if (pI830->CacheLines >= 0) {
cacheLines = pI830->CacheLines;
} else {
#if 1
/* Make sure there is enough for two DVD sized YUV buffers */
cacheLines = (pScrn->depth == 24) ? 256 : 384;
if (pScrn->displayWidth <= 1024)
cacheLines *= 2;
#else
/*
* Make sure there is enough for two DVD sized YUV buffers.
* Make that 1.5MB, which is around what was allocated with
* the old algorithm
*/
cacheLines = (MB(1) + KB(512)) / pI830->cpp / pScrn->displayWidth;
#endif
int size;
size = 3 * lineSize * pScrn->virtualY;
size += 1920 * 1088 * 2 * 2;
size = ROUND_TO_PAGE(size);
cacheLines = (size + lineSize - 1) / lineSize;
}
if (cacheLines > maxCacheLines)
cacheLines = maxCacheLines;
@ -902,8 +903,8 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
maxFb = pI830->FrontBuffer.Size + extra;
lineSize = pScrn->displayWidth * pI830->cpp;
maxFb = ROUND_DOWN_TO(maxFb, lineSize);
if (maxFb > lineSize * MAX_DISPLAY_HEIGHT)
maxFb = lineSize * MAX_DISPLAY_HEIGHT;
if (maxFb > lineSize * MAX_2D_HEIGHT)
maxFb = lineSize * MAX_2D_HEIGHT;
if (0/*maxFb > pI830->FrontBuffer.Size*/) {
unsigned long oldsize;
/*

27
src/i830_randr.c
View File

@ -627,14 +627,10 @@ xf86RandR12CrtcSet (ScreenPtr pScreen,
/* XXX need device-independent mode setting code through an API */
if (changed)
{
I830Ptr pI830 = I830PTR(pScrn);
crtc->enabled = mode != NULL;
/* Sync the engine before adjust mode */
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
if (mode)
{
@ -676,6 +672,23 @@ xf86RandR12CrtcSetGamma (ScreenPtr pScreen,
return TRUE;
}
static Bool
xf86RandR12OutputSetProperty (ScreenPtr pScreen,
RROutputPtr randr_output,
Atom property,
RRPropertyValuePtr value)
{
xf86OutputPtr output = randr_output->devPrivate;
/* If we don't have any property handler, then we don't care what the
* user is setting properties to.
*/
if (output->funcs->set_property == NULL)
return TRUE;
return output->funcs->set_property(output, property, value);
}
/**
* Given a list of xf86 modes and a RandR Output object, construct
* RandR modes and assign them to the output
@ -865,6 +878,9 @@ xf86RandR12CreateObjects12 (ScreenPtr pScreen)
strlen (output->name),
output);
RROutputAttachScreen (output->randr_output, pScreen);
if (output->funcs->create_resources != NULL)
output->funcs->create_resources(output);
}
return TRUE;
}
@ -901,6 +917,7 @@ xf86RandR12Init12 (ScreenPtr pScreen)
rp->rrScreenSetSize = xf86RandR12ScreenSetSize;
rp->rrCrtcSet = xf86RandR12CrtcSet;
rp->rrCrtcSetGamma = xf86RandR12CrtcSetGamma;
rp->rrOutputSetProperty = xf86RandR12OutputSetProperty;
rp->rrSetConfig = NULL;
pScrn->PointerMoved = xf86RandR12PointerMoved;
if (!xf86RandR12CreateObjects12 (pScreen))

11
src/i830_rotate.c
View File

@ -805,10 +805,7 @@ I965UpdateRotate (ScreenPtr pScreen,
/* Since we use the same little vertex buffer over and over, sync for
* subsequent rectangles.
*/
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
}
pbox++;
@ -895,12 +892,10 @@ I965UpdateRotate (ScreenPtr pScreen,
ADVANCE_LP_RING();
first_output = FALSE;
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
i830MarkSync(pScrn);
}
if (pI830->AccelInfoRec)
(*pI830->AccelInfoRec->Sync)(pScrn);
i830WaitSync(pScrn);
#ifdef XF86DRI
if (didLock)
I830DRIUnlock(pScrn1);

53
src/i830_video.c
View File

@ -128,6 +128,19 @@ I830FreeMemory(ScrnInfoPtr pScrn, struct linear_alloc *linear);
static Atom xvBrightness, xvContrast, xvSaturation, xvColorKey, xvPipe, xvDoubleBuffer;
static Atom xvGamma0, xvGamma1, xvGamma2, xvGamma3, xvGamma4, xvGamma5;
/* Limits for the overlay/textured video source sizes. The documented hardware
* limits are 2048x2048 or better for overlay and both of our textured video
* implementations. However, we run into the bigrequests limit of (currently)
* 4MB, which even the planar format's 2048*2048*1.5 bytes is larger than.
* Conveniently, the HD resolution, even in packed format, takes
* (1920*1088*2) bytes, which is just shy of 4MB. Additionally, on the 830
* and 845, larger sizes resulted in the card hanging, so we keep the limits
* lower there.
*
* While the HD resolution is actually 1920x1080, we increase our advertised
* size to 1088 because some software wants to send an image aligned to
* 16-pixel boundaries.
*/
#define IMAGE_MAX_WIDTH 1920
#define IMAGE_MAX_HEIGHT 1088
#define IMAGE_MAX_WIDTH_LEGACY 1024
@ -777,7 +790,6 @@ static XF86VideoAdaptorPtr
I830SetupImageVideoTextured(ScreenPtr pScreen)
{
XF86VideoAdaptorPtr adapt;
XF86VideoEncodingPtr encoding;
XF86AttributePtr attrs;
I830PortPrivPtr portPrivs;
DevUnion *devUnions;
@ -791,15 +803,13 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec));
portPrivs = xcalloc(nports, sizeof(I830PortPrivRec));
devUnions = xcalloc(nports, sizeof(DevUnion));
encoding = xcalloc(1, sizeof(XF86VideoEncodingRec));
attrs = xcalloc(nAttributes, sizeof(XF86AttributeRec));
if (adapt == NULL || portPrivs == NULL || devUnions == NULL ||
encoding == NULL || attrs == NULL)
attrs == NULL)
{
xfree(adapt);
xfree(portPrivs);
xfree(devUnions);
xfree(encoding);
xfree(attrs);
return NULL;
}
@ -808,13 +818,7 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Intel(R) Textured Video";
adapt->nEncodings = 1;
adapt->pEncodings = encoding;
adapt->pEncodings[0].id = 0;
adapt->pEncodings[0].name = "XV_IMAGE";
adapt->pEncodings[0].width = 2048;
adapt->pEncodings[0].height = 2048;
adapt->pEncodings[0].rate.numerator = 1;
adapt->pEncodings[0].rate.denominator = 1;
adapt->pEncodings = DummyEncoding;
adapt->nFormats = NUM_FORMATS;
adapt->pFormats = Formats;
adapt->nPorts = nports;
@ -2358,10 +2362,7 @@ I830PutImage(ScrnInfoPtr pScrn,
* acceleration to finish before writing the new video data into
* framebuffer.
*/
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
}
switch (id) {
@ -2449,18 +2450,16 @@ I830QueryImageAttributes(ScrnInfoPtr pScrn,
ErrorF("I830QueryImageAttributes: w is %d, h is %d\n", *w, *h);
#endif
if (!textured) {
if (IS_845G(pI830) || IS_I830(pI830)) {
if (*w > IMAGE_MAX_WIDTH_LEGACY)
*w = IMAGE_MAX_WIDTH_LEGACY;
if (*h > IMAGE_MAX_HEIGHT_LEGACY)
*h = IMAGE_MAX_HEIGHT_LEGACY;
} else {
if (*w > IMAGE_MAX_WIDTH)
*w = IMAGE_MAX_WIDTH;
if (*h > IMAGE_MAX_HEIGHT)
*h = IMAGE_MAX_HEIGHT;
}
if (IS_845G(pI830) || IS_I830(pI830)) {
if (*w > IMAGE_MAX_WIDTH_LEGACY)
*w = IMAGE_MAX_WIDTH_LEGACY;
if (*h > IMAGE_MAX_HEIGHT_LEGACY)
*h = IMAGE_MAX_HEIGHT_LEGACY;
} else {
if (*w > IMAGE_MAX_WIDTH)
*w = IMAGE_MAX_WIDTH;
if (*h > IMAGE_MAX_HEIGHT)
*h = IMAGE_MAX_HEIGHT;
}
*w = (*w + 1) & ~1;

22
src/i830_xf86Crtc.c
View File

@ -1237,6 +1237,9 @@ xf86DPMSSet(ScrnInfoPtr pScrn, int mode, int flags)
xf86CrtcConfigPtr config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
if (!pScrn->vtSema)
return;
if (mode == DPMSModeOff) {
for (i = 0; i < config->num_output; i++) {
xf86OutputPtr output = config->output[i];
@ -1260,6 +1263,25 @@ xf86DPMSSet(ScrnInfoPtr pScrn, int mode, int flags)
}
}
/**
* Implement the screensaver by just calling down into the driver DPMS hooks.
*
* Even for monitors with no DPMS support, by the definition of our DPMS hooks,
* the outputs will still get disabled (blanked).
*/
Bool
xf86SaveScreen(ScreenPtr pScreen, int mode)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
if (xf86IsUnblank(mode))
xf86DPMSSet(pScrn, DPMSModeOn, 0);
else
xf86DPMSSet(pScrn, DPMSModeOff, 0);
return TRUE;
}
#ifdef RANDR_12_INTERFACE
#define EDID_ATOM_NAME "EDID_DATA"

19
src/i830_xf86Crtc.h
View File

@ -170,6 +170,13 @@ struct _xf86Crtc {
};
typedef struct _xf86OutputFuncs {
/**
* Called to allow the output a chance to create properties after the
* RandR objects have been created.
*/
void
(*create_resources)(xf86OutputPtr output);
/**
* Turns the output on/off, or sets intermediate power levels if available.
*
@ -245,6 +252,15 @@ typedef struct _xf86OutputFuncs {
DisplayModePtr
(*get_modes)(xf86OutputPtr output);
#ifdef RANDR_12_INTERFACE
/**
* Callback when an output's property has changed.
*/
Bool
(*set_property)(xf86OutputPtr output,
Atom property,
RRPropertyValuePtr value);
#endif
/**
* Clean up driver-specific bits of the output
*/
@ -437,6 +453,9 @@ xf86InitialConfiguration (ScrnInfoPtr pScrn);
void
xf86DPMSSet(ScrnInfoPtr pScrn, int PowerManagementMode, int flags);
Bool
xf86SaveScreen(ScreenPtr pScreen, int mode);
/**
* Set the EDID information for the specified output
*/

3
src/i915_video.c
View File

@ -433,7 +433,6 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
ADVANCE_LP_RING();
}
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
i830MarkSync(pScrn);
}

23
src/i965_exa_render.c
View File

@ -369,6 +369,16 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
CARD32 mask_offset = 0, mask_pitch = 0;
CARD32 dst_format, dst_offset, dst_pitch;
#ifdef XF86DRI
if (pI830->directRenderingEnabled) {
drmI830Sarea *pSAREAPriv = DRIGetSAREAPrivate(pScrn->pScreen);
pSAREAPriv->ctxOwner = DRIGetContext(pScrn->pScreen);
}
#endif
pI830->last_3d = LAST_3D_RENDER;
src_offset = exaGetPixmapOffset(pSrc);
src_pitch = exaGetPixmapPitch(pSrc);
dst_offset = exaGetPixmapOffset(pDst);
@ -404,6 +414,9 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
binding_table_entries = 2; /* default no mask */
/* Wait for sync before we start setting up our new state */
i830WaitSync(pScrn);
/* Set up our layout of state in framebuffer. First the general state: */
next_offset = 0;
vs_offset = ALIGN(next_offset, 64);
@ -1024,6 +1037,11 @@ I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
"dstX %d, dstY %d\n", srcX, srcY, srcXend, srcYend,
maskX, maskY, maskXend, maskYend, dstX, dstY);
/* Wait for any existing composite rectangles to land before we overwrite
* the VB with the next one.
*/
i830WaitSync(pScrn);
i = 0;
/* rect (x2,y2) */
vb[i++] = (float)(srcXend) / pI830->scale_units[0][0];
@ -1088,4 +1106,9 @@ I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING(0); /* Immediate data high DW */
ADVANCE_LP_RING();
}
/* Mark sync so we can wait for it before setting up the VB on the next
* rectangle.
*/
i830MarkSync(pScrn);
}

2
src/ivch/ivch.c
View File

@ -92,7 +92,7 @@ ivch_init(I2CBusPtr b, I2CSlaveAddr addr)
xf86DrvMsg(b->scrnIndex, X_INFO, "detecting ivch\n");
priv = xcalloc(1, sizeof(struct ivch_priv));
if (priv = NULL)
if (priv == NULL)
return NULL;
priv->d.DevName = "i82807aa \"ivch\" LVDS/CMOS panel controller";