From 42a6b25817985e22e7d462be87fbd97973d96a29 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Sat, 9 Feb 2013 15:30:58 +0000 Subject: [PATCH] sna: Fix alignment of the base of partial buffers for pre-G33 chipsets The older chipsets have much more restrictive alignment rules for the base address of tiled but unfenced objects. Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1120108 Signed-off-by: Chris Wilson --- src/sna/sna_render.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/sna/sna_render.c b/src/sna/sna_render.c index 697b8025..69ac21c3 100644 --- a/src/sna/sna_render.c +++ b/src/sna/sna_render.c @@ -899,6 +899,9 @@ sna_render_pixmap_partial(struct sna *sna, DBG(("%s: tile size for tiling %d: %dx%d, size=%d\n", __FUNCTION__, bo->tiling, tile_width, tile_height, tile_size)); + if (sna->kgem.gen < 033) + tile_width = bo->pitch; + /* Ensure we align to an even tile row */ box.y1 = box.y1 & ~(2*tile_height - 1); box.y2 = ALIGN(box.y2, 2*tile_height);