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EXA: fix render issue with i965 

Fix SF kernel with corrent coeffient work, and correct
VUE storage in multi texture case.
This commit is contained in:
Wang Zhenyu 2007-02-07 17:30:51 +08:00
parent 785a59ead0
commit 44eacf2323
3 changed files with 32 additions and 35 deletions
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16
src/exa_sf_mask.g4a
View File

@ -22,25 +22,25 @@ mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
/* Cy[0] */
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
/* Cx[2] */
mul (1) g7.16<1>F g7.16<0,1,0>F g6<0,1,0>F { align1 };
mul (1) g7.8<1>F g7.8<0,1,0>F g6<0,1,0>F { align1 };
/* Cy[2] */
mul (1) g7.20<1>F g7.20<0,1,0>F g6.4<0,1,0>F { align1 };
mul (1) g7.12<1>F g7.12<0,1,0>F g6.4<0,1,0>F { align1 };
/* src Cx[0], Cx[1] */
mov (8) m1<1>F g7<0,1,0>F { align1 };
/* mask Cx[2], Cx[3] */
mov (1) m1.8<1>F g7.16<0,1,0>F { align1 };
mov (1) m1.12<1>F g7.16<0,1,0>F { align1 };
mov (1) m1.8<1>F g7.8<0,1,0>F { align1 };
mov (1) m1.12<1>F g7.8<0,1,0>F { align1 };
/* src Cy[0], Cy[1] */
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
/* mask Cy[2], Cy[3] */
mov (1) m2.8<1>F g7.20<0,1,0>F { align1 };
mov (1) m2.12<1>F g7.20<0,1,0>F { align1 };
mov (1) m2.8<1>F g7.12<0,1,0>F { align1 };
mov (1) m2.12<1>F g7.12<0,1,0>F { align1 };
/* src Co[0], Co[1] */
mov (8) m3<1>F g3<8,8,1>F { align1 };
/* mask Co[2], Co[3] */
mov (1) m3.8<1>F g3.16<0,1,0>F { align1 };
mov (1) m3.12<1>F g3.20<0,1,0>F { align1 };
mov (1) m3.8<1>F g3.8<0,1,0>F { align1 };
mov (1) m3.12<1>F g3.12<0,1,0>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;

16
src/exa_sf_mask_prog.h
View File

@ -3,17 +3,17 @@
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00000041, 0x20f077bd, 0x000000f0, 0x000000c0 },
{ 0x00000041, 0x20f477bd, 0x000000f4, 0x000000c4 },
{ 0x00000041, 0x20e877bd, 0x000000e8, 0x000000c0 },
{ 0x00000041, 0x20ec77bd, 0x000000ec, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00000001, 0x202803be, 0x000000f0, 0x00000000 },
{ 0x00000001, 0x202c03be, 0x000000f0, 0x00000000 },
{ 0x00000001, 0x202803be, 0x000000e8, 0x00000000 },
{ 0x00000001, 0x202c03be, 0x000000e8, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00000001, 0x204803be, 0x000000f4, 0x00000000 },
{ 0x00000001, 0x204c03be, 0x000000f4, 0x00000000 },
{ 0x00000001, 0x204803be, 0x000000ec, 0x00000000 },
{ 0x00000001, 0x204c03be, 0x000000ec, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00000001, 0x206803be, 0x00000070, 0x00000000 },
{ 0x00000001, 0x206c03be, 0x00000074, 0x00000000 },
{ 0x00000001, 0x206803be, 0x00000068, 0x00000000 },
{ 0x00000001, 0x206c03be, 0x0000006c, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

35
src/i965_render.c
View File

@ -948,44 +948,41 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
VB0_VERTEXDATA |
((4 * 2 * nelem) << VB0_BUFFER_PITCH_SHIFT));
OUT_RING(state_base_offset + vb_offset);
OUT_RING(2); // max index, prim has 4 coords
OUT_RING(3);
OUT_RING(0); // ignore for VERTEXDATA, but still there
/* Set up our vertex elements, sourced from the single vertex buffer.
*/
OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | ((2 * nelem) - 1));
/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(0 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
(0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(8 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
if (pMask) {
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(16 << VE0_OFFSET_SHIFT));
(8 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_NOSTORE << VE1_VFCOMPONENT_3_SHIFT) |
(2 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
}
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
((pMask?16:8) << VE0_OFFSET_SHIFT)); /* offset vb in bytes */
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT)); /* VUE offset in dwords */
ADVANCE_LP_RING();
}