Decode DSPCLK_GATE, dump PIPE*STAT, MI_MODE, MI_DISPLAY_POWER_DOWN, MI_ARB_STATE, MI_RDRET_STATE, ECOSKPD
This commit is contained in:
Keith Packard
parent
6633135598
commit
4a42b01f5e
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@ -377,7 +377,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define CACHE_MODE_0 0x2120
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#define CACHE_MODE_1 0x2124
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#define MI_MODE 0x209c
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#define MI_DISPLAY_POWER_DOWN 0x20e0
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#define MI_ARB_STATE 0x20e4
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#define MI_RDRET_STATE 0x20fc
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/* Start addresses for each of the primary rings:
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*/
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@ -988,6 +991,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define D_STATE 0x6104
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#define DSPCLK_GATE_D 0x6200
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# define DPUNIT_B_CLOCK_GATE_DISABLE (1 << 30) /* 965 */
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# define VSUNIT_CLOCK_GATE_DISABLE (1 << 29) /* 965 */
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# define VRHUNIT_CLOCK_GATE_DISABLE (1 << 28) /* 965 */
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# define VRDUNIT_CLOCK_GATE_DISABLE (1 << 27) /* 965 */
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# define AUDUNIT_CLOCK_GATE_DISABLE (1 << 26) /* 965 */
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# define DPUNIT_A_CLOCK_GATE_DISABLE (1 << 25) /* 965 */
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# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 24) /* 965 */
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# define TVRUNIT_CLOCK_GATE_DISABLE (1 << 23) /* 915-945 */
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# define TVCUNIT_CLOCK_GATE_DISABLE (1 << 22) /* 915-945 */
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# define TVFUNIT_CLOCK_GATE_DISABLE (1 << 21) /* 915-945 */
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@ -1002,7 +1012,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define DPLUNIT_CLOCK_GATE_DISABLE (1 << 12) /* 915-945 */
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# define DPOUNIT_CLOCK_GATE_DISABLE (1 << 11)
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# define DPBUNIT_CLOCK_GATE_DISABLE (1 << 10)
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# define DPCUNIT_CLOCK_GATE_DISABLE (1 << 9)
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# define DCUNIT_CLOCK_GATE_DISABLE (1 << 9)
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# define DPUNIT_CLOCK_GATE_DISABLE (1 << 8)
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# define VRUNIT_CLOCK_GATE_DISABLE (1 << 7) /* 915+: reserved */
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# define OVHUNIT_CLOCK_GATE_DISABLE (1 << 6) /* 830-865 */
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@ -2007,6 +2017,32 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define PIPEAGCMAXGREEN 0x70014
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#define PIPEAGCMAXBLUE 0x70018
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#define PIPEASTAT 0x70024
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# define FIFO_UNDERRUN (1 << 31)
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# define CRC_ERROR_ENABLE (1 << 29)
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# define CRC_DONE_ENABLE (1 << 28)
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# define GMBUS_EVENT_ENABLE (1 << 27)
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# define VSYNC_INT_ENABLE (1 << 25)
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# define DLINE_COMPARE_ENABLE (1 << 24)
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# define DPST_EVENT_ENABLE (1 << 23)
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# define LBLC_EVENT_ENABLE (1 << 22)
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# define OFIELD_INT_ENABLE (1 << 21)
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# define EFIELD_INT_ENABLE (1 << 20)
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# define SVBLANK_INT_ENABLE (1 << 18)
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# define VBLANK_INT_ENABLE (1 << 17)
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# define OREG_UPDATE_ENABLE (1 << 16)
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# define CRC_ERROR_INT_STATUS (1 << 13)
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# define CRC_DONE_INT_STATUS (1 << 12)
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# define GMBUS_INT_STATUS (1 << 11)
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# define VSYNC_INT_STATUS (1 << 9)
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# define DLINE_COMPARE_STATUS (1 << 8)
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# define DPST_EVENT_STATUS (1 << 7)
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# define LBLC_EVENT_STATUS (1 << 6)
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# define OFIELD_INT_STATUS (1 << 5)
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# define EFIELD_INT_STATUS (1 << 4)
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# define SVBLANK_INT_STATUS (1 << 2)
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# define VBLANK_INT_STATUS (1 << 1)
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# define OREG_UPDATE_STATUS (1 << 0)
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#define DSPARB 0x70030
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#define DSPFW1 0x70034
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134
src/i830_debug.c
134
src/i830_debug.c
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@ -88,6 +88,61 @@ DEBUGSTRING(i830_debug_pipeconf)
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return XNFprintf("%s, %s", enabled, bit30);
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}
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DEBUGSTRING(i830_debug_pipestat)
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{
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char *_FIFO_UNDERRUN = val & FIFO_UNDERRUN ? " FIFO_UNDERRUN" : "";
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char *_CRC_ERROR_ENABLE = val & CRC_ERROR_ENABLE ? " CRC_ERROR_ENABLE" : "";
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char *_CRC_DONE_ENABLE = val & CRC_DONE_ENABLE ? " CRC_DONE_ENABLE" : "";
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char *_GMBUS_EVENT_ENABLE = val & GMBUS_EVENT_ENABLE ? " GMBUS_EVENT_ENABLE" : "";
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char *_VSYNC_INT_ENABLE = val & VSYNC_INT_ENABLE ? " VSYNC_INT_ENABLE" : "";
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char *_DLINE_COMPARE_ENABLE = val & DLINE_COMPARE_ENABLE ? " DLINE_COMPARE_ENABLE" : "";
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char *_DPST_EVENT_ENABLE = val & DPST_EVENT_ENABLE ? " DPST_EVENT_ENABLE" : "";
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char *_LBLC_EVENT_ENABLE = val & LBLC_EVENT_ENABLE ? " LBLC_EVENT_ENABLE" : "";
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char *_OFIELD_INT_ENABLE = val & OFIELD_INT_ENABLE ? " OFIELD_INT_ENABLE" : "";
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char *_EFIELD_INT_ENABLE = val & EFIELD_INT_ENABLE ? " EFIELD_INT_ENABLE" : "";
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char *_SVBLANK_INT_ENABLE = val & SVBLANK_INT_ENABLE ? " SVBLANK_INT_ENABLE" : "";
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char *_VBLANK_INT_ENABLE = val & VBLANK_INT_ENABLE ? " VBLANK_INT_ENABLE" : "";
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char *_OREG_UPDATE_ENABLE = val & OREG_UPDATE_ENABLE ? " OREG_UPDATE_ENABLE" : "";
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char *_CRC_ERROR_INT_STATUS = val & CRC_ERROR_INT_STATUS ? " CRC_ERROR_INT_STATUS" : "";
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char *_CRC_DONE_INT_STATUS = val & CRC_DONE_INT_STATUS ? " CRC_DONE_INT_STATUS" : "";
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char *_GMBUS_INT_STATUS = val & GMBUS_INT_STATUS ? " GMBUS_INT_STATUS" : "";
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char *_VSYNC_INT_STATUS = val & VSYNC_INT_STATUS ? " VSYNC_INT_STATUS" : "";
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char *_DLINE_COMPARE_STATUS = val & DLINE_COMPARE_STATUS ? " DLINE_COMPARE_STATUS" : "";
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char *_DPST_EVENT_STATUS = val & DPST_EVENT_STATUS ? " DPST_EVENT_STATUS" : "";
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char *_LBLC_EVENT_STATUS = val & LBLC_EVENT_STATUS ? " LBLC_EVENT_STATUS" : "";
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char *_OFIELD_INT_STATUS = val & OFIELD_INT_STATUS ? " OFIELD_INT_STATUS" : "";
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char *_EFIELD_INT_STATUS = val & EFIELD_INT_STATUS ? " EFIELD_INT_STATUS" : "";
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char *_SVBLANK_INT_STATUS = val & SVBLANK_INT_STATUS ? " SVBLANK_INT_STATUS" : "";
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char *_VBLANK_INT_STATUS = val & VBLANK_INT_STATUS ? " VBLANK_INT_STATUS" : "";
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char *_OREG_UPDATE_STATUS = val & OREG_UPDATE_STATUS ? " OREG_UPDATE_STATUS" : "";
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return XNFprintf("status:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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_FIFO_UNDERRUN,
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_CRC_ERROR_ENABLE,
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_CRC_DONE_ENABLE,
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_GMBUS_EVENT_ENABLE,
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_VSYNC_INT_ENABLE,
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_DLINE_COMPARE_ENABLE,
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_DPST_EVENT_ENABLE,
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_LBLC_EVENT_ENABLE,
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_OFIELD_INT_ENABLE,
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_EFIELD_INT_ENABLE,
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_SVBLANK_INT_ENABLE,
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_VBLANK_INT_ENABLE,
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_OREG_UPDATE_ENABLE,
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_CRC_ERROR_INT_STATUS,
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_CRC_DONE_INT_STATUS,
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_GMBUS_INT_STATUS,
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_VSYNC_INT_STATUS,
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_DLINE_COMPARE_STATUS,
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_DPST_EVENT_STATUS,
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_LBLC_EVENT_STATUS,
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_OFIELD_INT_STATUS,
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_EFIELD_INT_STATUS,
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_SVBLANK_INT_STATUS,
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_VBLANK_INT_STATUS,
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_OREG_UPDATE_STATUS);
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}
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DEBUGSTRING(i830_debug_hvtotal)
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{
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return XNFprintf("%d active, %d total", (val & 0xffff) + 1,
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@ -340,6 +395,76 @@ DEBUGSTRING(i830_debug_sdvo)
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enable, pipe, stall, detected, sdvoextra, gang);
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}
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DEBUGSTRING(i830_debug_dspclk_gate_d)
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{
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char *DPUNIT_B = val & DPUNIT_B_CLOCK_GATE_DISABLE ? " DPUNIT_B" : "";
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char *VSUNIT = val & VSUNIT_CLOCK_GATE_DISABLE ? " VSUNIT" : "";
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char *VRHUNIT = val & VRHUNIT_CLOCK_GATE_DISABLE ? " VRHUNIT" : "";
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char *VRDUNIT = val & VRDUNIT_CLOCK_GATE_DISABLE ? " VRDUNIT" : "";
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char *AUDUNIT = val & AUDUNIT_CLOCK_GATE_DISABLE ? " AUDUNIT" : "";
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char *DPUNIT_A = val & DPUNIT_A_CLOCK_GATE_DISABLE ? " DPUNIT_A" : "";
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char *DPCUNIT = val & DPCUNIT_CLOCK_GATE_DISABLE ? " DPCUNIT" : "";
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char *TVRUNIT = val & TVRUNIT_CLOCK_GATE_DISABLE ? " TVRUNIT" : "";
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char *TVCUNIT = val & TVCUNIT_CLOCK_GATE_DISABLE ? " TVCUNIT" : "";
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char *TVFUNIT = val & TVFUNIT_CLOCK_GATE_DISABLE ? " TVFUNIT" : "";
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char *TVEUNIT = val & TVEUNIT_CLOCK_GATE_DISABLE ? " TVEUNIT" : "";
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char *DVSUNIT = val & DVSUNIT_CLOCK_GATE_DISABLE ? " DVSUNIT" : "";
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char *DSSUNIT = val & DSSUNIT_CLOCK_GATE_DISABLE ? " DSSUNIT" : "";
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char *DDBUNIT = val & DDBUNIT_CLOCK_GATE_DISABLE ? " DDBUNIT" : "";
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char *DPRUNIT = val & DPRUNIT_CLOCK_GATE_DISABLE ? " DPRUNIT" : "";
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char *DPFUNIT = val & DPFUNIT_CLOCK_GATE_DISABLE ? " DPFUNIT" : "";
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char *DPBMUNIT = val & DPBMUNIT_CLOCK_GATE_DISABLE ? " DPBMUNIT" : "";
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char *DPLSUNIT = val & DPLSUNIT_CLOCK_GATE_DISABLE ? " DPLSUNIT" : "";
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char *DPLUNIT = val & DPLUNIT_CLOCK_GATE_DISABLE ? " DPLUNIT" : "";
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char *DPOUNIT = val & DPOUNIT_CLOCK_GATE_DISABLE ? " DPOUNIT" : "";
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char *DPBUNIT = val & DPBUNIT_CLOCK_GATE_DISABLE ? " DPBUNIT" : "";
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char *DCUNIT = val & DCUNIT_CLOCK_GATE_DISABLE ? " DCUNIT" : "";
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char *DPUNIT = val & DPUNIT_CLOCK_GATE_DISABLE ? " DPUNIT" : "";
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char *VRUNIT = val & VRUNIT_CLOCK_GATE_DISABLE ? " VRUNIT" : "";
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char *OVHUNIT = val & OVHUNIT_CLOCK_GATE_DISABLE ? " OVHUNIT" : "";
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char *DPIOUNIT = val & DPIOUNIT_CLOCK_GATE_DISABLE ? " DPIOUNIT" : "";
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char *OVFUNIT = val & OVFUNIT_CLOCK_GATE_DISABLE ? " OVFUNIT" : "";
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char *OVBUNIT = val & OVBUNIT_CLOCK_GATE_DISABLE ? " OVBUNIT" : "";
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char *OVRUNIT = val & OVRUNIT_CLOCK_GATE_DISABLE ? " OVRUNIT" : "";
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char *OVCUNIT = val & OVCUNIT_CLOCK_GATE_DISABLE ? " OVCUNIT" : "";
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char *OVUUNIT = val & OVUUNIT_CLOCK_GATE_DISABLE ? " OVUUNIT" : "";
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char *OVLUNIT = val & OVLUNIT_CLOCK_GATE_DISABLE ? " OVLUNIT" : "";
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return XNFprintf ("clock gates disabled:%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
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DPUNIT_B,
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VSUNIT,
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VRHUNIT,
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VRDUNIT,
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AUDUNIT,
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DPUNIT_A,
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DPCUNIT,
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TVRUNIT,
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TVCUNIT,
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TVFUNIT,
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TVEUNIT,
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DVSUNIT,
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DSSUNIT,
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DDBUNIT,
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DPRUNIT,
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DPFUNIT,
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DPBMUNIT,
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DPLSUNIT,
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DPLUNIT,
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DPOUNIT,
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DPBUNIT,
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DCUNIT,
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DPUNIT,
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VRUNIT,
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OVHUNIT,
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DPIOUNIT,
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OVFUNIT,
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OVBUNIT,
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OVRUNIT,
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OVCUNIT,
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OVUUNIT,
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OVLUNIT);
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}
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#if 0
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DEBUGSTRING(i810_debug_fence_new)
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{
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@ -370,7 +495,7 @@ static struct i830SnapshotRec {
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DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
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DEFINEREG(CACHE_MODE_0),
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DEFINEREG(D_STATE),
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DEFINEREG(DSPCLK_GATE_D),
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DEFINEREG2(DSPCLK_GATE_D, i830_debug_dspclk_gate_d),
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DEFINEREG(RENCLK_GATE_D1),
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DEFINEREG(RENCLK_GATE_D2),
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/* DEFINEREG(RAMCLK_GATE_D), CRL only */
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@ -409,6 +534,7 @@ static struct i830SnapshotRec {
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DEFINEREG(DSPATILEOFF),
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DEFINEREG2(PIPEACONF, i830_debug_pipeconf),
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DEFINEREG2(PIPEASRC, i830_debug_yxminus1),
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DEFINEREG2(PIPEASTAT, i830_debug_pipestat),
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DEFINEREG(FBC_CFB_BASE),
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DEFINEREG(FBC_LL_BASE),
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@ -441,6 +567,7 @@ static struct i830SnapshotRec {
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DEFINEREG(DSPBTILEOFF),
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DEFINEREG2(PIPEBCONF, i830_debug_pipeconf),
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DEFINEREG2(PIPEBSRC, i830_debug_yxminus1),
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DEFINEREG2(PIPEBSTAT, i830_debug_pipestat),
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DEFINEREG2(FPB0, i830_debug_fp),
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DEFINEREG2(FPB1, i830_debug_fp),
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@ -495,6 +622,11 @@ static struct i830SnapshotRec {
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DEFINEREG(TV_H_CHROMA_0),
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DEFINEREG(TV_H_CHROMA_59),
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DEFINEREG(MI_MODE),
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DEFINEREG(MI_DISPLAY_POWER_DOWN),
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DEFINEREG(MI_ARB_STATE),
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DEFINEREG(MI_RDRET_STATE),
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DEFINEREG(ECOSKPD),
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#if 0
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DEFINEREG2(FENCE_NEW + 0, i810_debug_fence_new),
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DEFINEREG2(FENCE_NEW + 8, i810_debug_fence_new),
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