Write dpll_md register while updating dpll as that appears to be required.
SDVO multiplier on 965 is in the dpll_md register; for some reason, that needs to be written along with the dpll value or the multiplier doesn't get set correctly.
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9dd1520421
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@ -752,11 +752,9 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
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OUTREG(fp_reg, fp);
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OUTREG(dpll_reg, dpll);
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if (IS_I965G(pI830)) {
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/* Set the SDVO multiplier/divider to 1x for the sake of analog output.
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* It will be updated by the SDVO code if SDVO had fixed up the clock
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* for a higher multiplier.
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*/
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OUTREG(dpll_md_reg, 0);
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int sdvo_pixel_multiply = adjusted_mode->Clock / mode->Clock;
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OUTREG(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
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((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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}
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OUTREG(htot_reg, (adjusted_mode->CrtcHDisplay - 1) |
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@ -557,7 +557,6 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
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xf86CrtcPtr crtc = output->crtc;
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I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
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CARD32 sdvox;
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int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
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int sdvo_pixel_multiply;
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CARD16 width, height;
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CARD16 h_blank_len, h_sync_len, v_blank_len, v_sync_len;
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@ -663,8 +662,7 @@ i830_sdvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
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sdvo_pixel_multiply = i830_sdvo_get_pixel_multiplier(mode);
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if (IS_I965G(pI830)) {
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OUTREG(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
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((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
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/* done in crtc_mode_set as the dpll_md reg must be written early */
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} else if (IS_I945G(pI830) || IS_I945GM(pI830)) {
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/* done in crtc_mode_set as it lives inside the dpll register */
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} else {
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