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Force use of GTT and fence registers for mapping tiled objects 

If the buffer object is tiled, we need to use the fence registers to
perform the appropriate untiling for CPU access. Ensure that we always
take this path for tiled objects, regardless of their size.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-09-04 12:37:39 +01:00
parent b7a8087fbc
commit 501e78b009
1 changed files with 14 additions and 21 deletions
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35
src/intel_uxa.c
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@ -662,24 +662,16 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
(access == UXA_ACCESS_RW || priv->batch_write))
intel_batch_submit(scrn, FALSE);
if (bo->size > intel->max_gtt_map_size) {
ret = dri_bo_map(bo, access == UXA_ACCESS_RW);
if (ret != 0) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map failed: %s\n",
__FUNCTION__,
strerror(-ret));
return FALSE;
}
} else {
if (priv->tiling || bo->size <= intel->max_gtt_map_size)
ret = drm_intel_gem_bo_map_gtt(bo);
if (ret != 0) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: gtt bo map failed: %s\n",
__FUNCTION__,
strerror(-ret));
return FALSE;
}
else
ret = dri_bo_map(bo, access == UXA_ACCESS_RW);
if (ret) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map failed: %s\n",
__FUNCTION__,
strerror(-ret));
return FALSE;
}
pixmap->devPrivate.ptr = bo->virtual;
@ -690,18 +682,19 @@ static Bool intel_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
static void intel_uxa_finish_access(PixmapPtr pixmap)
{
dri_bo *bo = intel_get_pixmap_bo(pixmap);
ScreenPtr screen = pixmap->drawable.pScreen;
ScrnInfoPtr scrn = xf86Screens[screen->myNum];
intel_screen_private *intel = intel_get_screen_private(scrn);
struct intel_pixmap *priv = intel_get_pixmap_private(pixmap);
dri_bo *bo = priv->bo;
if (bo == intel->front_buffer)
intel->need_sync = TRUE;
if (bo->size > intel->max_gtt_map_size)
dri_bo_unmap(bo);
else
if (priv->tiling || bo->size <= intel->max_gtt_map_size)
drm_intel_gem_bo_unmap_gtt(bo);
else
dri_bo_unmap(bo);
pixmap->devPrivate.ptr = NULL;
}