sna/gen4: Revert changes to 965g[m]
The changes tested on g45/gm45 prove to be highly unstable on 965gm, suggesting a radical difference in the nature of the bugs between the two generations. In theory, g4x has additional features that could be exploited over and above gen4 which may prove interesting in the future. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
d560296561
commit
54d8968da5
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@ -72,6 +72,7 @@ libsna_la_SOURCES = \
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gen3_render.c \
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gen3_render.h \
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gen4_render.c \
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g4x_render.c \
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gen4_render.h \
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gen5_render.c \
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gen5_render.h \
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File diff suppressed because it is too large
Load Diff
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@ -65,8 +65,12 @@
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gen4_vertex_flush(sna); \
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OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); \
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} while (0)
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#define FLUSH(OP) do { \
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if ((OP)->mask.bo == NULL) _FLUSH(); \
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} while (0)
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#else
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#define _FLUSH()
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#define FLUSH(OP)
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#endif
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#define GEN4_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
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@ -97,15 +101,8 @@
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#define SF_KERNEL_NUM_GRF 16
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#define PS_KERNEL_NUM_GRF 32
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static const struct gt_info {
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uint32_t max_sf_threads;
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uint32_t max_wm_threads;
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uint32_t urb_size;
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} gen4_gt_info = {
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24, 32, 256,
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}, g4x_gt_info = {
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24, 50, 384,
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};
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#define GEN4_MAX_SF_THREADS 24
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#define GEN4_MAX_WM_THREADS 32
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static const uint32_t ps_kernel_packed_static[][4] = {
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#include "exa_wm_xy.g4b"
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@ -237,7 +234,7 @@ static void gen4_magic_ca_pass(struct sna *sna,
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gen4_emit_pipelined_pointers(sna, op, PictOpAdd,
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gen4_choose_composite_kernel(PictOpAdd,
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true, true, op->is_affine));
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OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
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OUT_BATCH(MI_FLUSH);
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OUT_BATCH(GEN4_3DPRIMITIVE |
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GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
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@ -702,23 +699,23 @@ gen4_emit_composite_primitive_solid(struct sna *sna,
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} dst;
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v = sna->render.vertices + sna->render.vertex_used;
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sna->render.vertex_used += 15;
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sna->render.vertex_used += 9;
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dst.p.x = r->dst.x + r->width;
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dst.p.y = r->dst.y + r->height;
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v[0] = dst.f;
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v[3] = v[1] = 1.;
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v[4] = v[2] = 1.;
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v[1] = 1.;
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v[2] = 1.;
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dst.p.x = r->dst.x;
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v[5] = dst.f;
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v[8] = v[6] = 0.;
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v[9] = v[7] = 1.;
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v[3] = dst.f;
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v[4] = 0.;
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v[5] = 1.;
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dst.p.y = r->dst.y;
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v[10] = dst.f;
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v[13] = v[11] = 0.;
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v[14] = v[12] = 0.;
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v[6] = dst.f;
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v[7] = 0.;
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v[8] = 0.;
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}
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fastcall static void
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@ -734,7 +731,7 @@ gen4_emit_composite_primitive_identity_source(struct sna *sna,
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} dst;
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v = sna->render.vertices + sna->render.vertex_used;
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sna->render.vertex_used += 15;
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sna->render.vertex_used += 9;
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sx = r->src.x + op->src.offset[0];
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sy = r->src.y + op->src.offset[1];
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@ -744,22 +741,16 @@ gen4_emit_composite_primitive_identity_source(struct sna *sna,
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v[0] = dst.f;
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v[1] = (sx + r->width) * sf[0];
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v[2] = (sy + r->height) * sf[1];
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v[3] = 1.;
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v[4] = 1.;
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dst.p.x = r->dst.x;
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v[5] = dst.f;
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v[6] = sx * sf[0];
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v[7] = v[2];
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v[8] = 0.;
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v[9] = 1.;
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v[3] = dst.f;
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v[4] = sx * sf[0];
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v[5] = v[2];
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dst.p.y = r->dst.y;
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v[10] = dst.f;
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v[11] = v[6];
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v[12] = sy * sf[1];
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v[13] = 0.;
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v[14] = 0.;
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v[6] = dst.f;
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v[7] = v[4];
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v[8] = sy * sf[1];
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}
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fastcall static void
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@ -774,7 +765,7 @@ gen4_emit_composite_primitive_affine_source(struct sna *sna,
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float *v;
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v = sna->render.vertices + sna->render.vertex_used;
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sna->render.vertex_used += 15;
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sna->render.vertex_used += 9;
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dst.p.x = r->dst.x + r->width;
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dst.p.y = r->dst.y + r->height;
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@ -785,30 +776,24 @@ gen4_emit_composite_primitive_affine_source(struct sna *sna,
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&v[1], &v[2]);
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v[1] *= op->src.scale[0];
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v[2] *= op->src.scale[1];
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v[3] = 1.;
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v[4] = 1.;
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dst.p.x = r->dst.x;
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v[5] = dst.f;
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v[3] = dst.f;
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_sna_get_transformed_coordinates(op->src.offset[0] + r->src.x,
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op->src.offset[1] + r->src.y + r->height,
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op->src.transform,
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&v[6], &v[7]);
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v[6] *= op->src.scale[0];
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v[7] *= op->src.scale[1];
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v[8] = 0.;
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v[9] = 1.;
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&v[4], &v[5]);
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v[4] *= op->src.scale[0];
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v[5] *= op->src.scale[1];
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dst.p.y = r->dst.y;
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v[10] = dst.f;
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v[6] = dst.f;
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_sna_get_transformed_coordinates(op->src.offset[0] + r->src.x,
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op->src.offset[1] + r->src.y,
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op->src.transform,
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&v[11], &v[12]);
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v[11] *= op->src.scale[0];
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v[12] *= op->src.scale[1];
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v[13] = 0.;
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v[14] = 0.;
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&v[7], &v[8]);
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v[7] *= op->src.scale[0];
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v[8] *= op->src.scale[1];
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}
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fastcall static void
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@ -867,7 +852,6 @@ gen4_emit_composite_primitive(struct sna *sna,
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bool is_affine = op->is_affine;
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const float *src_sf = op->src.scale;
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const float *mask_sf = op->mask.scale;
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bool has_mask = op->u.gen4.ve_id & 2;
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if (is_affine) {
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sna_get_transformed_coordinates(r->src.x + op->src.offset[0],
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@ -908,7 +892,7 @@ gen4_emit_composite_primitive(struct sna *sna,
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&src_w[2]);
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}
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if (has_mask) {
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if (op->mask.bo) {
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if (is_affine) {
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sna_get_transformed_coordinates(r->mask.x + op->mask.offset[0],
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r->mask.y + op->mask.offset[1],
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@ -954,7 +938,7 @@ gen4_emit_composite_primitive(struct sna *sna,
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OUT_VERTEX_F(src_y[2] * src_sf[1]);
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if (!is_affine)
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OUT_VERTEX_F(src_w[2]);
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if (has_mask) {
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if (op->mask.bo) {
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OUT_VERTEX_F(mask_x[2] * mask_sf[0]);
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OUT_VERTEX_F(mask_y[2] * mask_sf[1]);
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if (!is_affine)
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@ -966,7 +950,7 @@ gen4_emit_composite_primitive(struct sna *sna,
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OUT_VERTEX_F(src_y[1] * src_sf[1]);
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if (!is_affine)
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OUT_VERTEX_F(src_w[1]);
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if (has_mask) {
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if (op->mask.bo) {
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OUT_VERTEX_F(mask_x[1] * mask_sf[0]);
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OUT_VERTEX_F(mask_y[1] * mask_sf[1]);
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if (!is_affine)
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@ -978,7 +962,7 @@ gen4_emit_composite_primitive(struct sna *sna,
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OUT_VERTEX_F(src_y[0] * src_sf[1]);
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if (!is_affine)
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OUT_VERTEX_F(src_w[0]);
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if (has_mask) {
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if (op->mask.bo) {
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OUT_VERTEX_F(mask_x[0] * mask_sf[0]);
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OUT_VERTEX_F(mask_y[0] * mask_sf[1]);
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if (!is_affine)
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@ -1260,7 +1244,7 @@ gen4_emit_pipelined_pointers(struct sna *sna,
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uint16_t sp, bp;
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DBG(("%s: has_mask=%d, src=(%d, %d), mask=(%d, %d),kernel=%d, blend=%d, ca=%d, format=%x\n",
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__FUNCTION__, op->u.gen4.ve_id & 2,
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__FUNCTION__, op->mask.bo != NULL,
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op->src.filter, op->src.repeat,
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op->mask.filter, op->mask.repeat,
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kernel, blend, op->has_component_alpha, (int)op->dst.format));
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@ -1280,7 +1264,7 @@ gen4_emit_pipelined_pointers(struct sna *sna,
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OUT_BATCH(sna->render_state.gen4.vs);
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OUT_BATCH(GEN4_GS_DISABLE); /* passthrough */
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OUT_BATCH(GEN4_CLIP_DISABLE); /* passthrough */
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OUT_BATCH(sna->render_state.gen4.sf[!!(op->u.gen4.ve_id & 2)]);
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OUT_BATCH(sna->render_state.gen4.sf[op->mask.bo != NULL]);
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OUT_BATCH(sna->render_state.gen4.wm + sp);
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OUT_BATCH(sna->render_state.gen4.cc + bp);
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@ -1321,17 +1305,19 @@ gen4_emit_vertex_elements(struct sna *sna,
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* texture coordinate 1 if (has_mask is true): same as above
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*/
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struct gen4_render_state *render = &sna->render_state.gen4;
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int id = op->u.gen4.ve_id;
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int selem, nelem;
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bool has_mask = op->mask.bo != NULL;
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int nelem = has_mask ? 2 : 1;
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int selem;
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uint32_t w_component;
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uint32_t src_format;
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int id = op->u.gen4.ve_id;
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if (render->ve_id == id)
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return;
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render->ve_id = id;
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if (id & 1) {
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if (op->is_affine) {
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src_format = GEN4_SURFACEFORMAT_R32G32_FLOAT;
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w_component = GEN4_VFCOMPONENT_STORE_1_FLT;
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selem = 2;
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@ -1340,7 +1326,6 @@ gen4_emit_vertex_elements(struct sna *sna,
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w_component = GEN4_VFCOMPONENT_STORE_SRC;
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selem = 3;
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}
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nelem = id & 2 ? 2 : 1;
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/* The VUE layout
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* dword 0-3: position (x, y, 1.0, 1.0),
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@ -1370,7 +1355,7 @@ gen4_emit_vertex_elements(struct sna *sna,
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(2*4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); /* VUE offset in dwords */
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/* u1, v1, w1 */
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if (id & 2) {
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if (has_mask) {
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OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
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src_format << VE0_FORMAT_SHIFT |
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((1 + selem) * 4) << VE0_OFFSET_SHIFT); /* vb offset in bytes */
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@ -1387,14 +1372,14 @@ gen4_emit_state(struct sna *sna,
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const struct sna_composite_op *op,
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uint16_t wm_binding_table)
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{
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bool flush = wm_binding_table & 1;
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bool flush = false;
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gen4_emit_drawing_rectangle(sna, op);
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flush |= gen4_emit_binding_table(sna, wm_binding_table & ~1);
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flush |= gen4_emit_binding_table(sna, wm_binding_table);
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flush |= gen4_emit_pipelined_pointers(sna, op, op->op, op->u.gen4.wm_kernel);
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gen4_emit_vertex_elements(sna, op);
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if (kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
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if (flush || kgem_bo_is_dirty(op->src.bo) || kgem_bo_is_dirty(op->mask.bo)) {
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DBG(("%s: flushing dirty (%d, %d), forced? %d\n", __FUNCTION__,
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kgem_bo_is_dirty(op->src.bo),
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kgem_bo_is_dirty(op->mask.bo),
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@ -1402,17 +1387,13 @@ gen4_emit_state(struct sna *sna,
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OUT_BATCH(MI_FLUSH);
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kgem_clear_dirty(&sna->kgem);
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kgem_bo_mark_dirty(op->dst.bo);
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flush = false;
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}
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if (flush && op->op > PictOpSrc)
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OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
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}
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static void
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gen4_bind_surfaces(struct sna *sna,
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const struct sna_composite_op *op)
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{
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bool dirty = kgem_bo_is_dirty(op->dst.bo);
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uint32_t *binding_table;
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uint16_t offset;
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@ -1430,8 +1411,7 @@ gen4_bind_surfaces(struct sna *sna,
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op->src.bo, op->src.width, op->src.height,
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op->src.card_format,
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false);
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if (op->mask.bo) {
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assert(op->u.gen4.ve_id & 2);
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if (op->mask.bo)
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binding_table[2] =
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gen4_bind_bo(sna,
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op->mask.bo,
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@ -1439,7 +1419,6 @@ gen4_bind_surfaces(struct sna *sna,
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op->mask.height,
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op->mask.card_format,
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false);
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}
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if (sna->kgem.surface == offset &&
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*(uint64_t *)(sna->kgem.batch + sna->render_state.gen4.surface_table) == *(uint64_t*)binding_table &&
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@ -1449,7 +1428,7 @@ gen4_bind_surfaces(struct sna *sna,
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offset = sna->render_state.gen4.surface_table;
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}
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gen4_emit_state(sna, op, offset | dirty);
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gen4_emit_state(sna, op, offset);
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}
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fastcall static void
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@ -1466,6 +1445,9 @@ gen4_render_composite_blt(struct sna *sna,
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gen4_get_rectangles(sna, op, 1, gen4_bind_surfaces);
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op->prim_emit(sna, op, r);
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/* XXX are the shaders fubar? */
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FLUSH(op);
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}
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fastcall static void
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@ -1475,19 +1457,13 @@ gen4_render_composite_box(struct sna *sna,
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{
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struct sna_composite_rectangles r;
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DBG((" %s: (%d, %d), (%d, %d)\n",
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__FUNCTION__,
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box->x1, box->y1, box->x2, box->y2));
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gen4_get_rectangles(sna, op, 1, gen4_bind_surfaces);
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r.dst.x = box->x1;
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r.dst.y = box->y1;
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r.width = box->x2 - box->x1;
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r.height = box->y2 - box->y1;
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r.mask = r.src = r.dst;
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op->prim_emit(sna, op, &r);
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gen4_render_composite_blt(sna, op, &r);
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}
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static void
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@ -1503,28 +1479,16 @@ gen4_render_composite_boxes(struct sna *sna,
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op->mask.width, op->mask.height));
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do {
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int nbox_this_time;
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struct sna_composite_rectangles r;
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nbox_this_time = gen4_get_rectangles(sna, op, nbox,
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gen4_bind_surfaces);
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nbox -= nbox_this_time;
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do {
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struct sna_composite_rectangles r;
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DBG((" %s: (%d, %d), (%d, %d)\n",
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__FUNCTION__,
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box->x1, box->y1, box->x2, box->y2));
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r.dst.x = box->x1;
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r.dst.y = box->y1;
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r.width = box->x2 - box->x1;
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r.height = box->y2 - box->y1;
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r.mask = r.src = r.dst;
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op->prim_emit(sna, op, &r);
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box++;
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} while (--nbox_this_time);
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} while (nbox);
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r.dst.x = box->x1;
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r.dst.y = box->y1;
|
||||
r.width = box->x2 - box->x1;
|
||||
r.height = box->y2 - box->y1;
|
||||
r.mask = r.src = r.dst;
|
||||
gen4_render_composite_blt(sna, op, &r);
|
||||
box++;
|
||||
} while (--nbox);
|
||||
}
|
||||
|
||||
#ifndef MAX
|
||||
|
|
@ -1565,7 +1529,6 @@ static uint32_t gen4_bind_video_source(struct sna *sna,
|
|||
static void gen4_video_bind_surfaces(struct sna *sna,
|
||||
const struct sna_composite_op *op)
|
||||
{
|
||||
bool dirty = kgem_bo_is_dirty(op->dst.bo);
|
||||
struct sna_video_frame *frame = op->priv;
|
||||
uint32_t src_surf_format;
|
||||
uint32_t src_surf_base[6];
|
||||
|
|
@ -1627,7 +1590,7 @@ static void gen4_video_bind_surfaces(struct sna *sna,
|
|||
src_surf_format);
|
||||
}
|
||||
|
||||
gen4_emit_state(sna, op, offset | dirty);
|
||||
gen4_emit_state(sna, op, offset);
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -2332,7 +2295,6 @@ gen4_render_composite(struct sna *sna,
|
|||
dst_x, dst_y, width, height))
|
||||
return false;
|
||||
|
||||
tmp->op = op;
|
||||
switch (gen4_composite_picture(sna, src, &tmp->src,
|
||||
src_x, src_y,
|
||||
width, height,
|
||||
|
|
@ -2356,6 +2318,7 @@ gen4_render_composite(struct sna *sna,
|
|||
break;
|
||||
}
|
||||
|
||||
tmp->op = op;
|
||||
tmp->is_affine = tmp->src.is_affine;
|
||||
tmp->has_component_alpha = false;
|
||||
tmp->need_magic_ca_pass = false;
|
||||
|
|
@ -2409,6 +2372,7 @@ gen4_render_composite(struct sna *sna,
|
|||
if (tmp->src.transform == NULL && tmp->mask.transform == NULL)
|
||||
tmp->prim_emit = gen4_emit_composite_primitive_identity_source_mask;
|
||||
|
||||
tmp->floats_per_vertex = 5 + 2 * !tmp->is_affine;
|
||||
} else {
|
||||
if (tmp->src.is_solid)
|
||||
tmp->prim_emit = gen4_emit_composite_primitive_solid;
|
||||
|
|
@ -2416,16 +2380,17 @@ gen4_render_composite(struct sna *sna,
|
|||
tmp->prim_emit = gen4_emit_composite_primitive_identity_source;
|
||||
else if (tmp->src.is_affine)
|
||||
tmp->prim_emit = gen4_emit_composite_primitive_affine_source;
|
||||
|
||||
tmp->floats_per_vertex = 3 + !tmp->is_affine;
|
||||
}
|
||||
tmp->floats_per_vertex = 5 + 2 * !tmp->is_affine;
|
||||
tmp->floats_per_rect = 3*tmp->floats_per_vertex;
|
||||
|
||||
tmp->u.gen4.wm_kernel =
|
||||
gen4_choose_composite_kernel(tmp->op,
|
||||
mask != NULL,
|
||||
tmp->mask.bo != NULL,
|
||||
tmp->has_component_alpha,
|
||||
tmp->is_affine);
|
||||
tmp->u.gen4.ve_id = 1 << 1 | tmp->is_affine;
|
||||
tmp->u.gen4.ve_id = (tmp->mask.bo != NULL) << 1 | tmp->is_affine;
|
||||
|
||||
tmp->blt = gen4_render_composite_blt;
|
||||
tmp->box = gen4_render_composite_box;
|
||||
|
|
@ -2592,6 +2557,8 @@ gen4_render_composite_spans_box(struct sna *sna,
|
|||
|
||||
gen4_get_rectangles(sna, &op->base, 1, gen4_bind_surfaces);
|
||||
op->prim_emit(sna, op, box, opacity);
|
||||
|
||||
_FLUSH();
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -2619,6 +2586,7 @@ gen4_render_composite_spans_done(struct sna *sna,
|
|||
|
||||
DBG(("%s()\n", __FUNCTION__));
|
||||
|
||||
kgem_bo_destroy(&sna->kgem, op->base.mask.bo);
|
||||
if (op->base.src.bo)
|
||||
kgem_bo_destroy(&sna->kgem, op->base.src.bo);
|
||||
|
||||
|
|
@ -2712,7 +2680,9 @@ gen4_render_composite_spans(struct sna *sna,
|
|||
break;
|
||||
}
|
||||
|
||||
tmp->base.mask.bo = NULL;
|
||||
tmp->base.mask.bo = sna_render_get_solid(sna, 0);
|
||||
if (tmp->base.mask.bo == NULL)
|
||||
goto cleanup_src;
|
||||
|
||||
tmp->base.is_affine = tmp->base.src.is_affine;
|
||||
tmp->base.has_component_alpha = false;
|
||||
|
|
@ -2765,7 +2735,6 @@ cleanup_dst:
|
|||
static void
|
||||
gen4_copy_bind_surfaces(struct sna *sna, const struct sna_composite_op *op)
|
||||
{
|
||||
bool dirty = kgem_bo_is_dirty(op->dst.bo);
|
||||
uint32_t *binding_table;
|
||||
uint16_t offset;
|
||||
|
||||
|
|
@ -2790,7 +2759,7 @@ gen4_copy_bind_surfaces(struct sna *sna, const struct sna_composite_op *op)
|
|||
offset = sna->render_state.gen4.surface_table;
|
||||
}
|
||||
|
||||
gen4_emit_state(sna, op, offset | dirty);
|
||||
gen4_emit_state(sna, op, offset);
|
||||
}
|
||||
|
||||
static void
|
||||
|
|
@ -3091,30 +3060,57 @@ fallback:
|
|||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
gen4_fill_bind_surfaces(struct sna *sna, const struct sna_composite_op *op)
|
||||
{
|
||||
uint32_t *binding_table;
|
||||
uint16_t offset;
|
||||
|
||||
gen4_get_batch(sna);
|
||||
|
||||
binding_table = gen4_composite_get_binding_table(sna, &offset);
|
||||
|
||||
binding_table[0] =
|
||||
gen4_bind_bo(sna,
|
||||
op->dst.bo, op->dst.width, op->dst.height,
|
||||
gen4_get_dest_format(op->dst.format),
|
||||
true);
|
||||
binding_table[1] =
|
||||
gen4_bind_bo(sna,
|
||||
op->src.bo, 1, 1,
|
||||
GEN4_SURFACEFORMAT_B8G8R8A8_UNORM,
|
||||
false);
|
||||
|
||||
if (sna->kgem.surface == offset &&
|
||||
*(uint64_t *)(sna->kgem.batch + sna->render_state.gen4.surface_table) == *(uint64_t*)binding_table) {
|
||||
sna->kgem.surface +=
|
||||
sizeof(struct gen4_surface_state_padded)/sizeof(uint32_t);
|
||||
offset = sna->render_state.gen4.surface_table;
|
||||
}
|
||||
|
||||
gen4_emit_state(sna, op, offset);
|
||||
}
|
||||
|
||||
static void
|
||||
gen4_render_fill_rectangle(struct sna *sna,
|
||||
const struct sna_composite_op *op,
|
||||
int x, int y, int w, int h)
|
||||
{
|
||||
gen4_get_rectangles(sna, op, 1, gen4_bind_surfaces);
|
||||
gen4_get_rectangles(sna, op, 1, gen4_fill_bind_surfaces);
|
||||
|
||||
OUT_VERTEX(x+w, y+h);
|
||||
OUT_VERTEX_F(1);
|
||||
OUT_VERTEX_F(1);
|
||||
OUT_VERTEX_F(1);
|
||||
OUT_VERTEX_F(1);
|
||||
|
||||
OUT_VERTEX(x, y+h);
|
||||
OUT_VERTEX_F(0);
|
||||
OUT_VERTEX_F(1);
|
||||
OUT_VERTEX_F(0);
|
||||
OUT_VERTEX_F(1);
|
||||
|
||||
OUT_VERTEX(x, y);
|
||||
OUT_VERTEX_F(0);
|
||||
OUT_VERTEX_F(0);
|
||||
OUT_VERTEX_F(0);
|
||||
OUT_VERTEX_F(0);
|
||||
|
||||
_FLUSH();
|
||||
}
|
||||
|
||||
static bool
|
||||
|
|
@ -3188,20 +3184,22 @@ gen4_render_fill_boxes(struct sna *sna,
|
|||
tmp.dst.format = format;
|
||||
tmp.dst.bo = dst_bo;
|
||||
|
||||
gen4_composite_solid_init(sna, &tmp.src, pixel);
|
||||
tmp.src.bo = sna_render_get_solid(sna, pixel);
|
||||
tmp.src.filter = SAMPLER_FILTER_NEAREST;
|
||||
tmp.src.repeat = SAMPLER_EXTEND_REPEAT;
|
||||
|
||||
tmp.is_affine = true;
|
||||
tmp.floats_per_vertex = 5;
|
||||
tmp.floats_per_rect = 15;
|
||||
tmp.floats_per_vertex = 3;
|
||||
tmp.floats_per_rect = 9;
|
||||
tmp.u.gen4.wm_kernel = WM_KERNEL;
|
||||
tmp.u.gen4.ve_id = 1 | 1 << 1;
|
||||
tmp.u.gen4.ve_id = 1;
|
||||
|
||||
if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
|
||||
kgem_submit(&sna->kgem);
|
||||
assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
|
||||
}
|
||||
|
||||
gen4_bind_surfaces(sna, &tmp);
|
||||
gen4_fill_bind_surfaces(sna, &tmp);
|
||||
gen4_align_vertex(sna, &tmp);
|
||||
|
||||
do {
|
||||
|
|
@ -3290,23 +3288,29 @@ gen4_render_fill(struct sna *sna, uint8_t alu,
|
|||
op->base.need_magic_ca_pass = 0;
|
||||
op->base.has_component_alpha = 0;
|
||||
|
||||
gen4_composite_solid_init(sna, &op->base.src,
|
||||
sna_rgba_for_color(color,
|
||||
dst->drawable.depth));
|
||||
op->base.src.bo =
|
||||
sna_render_get_solid(sna,
|
||||
sna_rgba_for_color(color,
|
||||
dst->drawable.depth));
|
||||
op->base.src.filter = SAMPLER_FILTER_NEAREST;
|
||||
op->base.src.repeat = SAMPLER_EXTEND_REPEAT;
|
||||
|
||||
op->base.mask.bo = NULL;
|
||||
op->base.mask.filter = SAMPLER_FILTER_NEAREST;
|
||||
op->base.mask.repeat = SAMPLER_EXTEND_NONE;
|
||||
|
||||
op->base.is_affine = true;
|
||||
op->base.floats_per_vertex = 5;
|
||||
op->base.floats_per_rect = 15;
|
||||
op->base.floats_per_vertex = 3;
|
||||
op->base.floats_per_rect = 9;
|
||||
op->base.u.gen4.wm_kernel = WM_KERNEL;
|
||||
op->base.u.gen4.ve_id = 1 | 1 << 1;
|
||||
op->base.u.gen4.ve_id = 1;
|
||||
|
||||
if (!kgem_check_bo(&sna->kgem, dst_bo, NULL)) {
|
||||
kgem_submit(&sna->kgem);
|
||||
assert(kgem_check_bo(&sna->kgem, dst_bo, NULL));
|
||||
}
|
||||
|
||||
gen4_bind_surfaces(sna, &op->base);
|
||||
gen4_fill_bind_surfaces(sna, &op->base);
|
||||
gen4_align_vertex(sna, &op->base);
|
||||
|
||||
op->blt = gen4_render_fill_op_blt;
|
||||
|
|
@ -3366,26 +3370,32 @@ gen4_render_fill_one(struct sna *sna, PixmapPtr dst, struct kgem_bo *bo,
|
|||
tmp.dst.bo = bo;
|
||||
tmp.dst.x = tmp.dst.y = 0;
|
||||
|
||||
gen4_composite_solid_init(sna, &tmp.src,
|
||||
sna_rgba_for_color(color,
|
||||
dst->drawable.depth));
|
||||
tmp.src.bo =
|
||||
sna_render_get_solid(sna,
|
||||
sna_rgba_for_color(color,
|
||||
dst->drawable.depth));
|
||||
tmp.src.filter = SAMPLER_FILTER_NEAREST;
|
||||
tmp.src.repeat = SAMPLER_EXTEND_REPEAT;
|
||||
|
||||
tmp.mask.bo = NULL;
|
||||
tmp.mask.filter = SAMPLER_FILTER_NEAREST;
|
||||
tmp.mask.repeat = SAMPLER_EXTEND_NONE;
|
||||
|
||||
tmp.is_affine = true;
|
||||
tmp.floats_per_vertex = 5;
|
||||
tmp.floats_per_rect = 15;
|
||||
tmp.floats_per_vertex = 3;
|
||||
tmp.floats_per_rect = 9;
|
||||
tmp.has_component_alpha = 0;
|
||||
tmp.need_magic_ca_pass = false;
|
||||
|
||||
tmp.u.gen4.wm_kernel = WM_KERNEL;
|
||||
tmp.u.gen4.ve_id = 1 | 1 << 1;
|
||||
tmp.u.gen4.ve_id = 1;
|
||||
|
||||
if (!kgem_check_bo(&sna->kgem, bo, NULL)) {
|
||||
_kgem_submit(&sna->kgem);
|
||||
assert(kgem_check_bo(&sna->kgem, bo, NULL));
|
||||
}
|
||||
|
||||
gen4_bind_surfaces(sna, &tmp);
|
||||
gen4_fill_bind_surfaces(sna, &tmp);
|
||||
gen4_align_vertex(sna, &tmp);
|
||||
|
||||
gen4_render_fill_rectangle(sna, &tmp, x1, y1, x2 - x1, y2 - y1);
|
||||
|
|
@ -3477,7 +3487,6 @@ static uint32_t gen4_create_vs_unit_state(struct sna_static_stream *stream)
|
|||
}
|
||||
|
||||
static uint32_t gen4_create_sf_state(struct sna_static_stream *stream,
|
||||
const struct gt_info *info,
|
||||
uint32_t kernel)
|
||||
{
|
||||
struct gen4_sf_unit_state *sf;
|
||||
|
|
@ -3492,7 +3501,7 @@ static uint32_t gen4_create_sf_state(struct sna_static_stream *stream,
|
|||
/* don't smash vertex header, read start from dw8 */
|
||||
sf->thread3.urb_entry_read_offset = 1;
|
||||
sf->thread3.dispatch_grf_start_reg = 3;
|
||||
sf->thread4.max_threads = info->max_sf_threads - 1;
|
||||
sf->thread4.max_threads = GEN4_MAX_SF_THREADS - 1;
|
||||
sf->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
|
||||
sf->thread4.nr_urb_entries = URB_SF_ENTRIES;
|
||||
sf->sf5.viewport_transform = false; /* skip viewport */
|
||||
|
|
@ -3523,7 +3532,6 @@ static uint32_t gen4_create_sampler_state(struct sna_static_stream *stream,
|
|||
}
|
||||
|
||||
static void gen4_init_wm_state(struct gen4_wm_unit_state *wm,
|
||||
const struct gt_info *info,
|
||||
bool has_mask,
|
||||
uint32_t kernel,
|
||||
uint32_t sampler)
|
||||
|
|
@ -3544,7 +3552,7 @@ static void gen4_init_wm_state(struct gen4_wm_unit_state *wm,
|
|||
wm->wm4.sampler_state_pointer = sampler >> 5;
|
||||
wm->wm4.sampler_count = 1;
|
||||
|
||||
wm->wm5.max_threads = info->max_wm_threads - 1;
|
||||
wm->wm5.max_threads = GEN4_MAX_WM_THREADS - 1;
|
||||
wm->wm5.transposed_urb_read = 0;
|
||||
wm->wm5.thread_dispatch_enable = 1;
|
||||
/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
|
||||
|
|
@ -3620,15 +3628,9 @@ static bool gen4_render_setup(struct sna *sna)
|
|||
struct gen4_render_state *state = &sna->render_state.gen4;
|
||||
struct sna_static_stream general;
|
||||
struct gen4_wm_unit_state_padded *wm_state;
|
||||
const struct gt_info *info;
|
||||
uint32_t sf[2], wm[KERNEL_COUNT];
|
||||
int i, j, k, l, m;
|
||||
|
||||
if (sna->kgem.gen == 45)
|
||||
info = &g4x_gt_info;
|
||||
else
|
||||
info = &gen4_gt_info;
|
||||
|
||||
sna_static_stream_init(&general);
|
||||
|
||||
/* Zero pad the start. If you see an offset of 0x0 in the batchbuffer
|
||||
|
|
@ -3652,8 +3654,8 @@ static bool gen4_render_setup(struct sna *sna)
|
|||
}
|
||||
|
||||
state->vs = gen4_create_vs_unit_state(&general);
|
||||
state->sf[0] = gen4_create_sf_state(&general, info, sf[0]);
|
||||
state->sf[1] = gen4_create_sf_state(&general, info, sf[1]);
|
||||
state->sf[0] = gen4_create_sf_state(&general, sf[0]);
|
||||
state->sf[1] = gen4_create_sf_state(&general, sf[1]);
|
||||
|
||||
wm_state = sna_static_stream_map(&general,
|
||||
sizeof(*wm_state) * KERNEL_COUNT *
|
||||
|
|
@ -3673,7 +3675,7 @@ static bool gen4_render_setup(struct sna *sna)
|
|||
k, l);
|
||||
|
||||
for (m = 0; m < KERNEL_COUNT; m++) {
|
||||
gen4_init_wm_state(&wm_state->state, info,
|
||||
gen4_init_wm_state(&wm_state->state,
|
||||
wm_kernels[m].has_mask,
|
||||
wm[m], sampler_state);
|
||||
wm_state++;
|
||||
|
|
|
|||
|
|
@ -14277,9 +14277,12 @@ bool sna_accel_init(ScreenPtr screen, struct sna *sna)
|
|||
} else if (sna->info->gen >= 50) {
|
||||
if ((sna->have_render = gen5_render_init(sna)))
|
||||
backend = "Ironlake";
|
||||
} else if (sna->info->gen >= 45) {
|
||||
if ((sna->have_render = g4x_render_init(sna)))
|
||||
backend = "Eaglelake/Cantiga";
|
||||
} else if (sna->info->gen >= 40) {
|
||||
if ((sna->have_render = gen4_render_init(sna)))
|
||||
backend = "Broadwater";
|
||||
backend = "Broadwater/Crestline";
|
||||
} else if (sna->info->gen >= 30) {
|
||||
if ((sna->have_render = gen3_render_init(sna)))
|
||||
backend = "gen3";
|
||||
|
|
|
|||
|
|
@ -1091,7 +1091,7 @@ next_image:
|
|||
(int)this_atlas->format,
|
||||
(int)(format->depth << 24 | format->format)));
|
||||
if (this_atlas->format == (format->depth << 24 | format->format) &&
|
||||
!(sna->kgem.gen >= 40 && sna->kgem.gen < 50)) { /* XXX cache corruption? how? */
|
||||
sna->kgem.gen != 45) { /* XXX cache corruption? how? */
|
||||
ok = sna->render.composite(sna, PictOpAdd,
|
||||
this_atlas, NULL, mask,
|
||||
0, 0, 0, 0, 0, 0,
|
||||
|
|
|
|||
|
|
@ -524,6 +524,7 @@ void no_render_init(struct sna *sna);
|
|||
bool gen2_render_init(struct sna *sna);
|
||||
bool gen3_render_init(struct sna *sna);
|
||||
bool gen4_render_init(struct sna *sna);
|
||||
bool g4x_render_init(struct sna *sna);
|
||||
bool gen5_render_init(struct sna *sna);
|
||||
bool gen6_render_init(struct sna *sna);
|
||||
bool gen7_render_init(struct sna *sna);
|
||||
|
|
|
|||
Loading…
Reference in New Issue