Move 965 render unit state to BOs.
This is a first step in a series of changes to avoid requiring a pinned object, which gets in the way of doing non-root KMS. This change appears to result in about a 2-6% loss in x11perf -aa10text, which better algorithms in libdrm could make up for (it hasn't really had to deal with code this bad before).
This commit is contained in:
Eric Anholt
parent
64b08ed5ad
commit
5d705de5d1
15
src/i830.h
15
src/i830.h
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@ -1040,6 +1040,21 @@ intel_emit_reloc(drm_intel_bo *bo, uint32_t offset,
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return target_bo->offset + target_offset;
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}
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static inline drm_intel_bo *
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intel_bo_alloc_for_data(ScrnInfoPtr scrn, void *data, unsigned int size,
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char *name)
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{
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I830Ptr pI830 = I830PTR(scrn);
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drm_intel_bo *bo;
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bo = drm_intel_bo_alloc(pI830->bufmgr, name, size, 4096);
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if (!bo)
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return NULL;
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drm_intel_bo_subdata(bo, 0, size, data);
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return bo;
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}
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extern const int I830PatternROP[16];
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extern const int I830CopyROP[16];
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@ -423,6 +423,44 @@ typedef enum {
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SAMPLER_STATE_EXTEND_COUNT
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} sampler_state_extend_t;
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typedef enum {
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WM_KERNEL_NOMASK_AFFINE,
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WM_KERNEL_NOMASK_PROJECTIVE,
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WM_KERNEL_MASKCA_AFFINE,
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WM_KERNEL_MASKCA_PROJECTIVE,
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WM_KERNEL_MASKCA_SRCALPHA_AFFINE,
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WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE,
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WM_KERNEL_MASKNOCA_AFFINE,
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WM_KERNEL_MASKNOCA_PROJECTIVE,
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WM_KERNEL_COUNT
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} wm_kernel_t;
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#define KERNEL(kernel_enum, kernel, masked) \
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[kernel_enum] = {&kernel, sizeof(kernel), masked}
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struct wm_kernel_info {
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void *data;
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unsigned int size;
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Bool has_mask;
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} wm_kernels[] = {
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KERNEL(WM_KERNEL_NOMASK_AFFINE,
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ps_kernel_nomask_affine_static, FALSE),
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KERNEL(WM_KERNEL_NOMASK_PROJECTIVE,
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ps_kernel_nomask_projective_static, FALSE),
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KERNEL(WM_KERNEL_MASKCA_AFFINE,
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ps_kernel_maskca_affine_static, TRUE),
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KERNEL(WM_KERNEL_MASKCA_PROJECTIVE,
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ps_kernel_maskca_projective_static, TRUE),
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KERNEL(WM_KERNEL_MASKCA_SRCALPHA_AFFINE,
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ps_kernel_maskca_srcalpha_affine_static, TRUE),
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KERNEL(WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE,
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ps_kernel_maskca_srcalpha_projective_static, TRUE),
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KERNEL(WM_KERNEL_MASKNOCA_AFFINE,
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ps_kernel_masknoca_affine_static, TRUE),
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KERNEL(WM_KERNEL_MASKNOCA_PROJECTIVE,
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ps_kernel_masknoca_projective_static, TRUE),
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};
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#undef KERNEL
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typedef struct _brw_cc_unit_state_padded {
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struct brw_cc_unit_state state;
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char pad[64 - sizeof (struct brw_cc_unit_state)];
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@ -433,6 +471,12 @@ typedef struct brw_surface_state_padded {
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char pad[32 - sizeof (struct brw_surface_state)];
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} brw_surface_state_padded;
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struct gen4_cc_unit_state {
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/* Index by [src_blend][dst_blend] */
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brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
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[BRW_BLENDFACTOR_COUNT];
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};
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/**
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* Gen4 rendering state buffer structure.
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*
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@ -452,23 +496,6 @@ typedef struct _gen4_static_state {
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KERNEL_DECL (ps_kernel_masknoca_affine);
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KERNEL_DECL (ps_kernel_masknoca_projective);
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struct brw_vs_unit_state vs_state;
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PAD64 (brw_vs_unit_state, 0);
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struct brw_sf_unit_state sf_state;
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PAD64 (brw_sf_unit_state, 0);
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struct brw_sf_unit_state sf_state_mask;
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PAD64 (brw_sf_unit_state, 1);
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WM_STATE_DECL (nomask_affine);
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WM_STATE_DECL (nomask_projective);
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WM_STATE_DECL (maskca_affine);
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WM_STATE_DECL (maskca_projective);
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WM_STATE_DECL (maskca_srcalpha_affine);
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WM_STATE_DECL (maskca_srcalpha_projective);
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WM_STATE_DECL (masknoca_affine);
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WM_STATE_DECL (masknoca_projective);
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/* Index by [src_filter][src_extend][mask_filter][mask_extend]. Two of
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* the structs happen to add to 32 bytes.
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*/
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@ -479,12 +506,6 @@ typedef struct _gen4_static_state {
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struct brw_sampler_legacy_border_color sampler_border_color;
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PAD64 (brw_sampler_legacy_border_color, 0);
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/* Index by [src_blend][dst_blend] */
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brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
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[BRW_BLENDFACTOR_COUNT];
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struct brw_cc_viewport cc_viewport;
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PAD64 (brw_cc_viewport, 0);
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} gen4_static_state_t;
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typedef float gen4_vertex_buffer[VERTEX_BUFFER_SIZE];
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@ -510,6 +531,17 @@ struct gen4_render_state {
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gen4_static_state_t *static_state;
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uint32_t static_state_offset;
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drm_intel_bo *vs_state_bo;
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drm_intel_bo *sf_state_bo;
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drm_intel_bo *sf_mask_state_bo;
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drm_intel_bo *cc_state_bo;
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drm_intel_bo *wm_state_bo[WM_KERNEL_COUNT]
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[SAMPLER_STATE_FILTER_COUNT]
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[SAMPLER_STATE_EXTEND_COUNT]
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[SAMPLER_STATE_FILTER_COUNT]
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[SAMPLER_STATE_EXTEND_COUNT];
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drm_intel_bo *wm_kernel_bo[WM_KERNEL_COUNT];
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dri_bo* vertex_buffer_bo;
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gen4_composite_op composite_op;
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@ -527,9 +559,18 @@ struct gen4_render_state {
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* calculate dA/dx and dA/dy. Hand these interpolation coefficients
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* back to SF which then hands pixels off to WM.
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*/
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static void
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sf_state_init (struct brw_sf_unit_state *sf_state, int kernel_offset)
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static drm_intel_bo *
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gen4_create_sf_state(ScrnInfoPtr scrn, int kernel_offset)
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{
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I830Ptr pI830 = I830PTR(scrn);
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struct brw_sf_unit_state *sf_state;
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drm_intel_bo *sf_state_bo;
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sf_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 SF state",
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sizeof(*sf_state), 4096);
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drm_intel_bo_map(sf_state_bo, TRUE);
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sf_state = sf_state_bo->virtual;
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memset(sf_state, 0, sizeof(*sf_state));
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sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
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sf_state->sf1.single_program_flow = 1;
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@ -561,6 +602,10 @@ sf_state_init (struct brw_sf_unit_state *sf_state, int kernel_offset)
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assert((kernel_offset & 63) == 0);
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sf_state->thread0.kernel_start_pointer = kernel_offset >> 6;
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drm_intel_bo_unmap(sf_state_bo);
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return sf_state_bo;
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}
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static void
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@ -621,11 +666,17 @@ sampler_state_init (struct brw_sampler_state *sampler_state,
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}
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static void
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cc_state_init (struct brw_cc_unit_state *cc_state,
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cc_state_init (drm_intel_bo *cc_state_bo,
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uint32_t cc_state_offset,
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int src_blend,
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int dst_blend,
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int cc_viewport_offset)
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drm_intel_bo *cc_vp_bo)
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{
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struct brw_cc_unit_state *cc_state;
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cc_state = (struct brw_cc_unit_state *)((char *)cc_state_bo->virtual +
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cc_state_offset);
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memset(cc_state, 0, sizeof(*cc_state));
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cc_state->cc0.stencil_enable = 0; /* disable stencil */
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cc_state->cc2.depth_test = 0; /* disable depth test */
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@ -634,8 +685,11 @@ cc_state_init (struct brw_cc_unit_state *cc_state,
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cc_state->cc3.blend_enable = 1; /* enable color blend */
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cc_state->cc3.alpha_test = 0; /* disable alpha test */
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assert((cc_viewport_offset & 31) == 0);
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cc_state->cc4.cc_viewport_state_offset = cc_viewport_offset >> 5;
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cc_state->cc4.cc_viewport_state_offset =
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intel_emit_reloc(cc_state_bo, cc_state_offset +
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offsetof(struct brw_cc_unit_state, cc4),
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cc_vp_bo, 0,
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I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
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cc_state->cc5.dither_enable = 0; /* disable dither */
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cc_state->cc5.logicop_func = 0xc; /* COPY */
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@ -655,15 +709,29 @@ cc_state_init (struct brw_cc_unit_state *cc_state,
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cc_state->cc6.dest_blend_factor = dst_blend;
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}
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static void
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wm_state_init (struct brw_wm_unit_state *wm_state,
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Bool has_mask,
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int kernel_offset,
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int sampler_state_offset)
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static drm_intel_bo *
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gen4_create_wm_state(ScrnInfoPtr scrn,
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Bool has_mask, drm_intel_bo *kernel_bo,
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uint32_t sampler_state_offset)
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{
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I830Ptr pI830 = I830PTR(scrn);
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struct brw_wm_unit_state *wm_state;
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drm_intel_bo *wm_state_bo;
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wm_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 WM state",
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sizeof(*wm_state), 4096);
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drm_intel_bo_map(wm_state_bo, TRUE);
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wm_state = wm_state_bo->virtual;
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memset(wm_state, 0, sizeof (*wm_state));
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wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
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wm_state->thread1.single_program_flow = 0;
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wm_state->thread0.kernel_start_pointer =
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intel_emit_reloc(wm_state_bo,
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offsetof(struct brw_wm_unit_state, thread0),
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kernel_bo, wm_state->thread0.grf_reg_count << 1,
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I915_GEM_DOMAIN_INSTRUCTION, 0) >> 6;
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wm_state->thread1.single_program_flow = 0;
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/* scratch space is not used in our kernel */
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wm_state->thread2.scratch_space_base_pointer = 0;
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@ -690,9 +758,6 @@ wm_state_init (struct brw_wm_unit_state *wm_state,
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wm_state->wm5.enable_8_pix = 0;
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wm_state->wm5.early_depth_test = 1;
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assert((kernel_offset & 63) == 0);
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wm_state->thread0.kernel_start_pointer = kernel_offset >> 6;
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/* Each pair of attributes (src/mask coords) is two URB entries */
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if (has_mask) {
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wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
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@ -701,6 +766,76 @@ wm_state_init (struct brw_wm_unit_state *wm_state,
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wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
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wm_state->thread3.urb_entry_read_length = 2;
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}
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drm_intel_bo_unmap(wm_state_bo);
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return wm_state_bo;
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}
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static drm_intel_bo *
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gen4_create_cc_viewport(ScrnInfoPtr scrn)
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{
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I830Ptr pI830 = I830PTR(scrn);
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drm_intel_bo *bo;
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struct brw_cc_viewport cc_viewport;
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cc_viewport.min_depth = -1.e35;
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cc_viewport.max_depth = 1.e35;
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bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 render unit state",
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sizeof(cc_viewport), 4096);
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drm_intel_bo_subdata(bo, 0, sizeof(cc_viewport), &cc_viewport);
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return bo;
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}
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static drm_intel_bo *
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gen4_create_vs_unit_state(ScrnInfoPtr scrn)
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{
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struct brw_vs_unit_state vs_state;
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memset(&vs_state, 0, sizeof(vs_state));
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/* Set up the vertex shader to be disabled (passthrough) */
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vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
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vs_state.thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
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vs_state.vs6.vs_enable = 0;
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vs_state.vs6.vert_cache_disable = 1;
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return intel_bo_alloc_for_data(scrn, &vs_state, sizeof(vs_state),
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"gen4 render VS state");
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}
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/**
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* Set up all combinations of cc state: each blendfactor for source and
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* dest.
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*/
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static drm_intel_bo *
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gen4_create_cc_unit_state(ScrnInfoPtr scrn)
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{
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I830Ptr pI830 = I830PTR(scrn);
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struct gen4_cc_unit_state *cc_state;
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drm_intel_bo *cc_state_bo, *cc_vp_bo;
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int i, j;
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cc_vp_bo = gen4_create_cc_viewport(scrn);
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cc_state_bo = drm_intel_bo_alloc(pI830->bufmgr, "gen4 CC state",
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sizeof(*cc_state), 4096);
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drm_intel_bo_map(cc_state_bo, TRUE);
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cc_state = cc_state_bo->virtual;
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for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
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for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
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cc_state_init(cc_state_bo,
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offsetof(struct gen4_cc_unit_state,
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cc_state[i][j].state),
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i, j, cc_vp_bo);
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}
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}
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drm_intel_bo_unmap(cc_state_bo);
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drm_intel_bo_unreference(cc_vp_bo);
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return cc_state_bo;
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}
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/**
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@ -718,24 +853,8 @@ gen4_static_state_init (gen4_static_state_t *static_state,
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KERNEL_COPY (sip_kernel);
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KERNEL_COPY (sf_kernel);
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KERNEL_COPY (sf_kernel_mask);
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KERNEL_COPY (ps_kernel_nomask_affine);
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KERNEL_COPY (ps_kernel_nomask_projective);
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KERNEL_COPY (ps_kernel_maskca_affine);
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KERNEL_COPY (ps_kernel_maskca_projective);
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KERNEL_COPY (ps_kernel_maskca_srcalpha_affine);
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KERNEL_COPY (ps_kernel_maskca_srcalpha_projective);
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KERNEL_COPY (ps_kernel_masknoca_affine);
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KERNEL_COPY (ps_kernel_masknoca_projective);
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#undef KERNEL_COPY
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/* Set up the vertex shader to be disabled (passthrough) */
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memset(&static_state->vs_state, 0, sizeof(static_state->vs_state));
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static_state->vs_state.thread4.nr_urb_entries = URB_VS_ENTRIES;
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static_state->vs_state.thread4.urb_entry_allocation_size =
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URB_VS_ENTRY_SIZE - 1;
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static_state->vs_state.vs6.vs_enable = 0;
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static_state->vs_state.vs6.vert_cache_disable = 1;
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/* Set up the sampler border color (always transparent black) */
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memset(&static_state->sampler_border_color, 0,
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sizeof(static_state->sampler_border_color));
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@ -744,16 +863,6 @@ gen4_static_state_init (gen4_static_state_t *static_state,
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static_state->sampler_border_color.color[2] = 0; /* B */
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static_state->sampler_border_color.color[3] = 0; /* A */
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static_state->cc_viewport.min_depth = -1.e35;
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static_state->cc_viewport.max_depth = 1.e35;
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sf_state_init (&static_state->sf_state,
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static_state_offset +
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offsetof (gen4_static_state_t, sf_kernel));
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sf_state_init (&static_state->sf_state_mask,
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static_state_offset +
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offsetof (gen4_static_state_t, sf_kernel_mask));
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for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
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for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
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for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
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@ -772,42 +881,6 @@ gen4_static_state_init (gen4_static_state_t *static_state,
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}
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}
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}
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for (i = 0; i < BRW_BLENDFACTOR_COUNT; i++) {
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for (j = 0; j < BRW_BLENDFACTOR_COUNT; j++) {
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cc_state_init (&static_state->cc_state[i][j].state, i, j,
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static_state_offset +
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offsetof (gen4_static_state_t, cc_viewport));
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}
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}
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#define SETUP_WM_STATE(kernel, has_mask) \
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wm_state_init(&static_state->wm_state_ ## kernel [i][j][k][l], \
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has_mask, \
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static_state_offset + offsetof(gen4_static_state_t, \
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ps_kernel_ ## kernel), \
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static_state_offset + offsetof(gen4_static_state_t, \
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sampler_state[i][j][k][l]));
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for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
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for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
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for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
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for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
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SETUP_WM_STATE (nomask_affine, FALSE);
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SETUP_WM_STATE (nomask_projective, FALSE);
|
||||
SETUP_WM_STATE (maskca_affine, TRUE);
|
||||
SETUP_WM_STATE (maskca_projective, TRUE);
|
||||
SETUP_WM_STATE (maskca_srcalpha_affine, TRUE);
|
||||
SETUP_WM_STATE (maskca_srcalpha_projective, TRUE);
|
||||
SETUP_WM_STATE (masknoca_affine, TRUE);
|
||||
SETUP_WM_STATE (masknoca_projective, TRUE);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
#undef SETUP_WM_STATE
|
||||
}
|
||||
|
||||
static uint32_t
|
||||
|
|
@ -941,7 +1014,6 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
|
|||
PicturePtr pDstPicture = composite_op->dest_picture;
|
||||
PixmapPtr pMask = composite_op->mask;
|
||||
PixmapPtr pDst = composite_op->dest;
|
||||
uint32_t sf_state_offset;
|
||||
sampler_state_filter_t src_filter = composite_op->src_filter;
|
||||
sampler_state_filter_t mask_filter = composite_op->mask_filter;
|
||||
sampler_state_extend_t src_extend = composite_op->src_extend;
|
||||
|
|
@ -956,6 +1028,7 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
|
|||
int state_base_offset;
|
||||
uint32_t src_blend, dst_blend;
|
||||
dri_bo *binding_table_bo = composite_op->binding_table_bo;
|
||||
wm_kernel_t wm_kernel;
|
||||
|
||||
render_state->needs_state_emit = FALSE;
|
||||
|
||||
|
|
@ -1058,33 +1131,16 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
|
|||
|
||||
/* Set the pointers to the 3d pipeline state */
|
||||
OUT_BATCH(BRW_3DSTATE_PIPELINED_POINTERS | 5);
|
||||
assert((offsetof(gen4_static_state_t, vs_state) & 31) == 0);
|
||||
OUT_BATCH(state_base_offset + offsetof(gen4_static_state_t, vs_state));
|
||||
OUT_RELOC(render_state->vs_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
|
||||
OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
|
||||
OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
|
||||
|
||||
if (pMask) {
|
||||
sf_state_offset = state_base_offset +
|
||||
offsetof(gen4_static_state_t, sf_state_mask);
|
||||
OUT_RELOC(render_state->sf_mask_state_bo,
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
|
||||
} else {
|
||||
sf_state_offset = state_base_offset +
|
||||
offsetof(gen4_static_state_t, sf_state);
|
||||
OUT_RELOC(render_state->sf_state_bo,
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
|
||||
}
|
||||
assert((sf_state_offset & 31) == 0);
|
||||
OUT_BATCH(sf_state_offset);
|
||||
|
||||
/* Shorthand for long array lookup */
|
||||
#define OUT_WM_KERNEL(kernel) do { \
|
||||
uint32_t offset = state_base_offset + \
|
||||
offsetof(gen4_static_state_t, \
|
||||
wm_state_ ## kernel \
|
||||
[src_filter] \
|
||||
[src_extend] \
|
||||
[mask_filter] \
|
||||
[mask_extend]); \
|
||||
assert((offset & 31) == 0); \
|
||||
OUT_BATCH(offset); \
|
||||
} while (0)
|
||||
|
||||
if (pMask) {
|
||||
if (pMaskPicture->componentAlpha &&
|
||||
|
|
@ -1092,34 +1148,36 @@ i965_emit_composite_state(ScrnInfoPtr pScrn)
|
|||
{
|
||||
if (i965_blend_op[op].src_alpha) {
|
||||
if (is_affine)
|
||||
OUT_WM_KERNEL(maskca_srcalpha_affine);
|
||||
wm_kernel = WM_KERNEL_MASKCA_SRCALPHA_AFFINE;
|
||||
else
|
||||
OUT_WM_KERNEL(maskca_srcalpha_projective);
|
||||
wm_kernel = WM_KERNEL_MASKCA_SRCALPHA_PROJECTIVE;
|
||||
} else {
|
||||
if (is_affine)
|
||||
OUT_WM_KERNEL(maskca_affine);
|
||||
wm_kernel = WM_KERNEL_MASKCA_AFFINE;
|
||||
else
|
||||
OUT_WM_KERNEL(maskca_projective);
|
||||
wm_kernel = WM_KERNEL_MASKCA_PROJECTIVE;
|
||||
}
|
||||
} else {
|
||||
if (is_affine)
|
||||
OUT_WM_KERNEL(masknoca_affine);
|
||||
wm_kernel = WM_KERNEL_MASKNOCA_AFFINE;
|
||||
else
|
||||
OUT_WM_KERNEL(masknoca_projective);
|
||||
wm_kernel = WM_KERNEL_MASKNOCA_PROJECTIVE;
|
||||
}
|
||||
} else {
|
||||
if (is_affine)
|
||||
OUT_WM_KERNEL(nomask_affine);
|
||||
wm_kernel = WM_KERNEL_NOMASK_AFFINE;
|
||||
else
|
||||
OUT_WM_KERNEL(nomask_projective);
|
||||
wm_kernel = WM_KERNEL_NOMASK_PROJECTIVE;
|
||||
}
|
||||
#undef OUT_WM_KERNEL
|
||||
OUT_RELOC(render_state->wm_state_bo[wm_kernel]
|
||||
[src_filter][src_extend]
|
||||
[mask_filter][mask_extend],
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
|
||||
|
||||
/* 64 byte aligned */
|
||||
assert((offsetof(gen4_static_state_t,
|
||||
cc_state[src_blend][dst_blend]) & 63) == 0);
|
||||
OUT_BATCH(state_base_offset +
|
||||
offsetof(gen4_static_state_t, cc_state[src_blend][dst_blend]));
|
||||
OUT_RELOC(render_state->cc_state_bo,
|
||||
I915_GEM_DOMAIN_INSTRUCTION, 0,
|
||||
offsetof(struct gen4_cc_unit_state,
|
||||
cc_state[src_blend][dst_blend]));
|
||||
|
||||
/* URB fence */
|
||||
OUT_BATCH(BRW_URB_FENCE |
|
||||
|
|
@ -1590,7 +1648,9 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
|
|||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
struct gen4_render_state *render_state;
|
||||
uint32_t static_state_offset;
|
||||
int ret;
|
||||
int i, j, k, l, m;
|
||||
|
||||
if (pI830->gen4_render_state == NULL)
|
||||
pI830->gen4_render_state = calloc(sizeof(*render_state), 1);
|
||||
|
|
@ -1598,6 +1658,7 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
|
|||
render_state = pI830->gen4_render_state;
|
||||
|
||||
render_state->static_state_offset = pI830->gen4_render_state_mem->offset;
|
||||
static_state_offset = render_state->static_state_offset;
|
||||
|
||||
if (pI830->use_drm_mode) {
|
||||
ret = dri_bo_map(pI830->gen4_render_state_mem->bo, 1);
|
||||
|
|
@ -1611,9 +1672,51 @@ gen4_render_state_init(ScrnInfoPtr pScrn)
|
|||
render_state->static_state = (gen4_static_state_t *)
|
||||
(pI830->FbBase + render_state->static_state_offset);
|
||||
}
|
||||
|
||||
gen4_static_state_init(render_state->static_state,
|
||||
render_state->static_state_offset);
|
||||
|
||||
render_state->vs_state_bo = gen4_create_vs_unit_state(pScrn);
|
||||
/* Set up the two SF states (one for blending with a mask, one without) */
|
||||
render_state->sf_state_bo =
|
||||
gen4_create_sf_state(pScrn, static_state_offset +
|
||||
offsetof(gen4_static_state_t,
|
||||
sf_kernel));
|
||||
render_state->sf_mask_state_bo =
|
||||
gen4_create_sf_state(pScrn, static_state_offset +
|
||||
offsetof(gen4_static_state_t,
|
||||
sf_kernel_mask));
|
||||
|
||||
for (m = 0; m < WM_KERNEL_COUNT; m++) {
|
||||
render_state->wm_kernel_bo[m] =
|
||||
intel_bo_alloc_for_data(pScrn,
|
||||
wm_kernels[m].data, wm_kernels[m].size,
|
||||
"WM kernel");
|
||||
}
|
||||
|
||||
/* Set up the WM states: each filter/extend type for source and mask, per
|
||||
* kernel.
|
||||
*/
|
||||
for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
|
||||
for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
|
||||
for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
|
||||
for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
|
||||
for (m = 0; m < WM_KERNEL_COUNT; m++) {
|
||||
uint32_t sampler_offset = static_state_offset +
|
||||
offsetof(gen4_static_state_t,
|
||||
sampler_state[i][j][k][l]);
|
||||
|
||||
render_state->wm_state_bo[m][i][j][k][l] =
|
||||
gen4_create_wm_state(pScrn,
|
||||
wm_kernels[m].has_mask,
|
||||
render_state->wm_kernel_bo[m],
|
||||
sampler_offset);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
render_state->cc_state_bo = gen4_create_cc_unit_state(pScrn);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -1624,6 +1727,7 @@ gen4_render_state_cleanup(ScrnInfoPtr pScrn)
|
|||
{
|
||||
I830Ptr pI830 = I830PTR(pScrn);
|
||||
struct gen4_render_state *render_state= pI830->gen4_render_state;
|
||||
int i;
|
||||
|
||||
if (render_state->vertex_buffer_bo) {
|
||||
dri_bo_unreference (render_state->vertex_buffer_bo);
|
||||
|
|
@ -1635,6 +1739,18 @@ gen4_render_state_cleanup(ScrnInfoPtr pScrn)
|
|||
dri_bo_unreference(pI830->gen4_render_state_mem->bo);
|
||||
}
|
||||
render_state->static_state = NULL;
|
||||
drm_intel_bo_unreference(render_state->vs_state_bo);
|
||||
render_state->vs_state_bo = NULL;
|
||||
drm_intel_bo_unreference(render_state->sf_state_bo);
|
||||
render_state->sf_state_bo = NULL;
|
||||
drm_intel_bo_unreference(render_state->sf_mask_state_bo);
|
||||
render_state->sf_mask_state_bo = NULL;
|
||||
drm_intel_bo_unreference(render_state->cc_state_bo);
|
||||
render_state->cc_state_bo = NULL;
|
||||
for (i = 0; i < WM_KERNEL_COUNT; i++) {
|
||||
drm_intel_bo_unreference(render_state->wm_kernel_bo[i]);
|
||||
render_state->wm_kernel_bo[i] = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
unsigned int
|
||||
|
|
|
|||
Loading…
Reference in New Issue