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uxa: Enable reduced fence sizes for i915 

Depends on libdrm 362457715faacd3101929e5f0d8ae250d0ad09df (for
HAS_RELAXED_FENCING define).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2010-10-29 11:07:50 +01:00
parent b066ddda31
commit 6b3ce2e870
2 changed files with 9 additions and 2 deletions
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1
src/intel.h
View File

@ -336,6 +336,7 @@ typedef struct intel_screen_private {
Bool tiling;
Bool swapbuffers_wait;
Bool has_relaxed_fencing;
int Chipset;
unsigned long LinearAddr;

10
src/intel_memory.c
View File

@ -94,7 +94,7 @@ unsigned long intel_get_fence_size(intel_screen_private *intel, unsigned long si
unsigned long i;
unsigned long start;
if (INTEL_INFO(intel)->gen >= 40) {
if (INTEL_INFO(intel)->gen >= 40 || intel->has_relaxed_fencing) {
/* The 965 can have fences at any page boundary. */
return ALIGN(size, GTT_PAGE_SIZE);
} else {
@ -294,11 +294,17 @@ void intel_set_gem_max_sizes(ScrnInfoPtr scrn)
{
intel_screen_private *intel = intel_get_screen_private(scrn);
struct drm_i915_gem_get_aperture aperture;
drm_i915_getparam_t gp;
int ret;
aperture.aper_available_size = 0;
ioctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GEM_GET_APERTURE, &aperture);
intel_set_max_bo_size(intel, &aperture);
intel_set_max_gtt_map_size(intel, &aperture);
intel_set_max_tiling_size(intel, &aperture);
gp.param = I915_PARAM_HAS_RELAXED_FENCING;
ret = drmIoctl(intel->drmSubFD, DRM_IOCTL_I915_GETPARAM, &gp);
intel->has_relaxed_fencing = ret == 0;
}