Create known output configuration at EnterVT time
Since we added the pipe A force quirk (leaving pipe A on all the time), DPMS calls to disable it have silently returned, leaving the pipe on. If another driver (like vesafb) has enabled it, we may end up with a bad configuration, leading to hangs or blank screens at VT switch time. Fixes bug #19603.
This commit is contained in:
Jesse Barnes
parent
7c94227dd4
commit
6deb26ae7b
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@ -1121,6 +1121,134 @@ i830_disable_vga_plane (xf86CrtcPtr crtc)
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}
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void
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i830_crtc_enable(xf86CrtcPtr crtc)
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{
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ScrnInfoPtr pScrn = crtc->scrn;
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I830Ptr pI830 = I830PTR(pScrn);
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I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
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int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
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uint32_t temp;
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/* Enable the DPLL */
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temp = INREG(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0)
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{
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OUTREG(dpll_reg, temp);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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}
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/* Enable the pipe */
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temp = INREG(pipeconf_reg);
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if ((temp & PIPEACONF_ENABLE) == 0)
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OUTREG(pipeconf_reg, temp | PIPEACONF_ENABLE);
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/* Enable the plane */
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temp = INREG(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0)
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{
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OUTREG(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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OUTREG(dspbase_reg, INREG(dspbase_reg));
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}
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i830_crtc_load_lut(crtc);
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/* Give the overlay scaler a chance to enable if it's on this pipe */
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i830_crtc_dpms_video(crtc, TRUE);
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/* Reenable compression if needed */
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if (i830_use_fb_compression(crtc))
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i830_enable_fb_compression(crtc);
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i830_modeset_ctl(crtc, 0);
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}
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void
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i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe)
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{
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ScrnInfoPtr pScrn = crtc->scrn;
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I830Ptr pI830 = I830PTR(pScrn);
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I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
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int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
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uint32_t temp;
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i830_modeset_ctl(crtc, 1);
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/* Shut off compression if in use */
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if (i830_use_fb_compression(crtc))
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i830_disable_fb_compression(crtc);
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/* Give the overlay scaler a chance to disable if it's on this pipe */
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i830_crtc_dpms_video(crtc, FALSE);
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/*
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* The documentation says :
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* - Disable planes (VGA or hires)
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* - Disable pipe
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* - Disable VGA display
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*/
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/* Disable display plane */
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temp = INREG(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0)
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{
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OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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OUTREG(dspbase_reg, INREG(dspbase_reg));
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POSTING_READ(dspbase_reg);
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}
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if (!IS_I9XX(pI830)) {
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/* Wait for vblank for the disable to take effect */
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i830WaitForVblank(pScrn);
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}
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/* May need to leave pipe A on */
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if (disable_pipe)
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{
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/* Next, disable display pipes */
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temp = INREG(pipeconf_reg);
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if ((temp & PIPEACONF_ENABLE) != 0) {
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OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
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POSTING_READ(pipeconf_reg);
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}
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/* Wait for vblank for the disable to take effect. */
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i830WaitForVblank(pScrn);
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temp = INREG(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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}
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/* Wait for the clocks to turn off. */
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usleep(150);
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}
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/* Disable the VGA plane that we never use. */
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i830_disable_vga_plane (crtc);
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}
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/**
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* Sets the power management mode of the pipe and plane.
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*
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@ -1134,12 +1262,7 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
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I830Ptr pI830 = I830PTR(pScrn);
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I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
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int pipe = intel_crtc->pipe;
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int plane = intel_crtc->plane;
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int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
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int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
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int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
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int dspbase_reg = (plane == 0) ? DSPABASE : DSPBBASE;
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uint32_t temp;
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Bool disable_pipe = TRUE;
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/* XXX: When our outputs are all unaware of DPMS modes other than off and
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* on, we should map those modes to DPMSModeOff in the CRTC.
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@ -1148,105 +1271,12 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
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case DPMSModeOn:
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case DPMSModeStandby:
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case DPMSModeSuspend:
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/* Enable the DPLL */
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temp = INREG(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) == 0)
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{
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OUTREG(dpll_reg, temp);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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OUTREG(dpll_reg, temp | DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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/* Wait for the clocks to stabilize. */
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usleep(150);
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}
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/* Enable the pipe */
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temp = INREG(pipeconf_reg);
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if ((temp & PIPEACONF_ENABLE) == 0)
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OUTREG(pipeconf_reg, temp | PIPEACONF_ENABLE);
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/* Enable the plane */
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temp = INREG(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0)
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{
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OUTREG(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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OUTREG(dspbase_reg, INREG(dspbase_reg));
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}
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i830_crtc_load_lut(crtc);
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/* Give the overlay scaler a chance to enable if it's on this pipe */
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i830_crtc_dpms_video(crtc, TRUE);
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/* Reenable compression if needed */
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if (i830_use_fb_compression(crtc))
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i830_enable_fb_compression(crtc);
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i830_modeset_ctl(crtc, 0);
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i830_crtc_enable(crtc);
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break;
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case DPMSModeOff:
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i830_modeset_ctl(crtc, 1);
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/* Shut off compression if in use */
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if (i830_use_fb_compression(crtc))
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i830_disable_fb_compression(crtc);
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/* Give the overlay scaler a chance to disable if it's on this pipe */
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i830_crtc_dpms_video(crtc, FALSE);
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/*
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* The documentation says :
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* - Disable planes (VGA or hires)
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* - Disable pipe
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* - Disable VGA display
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*/
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/* Disable display plane */
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temp = INREG(dspcntr_reg);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0)
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{
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OUTREG(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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OUTREG(dspbase_reg, INREG(dspbase_reg));
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POSTING_READ(dspbase_reg);
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}
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if (!IS_I9XX(pI830)) {
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/* Wait for vblank for the disable to take effect */
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i830WaitForVblank(pScrn);
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}
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/* May need to leave pipe A on */
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if ((pipe != 0) || !(pI830->quirk_flag & QUIRK_PIPEA_FORCE))
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{
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/* Next, disable display pipes */
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temp = INREG(pipeconf_reg);
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if ((temp & PIPEACONF_ENABLE) != 0) {
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OUTREG(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
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POSTING_READ(pipeconf_reg);
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}
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/* Wait for vblank for the disable to take effect. */
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i830WaitForVblank(pScrn);
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temp = INREG(dpll_reg);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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OUTREG(dpll_reg, temp & ~DPLL_VCO_ENABLE);
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POSTING_READ(dpll_reg);
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}
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/* Wait for the clocks to turn off. */
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usleep(150);
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}
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/* Disable the VGA plane that we never use. */
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i830_disable_vga_plane (crtc);
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if ((pipe == 0) && (pI830->quirk_flag & QUIRK_PIPEA_FORCE))
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disable_pipe = FALSE;
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i830_crtc_disable(crtc, disable_pipe);
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break;
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}
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@ -32,6 +32,8 @@ void i830PipeSetBase(xf86CrtcPtr crtc, int x, int y);
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void i830WaitForVblank(ScrnInfoPtr pScrn);
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void i830DescribeOutputConfiguration(ScrnInfoPtr pScrn);
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void i830_set_new_crtc_bo(ScrnInfoPtr pScrn);
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void i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe);
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void i830_crtc_enable(xf86CrtcPtr crtc);
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xf86CrtcPtr i830GetLoadDetectPipe(xf86OutputPtr output, DisplayModePtr mode, int *dpms_mode);
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void i830ReleaseLoadDetectPipe(xf86OutputPtr output, int dpms_mode);
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@ -2275,7 +2275,7 @@ RestoreHWState(ScrnInfoPtr pScrn)
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/* Disable pipes */
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for (i = 0; i < xf86_config->num_crtc; i++) {
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xf86CrtcPtr crtc = xf86_config->crtc[i];
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crtc->funcs->dpms(crtc, DPMSModeOff);
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i830_crtc_disable(crtc, TRUE);
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}
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i830WaitForVblank(pScrn);
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@ -3460,8 +3460,9 @@ static Bool
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I830EnterVT(int scrnIndex, int flags)
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{
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ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
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xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
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I830Ptr pI830 = I830PTR(pScrn);
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int ret;
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int i, ret;
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DPRINTF(PFX, "Enter VT\n");
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@ -3482,6 +3483,23 @@ I830EnterVT(int scrnIndex, int flags)
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SaveHWState(pScrn);
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}
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/* Get the hardware into a known state if needed */
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if (!pI830->use_drm_mode) {
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/* Disable outputs */
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for (i = 0; i < xf86_config->num_output; i++) {
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xf86OutputPtr output = xf86_config->output[i];
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output->funcs->dpms(output, DPMSModeOff);
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}
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i830WaitForVblank(pScrn);
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/* Disable pipes */
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for (i = 0; i < xf86_config->num_crtc; i++) {
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xf86CrtcPtr crtc = xf86_config->crtc[i];
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i830_crtc_disable(crtc, TRUE);
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}
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i830WaitForVblank(pScrn);
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}
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pI830->leaving = FALSE;
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if (!pI830->use_drm_mode)
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