Avoid needless flush emits in the blockhandler.
The EmitFlush in i830_dri.c was added as a pageflipping workaround, and was noted to not even be sufficient then. There's no reason for it to be there, so it's removed. After that, we just have to not emit an MI_FLUSH if we already had, and cursor movement no longer bashes memory manager.
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@ -463,6 +463,8 @@ typedef struct _I830Rec {
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#endif
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#endif
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Bool need_mi_flush;
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Bool NeedRingBufferLow;
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Bool allowPageFlip;
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Bool TripleBuffer;
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@ -32,10 +32,12 @@
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#include <assert.h>
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#include <stdlib.h>
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#include <errno.h>
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#include "xf86.h"
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#include "i830.h"
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#include "i830_ring.h"
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#include "i915_drm.h"
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static void
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intel_next_batch(ScrnInfoPtr pScrn)
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@ -116,4 +118,10 @@ intel_batch_flush(ScrnInfoPtr pScrn)
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dri_bo_unreference(pI830->batch_bo);
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intel_next_batch(pScrn);
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/* Mark that we need to flush whatever potential rendering we've done in the
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* blockhandler. We could set this less often, but it's probably not worth
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* the work.
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*/
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pI830->need_mi_flush = TRUE;
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}
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@ -1067,8 +1067,6 @@ I830DRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
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pI830->LockHeld = 1;
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i830_refresh_ring(pScrn);
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I830EmitFlush(pScrn);
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#ifdef DAMAGE
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if (!pI830->pDamage && pI830->allowPageFlip) {
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PixmapPtr pPix = pScreen->GetScreenPixmap(pScreen);
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@ -1122,8 +1120,6 @@ I830DRISwapContext(ScreenPtr pScreen, DRISyncType syncType,
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}
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#endif
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I830EmitFlush(pScrn);
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#ifdef DAMAGE
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/* Try flipping back to the front page if necessary */
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if (sPriv && !sPriv->pf_enabled && sPriv->pf_current_page != 0) {
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@ -2496,17 +2496,17 @@ I830BlockHandler(int i,
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if (pScrn->vtSema && !pI830->noAccel) {
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/* Emit a flush of the rendering cache, or on the 965 and beyond
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* rendering results may not hit the framebuffer until significantly
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* later. In the direct rendering case this is already done just
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* after the page flipping updates, so there's no need to duplicate
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* the effort here.
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* later.
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*/
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if (!pI830->noAccel && !pI830->directRenderingEnabled)
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if (!pI830->noAccel && pI830->need_mi_flush)
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I830EmitFlush(pScrn);
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/* Flush the batch, so that any rendering is executed in a timely
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* fashion.
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*/
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intel_batch_flush(pScrn);
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pI830->need_mi_flush = FALSE;
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}
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/*
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