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Merge branch 'master' into modesetting 

This reverts most of the mergedfb code.  This will instead be done in device-
independent RandR code.

Conflicts:

	src/Makefile.am
	src/i810_driver.c
	src/i810_reg.h
	src/i830.h
	src/i830_cursor.c
	src/i830_driver.c
	src/i830_modes.c
	src/i830_video.c
This commit is contained in:
Eric Anholt 2006-09-27 16:38:01 -07:00
parent fdb6de6635 b970166eab
commit 6ea16bf6b0
36 changed files with 7875 additions and 679 deletions
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163
README
View File

@ -1,8 +1,6 @@
$XFree86:
xc/programs/Xserver/hw/xfree86/doc/sgml/i810.sgml,v 1.4
2001/04/04 01:34:18 dawes Exp $ Information for i810 Users
Precision Insight, Inc.
3 March 2000
Information for Intel graphics driver users
Eric Anholt
2006-08-04
____________________________________________________________
Table of Contents
@ -12,88 +10,85 @@
2. Supported Hardware
3. Features
4. Technical Notes
5. Reported Working Video Cards
6. Configuration
7. Driver Options
8. Known Limitations
9. Author
5. Configuration
6. Driver Options
7. Known Limitations
8. Author
______________________________________________________________________
1. Introduction
11.. IInnttrroodduuccttiioonn
This document provides a brief summary of the i810/i815 support
provided by the i810 driver. Support for later chipsets is not
covered here. More up to date information about the i810 driver can
be found in the i810(4) manual page.
This document provides a brief summary of the Intel graphics support
provided by the xf86-video-intel driver. More information can also be
found in the i810(4) manual page.
2. Supported Hardware
22.. SSuuppppoorrtteedd HHaarrddwwaarree
+o Intel 810 motherboards:
+o i810,
+o i810,
+o i810-dc100,
+o i810-dc100,
+o i810e
+o i810e
+o i815
+o i815
+o i830
+o i845
+o i852
+o i855
+o i915
+o i945
+o i965
3. Features
33.. FFeeaattuurreess
+o Full support for 8, 15, 16, and 24 bit pixel depths.
+o Hardware cursor support to reduce sprite flicker.
+o Hardware accelerated 2D drawing engine support for 8, 15, 16 and 24
bit pixel depths.
+o Support for high resolution video modes up to 1600x1200.
+o Hardware accelerated 3D drawing using OpenGL and the DRI.
+o Fully programmable clock supported.
+o Hardware cursor support to reduce sprite flicker.
+o Robust text mode restore for VT switching.
+o Textured video XV implementation on i915 through i965.
+o Hardware overlay XV implementation up through i945.
+o Screen resize and rotation on chipsets up through i945.
+o Screen resize on i965.
4. Technical Notes
44.. TTeecchhnniiccaall NNootteess
+o Hardware acceleration is not possible when using the framebuffer in
32 bit per pixel format, and this mode is not supported by this
driver.
+o Interlace modes cannot be supported.
+o This driver currently only works for Linux/ix86 and recent versions
of FreeBSD. It requires the agpgart kernel support, which is
included in Linux kernels 2.3.42 and higher, and FreeBSD 4.1 and
higher.
+o This driver requires kernel support for AGP, which is included in
Linux kernels 2.3.42 and higher, and FreeBSD 4.1 and higher.
5. Reported Working Video Cards
+o Intel evaluation hardware - i810, i810-dc100, i810e and i815.
+o Tyan Tomcat Motherboard.
+o HappyPC set-top box.
6. Configuration
55.. CCoonnffiigguurraattiioonn
The driver auto-detects all device information necessary to initialize
the card. The only lines you need in the "Device" section of your
xorg.conf file are:
the card. The only lines you should need in the "Device" section of
your xorg.conf file are:
Section "Device"
Identifier "Intel i810"
@ -101,54 +96,68 @@
EndSection
or let xorgconfig do this for you.
However, if you have problems with auto-detection, you can specify:
In order to use most resolutions, it is necessary to install the
"agpgart.o" module. You will probably have to compile the module
yourself (see the notes in the module).
+o DacSpeed - in MHz
+o MemBase - physical address of the linear framebuffer
66.. DDrriivveerr OOppttiioonnss
+o IOBase - physical address of the memory mapped IO registers
In order to use most resolutions, it is necessary to install the (see
the notes in the module).
Note: the i810 driver detects whether your motherboard has display
cache video memory. This memory is has reduced bandwidth compared to
normal system memory, and isn't used by the server. The main function
of this memory is for ancillary buffers (eg. z buffer) in a
forthcoming 3d capable server.
Please refer to the i810(4) manual page for information on
configuration options.
7. Driver Options
77.. KKnnoowwnn LLiimmiittaattiioonnss
+o "NoAccel" - Turn off hardware acceleration
+o Many systems with Intel graphics have issues with setting video
modes at larger than some small maximum resolution. This is not
fixed in the current release, but is being actively worked on in
the modesetting branch.
+o Bug #5795: Some systems have issues with VT switching. This should
be fixed with the modesetting brach integration.
+o "SWCursor" - Request a software cursor (hardware is default)
+o Bug #5817: Hotkey switching from LVDS to CRT breaks CRT output.
This is a known issue, but will not be fixed in the current
release.
+o "Dac6Bit" - Force the use of a 6 Bit Dac (8 Bit is the default)
+o Bug #6635: Video is output from an incorrect offset in the
framebuffer. This is expected to be fixed with the modesetting
branch integration.
+o GL_EXT_texture_compression_s3tc is not supported. We can't support
the extension due to patent restrictions on compression, but may be
able to support an option for partial extension support in the
future. For now, this prevents Quake4 and some other games from
running.
8. Known Limitations
+o Some X Test Suite cases sometimes fail due to a timeout. These
cases include: Xt8/XtResizeWindow, Xt8/XtQueryGeometry,
Xt9/XtAppAddInput, Xt9/XtRemoveInput, Xt9/XtAppAddTimeOut,
Xt9/XtRemoveTimeOut, Xt9/XtAddGrab, Xt9/XtRemoveGrab.
+o Some X Test Suite cases fail in 64-bit mode: Xlib9/XDrawArc,
XDrawImageString, XDrawLine, XDrawRectangle, XDrawSegments,
XFillArc, XFillPolygon, XFillRectangle, XPutImage,
Xt11/XtVaGetSubresources, XtSetSubvalues, and XtVaSetSubvalues.
+o No 3D support in this release.
+o Running two X servers on different VTs is not supported at this
time.
+o Some GLEAN test cases fail if DRI is enabled: pointAtten,
readPixSanity, texCombine, texCube, texEnv, texgen,
coloredTexPerf2, and coloredLitPerf2.
9. Author
88.. AAuutthhoorr
+o Eric Anholt
+o Keith Whitwell
The X11R6.8 version of this driver originally came from XFree86 4.4
The X11R7.1 version of this driver originally came from XFree86 4.4
rc2.
The XFree86 version of this driver was donated to The XFree86 Project
@ -160,7 +169,9 @@
http://www.precisioninsight.com
The X.Org version of this driver is maintained by Intel Corporation.
http://www.intellinuxgraphics.org

117
README.sgml
View File

@ -3,31 +3,31 @@
]>
<article>
<title>Information for i810 Users
<author>Precision Insight, Inc.
<date>3 March 2000
<ident>
$XFree86: xc/programs/Xserver/hw/xfree86/doc/sgml/i810.sgml,v 1.4 2001/04/04 01:34:18 dawes Exp $
</ident>
<title>Information for Intel graphics driver users
<author>Eric Anholt
<date>2006-08-04
<toc>
<sect>Introduction
<p>
This document provides a brief summary of the i810/i815 support provided
by the i810 driver. Support for later chipsets is not covered here.
More up to date information about the i810 driver can be found in the
This document provides a brief summary of the Intel graphics support provided
by the xf86-video-intel driver. More information can also be found in the
<htmlurl name="i810(4)" url="i810.4.html"> manual page.
<sect>Supported Hardware
<p>
<itemize>
<item>Intel 810 motherboards:
<itemize>
<item>i810,
<item>i810-dc100,
<item>i810e
<item>i815
</itemize>
<item>i810,
<item>i810-dc100,
<item>i810e
<item>i815
<item>i830
<item>i845
<item>i852
<item>i855
<item>i915
<item>i945
<item>i965
</itemize>
@ -35,42 +35,31 @@ More up to date information about the i810 driver can be found in the
<p>
<itemize>
<item>Full support for 8, 15, 16, and 24 bit pixel depths.
<item>Hardware cursor support to reduce sprite flicker.
<item>Hardware accelerated 2D drawing engine support for 8, 15, 16 and
24 bit pixel depths.
<item>Support for high resolution video modes up to 1600x1200.
<item>Fully programmable clock supported.
<item>Robust text mode restore for VT switching.
<item>Hardware accelerated 3D drawing using OpenGL and the DRI.
<item>Hardware cursor support to reduce sprite flicker.
<item>Textured video XV implementation on i915 through i965.
<item>Hardware overlay XV implementation up through i945.
<item>Screen resize and rotation on chipsets up through i945.
<item>Screen resize on i965.
</itemize>
<sect>Technical Notes
<p>
<itemize>
<item>Hardware acceleration is not possible when using the framebuffer
in 32 bit per pixel format, and this mode is not supported by
this driver.
<item>Interlace modes cannot be supported.
<item>This driver currently only works for Linux/ix86 and recent versions
of FreeBSD. It requires the agpgart kernel support, which is
<item>This driver requires kernel support for AGP, which is
included in Linux kernels 2.3.42 and higher, and FreeBSD 4.1
and higher.
</itemize>
<sect>Reported Working Video Cards
<p>
<itemize>
<item>Intel evaluation hardware - i810, i810-dc100, i810e and i815.
<item>Tyan Tomcat Motherboard.
<item>HappyPC set-top box.
</itemize>
<sect>Configuration
<p>
The driver auto-detects all device information necessary to
initialize the card. The only lines you need in the "Device"
initialize the card. The only lines you should need in the "Device"
section of your xorg.conf file are:
<verb>
Section "Device"
@ -78,45 +67,51 @@ section of your xorg.conf file are:
Driver "i810"
EndSection
</verb>
or let <tt>xorgconfig</tt> do this for you.
However, if you have problems with auto-detection, you can specify:
<itemize>
<item>DacSpeed - in MHz
<item>MemBase - physical address of the linear framebuffer
<item>IOBase - physical address of the memory mapped IO registers
</itemize>
In order to use most resolutions, it is necessary to install the
'agpgart.o' module. You will probably have to compile the module yourself
"agpgart.o" module. You will probably have to compile the module yourself
(see the notes in the module).
Note: the i810 driver detects whether your motherboard has display cache
video memory. This memory is has reduced bandwidth compared to normal
system memory, and isn't used by the server. The main function of this
memory is for ancillary buffers (eg. z buffer) in a forthcoming 3d
capable server.
<sect>Driver Options
<p>
<itemize>
<item>"NoAccel" - Turn off hardware acceleration
<item>"SWCursor" - Request a software cursor (hardware is default)
<item>"Dac6Bit" - Force the use of a 6 Bit Dac (8 Bit is the default)
</itemize>
Please refer to the <htmlurl name="i810(4)" url="i810.4.html"> manual page
for information on configuration options.
<sect>Known Limitations
<p>
<itemize>
<item>No 3D support in this release.
<item>Running two X servers on different VTs is not supported at this time.
<item>Many systems with Intel graphics have issues with setting video modes
at larger than some small maximum resolution. This is not fixed in the current
release, but is being actively worked on in the modesetting branch.
<item>Bug #5795: Some systems have issues with VT switching. This should
be fixed with the modesetting brach integration.
<item>Bug #5817: Hotkey switching from LVDS to CRT breaks CRT output. This
is a known issue, but will not be fixed in the current release.
<item>Bug #6635: Video is output from an incorrect offset in the framebuffer.
This is expected to be fixed with the modesetting branch integration.
<item>GL_EXT_texture_compression_s3tc is not supported. We can't support the
extension due to patent restrictions on compression, but may be able to support
an option for partial extension support in the future. For now, this prevents
Quake4 and some other games from running.
<item>Some X Test Suite cases sometimes fail due to a timeout. These cases
include: Xt8/XtResizeWindow, Xt8/XtQueryGeometry, Xt9/XtAppAddInput,
Xt9/XtRemoveInput, Xt9/XtAppAddTimeOut, Xt9/XtRemoveTimeOut, Xt9/XtAddGrab,
Xt9/XtRemoveGrab.
<item>Some X Test Suite cases fail in 64-bit mode: Xlib9/XDrawArc,
XDrawImageString, XDrawLine, XDrawRectangle, XDrawSegments, XFillArc,
XFillPolygon, XFillRectangle, XPutImage, Xt11/XtVaGetSubresources,
XtSetSubvalues, and XtVaSetSubvalues.
<item>Some GLEAN test cases fail if DRI is enabled: pointAtten,
readPixSanity, texCombine, texCube, texEnv, texgen, coloredTexPerf2, and
coloredLitPerf2.
</itemize>
<sect>Author
<p>
<itemize>
<item>Eric Anholt
<item>Keith Whitwell
</itemize>
@ -129,8 +124,10 @@ The XFree86 version of this driver was donated to The XFree86 Project by:
USA
</verb>
<htmlurl name="http://www.precisioninsight.com"
url="http://www.precisioninsight.com">
The X.Org version of this driver is maintained by Intel Corporation.
<htmlurl name="http://www.intellinuxgraphics.org"
url="http://www.intellinuxgraphics.org">
</article>

16
configure.ac
View File

@ -22,10 +22,20 @@
AC_PREREQ(2.57)
AC_INIT([xf86-video-i810],
1.6.0,
1.6.5,
[https://bugs.freedesktop.org/enter_bug.cgi?product=xorg],
xf86-video-i810)
AC_DEFINE_UNQUOTED([INTEL_VERSION_MAJOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^\([[0-9]]\)\.[[0-9]]\.[[0-9]]/\1/')],
[Major version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_MINOR],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.\([[0-9]]\)\.[[0-9]]/\1/')],
[Minor version])
AC_DEFINE_UNQUOTED([INTEL_VERSION_PATCH],
[$(echo $PACKAGE_VERSION | sed -e 's/^[[0-9]]\.[[0-9]]\.\([[0-9]]\)/\1/')],
[Patch version])
AC_CONFIG_SRCDIR([Makefile.am])
AM_CONFIG_HEADER([config.h])
AC_CONFIG_AUX_DIR(.)
@ -39,6 +49,9 @@ AC_DISABLE_STATIC
AC_PROG_LIBTOOL
AC_PROG_CC
AC_CHECK_PROG(gen4asm, [intel-gen4asm], yes, no)
AM_CONDITIONAL(HAVE_GEN4ASM, test x$gen4asm = xyes)
AH_TOP([#include "xorg-server.h"])
AC_ARG_WITH(xorg-module-dir,
@ -54,6 +67,7 @@ AC_ARG_ENABLE(dri, AC_HELP_STRING([--disable-dri],
# Checks for extensions
XORG_DRIVER_CHECK_EXT(XINERAMA, xineramaproto)
XORG_DRIVER_CHECK_EXT(RANDR, randrproto)
XORG_DRIVER_CHECK_EXT(RENDER, renderproto)
XORG_DRIVER_CHECK_EXT(XF86DRI, xextproto x11)

2
man/.gitignore vendored
View File

@ -1,2 +0,0 @@
i810.4
i810.4x

33
man/i810.man
View File

@ -17,30 +17,29 @@ i810 \- Intel 8xx integrated graphics chipsets
is an __xservername__ driver for Intel integrated graphics chipsets.
The driver supports depths 8, 15, 16 and 24. All visual types are
supported in depth 8. For the i810/i815 other depths support the
TrueColor and DirectColor visuals. For the 830M and later, only the
TrueColor and DirectColor visuals. For the i830M and later, only the
TrueColor visual is supported for depths greater than 8. The driver
supports hardware accelerated 3D via the Direct Rendering Infrastructure
(DRI), but only in depth 16 for the i810/i815 and depths 16 and 24 for
the 830M and later.
.SH SUPPORTED HARDWARE
.B i810
supports the i810, i810-DC100, i810e, i815, 830M, 845G, 852GM, 855GM,
865G, 915G and 915GM chipsets.
supports the i810, i810-DC100, i810e, i815, i830M, 845G, 852GM, 855GM,
865G, 915G, 915GM, 945G, 945GM, 965G, 965Q and 946GZ chipsets.
.SH CONFIGURATION DETAILS
Please refer to __xconfigfile__(__filemansuffix__) for general configuration
details. This section only covers configuration details specific to this
driver.
.PP
The Intel 8xx family of integrated graphics chipsets has a unified memory
architecture and uses system memory for video ram. For the i810 and
The Intel 8xx and 9xx families of integrated graphics chipsets has a unified
memory architecture and uses system memory for video ram. For the i810 and
i815 family of chipset, operating system support for allocating system
memory for video use is required in order to use this driver. For the
830M and later, this is required in order for the driver to use more
video ram than has been pre-allocated at boot time by the BIOS. This
is usually achieved with an "agpgart" or "agp" kernel driver. Linux,
and recent versions of FreeBSD, OpenBSD and NetBSD have such kernel
drivers available.
memory for video use is required in order to use this driver. For the 830M
and later, this is required in order for the driver to use more video ram
than has been pre-allocated at boot time by the BIOS. This is usually
achieved with an "agpgart" or "agp" kernel driver. Linux, and recent
versions of FreeBSD, OpenBSD and NetBSD have such kernel drivers available.
.PP
By default 8 Megabytes
of system memory are used for graphics. For the 830M and later, the
@ -188,9 +187,11 @@ Default 0KB (off).
.SH "SEE ALSO"
__xservername__(__appmansuffix__), __xconfigfile__(__filemansuffix__), xorgconfig(__appmansuffix__), Xserver(__appmansuffix__), X(__miscmansuffix__)
.SH AUTHORS
Authors include: Keith Whitwell, and also Jonathan Bian, Matthew J Sottek,
Authors include: Keith Whitwell, and also Jonathan Bian, Matthew J Sottek,
Jeff Hartmann, Mark Vojkovich, Alan Hourihane, H. J. Lu. 830M and 845G
support reworked for XFree86 4.3 by David Dawes and Keith Whitwell.
852GM, 855GM, and 865G support added by David Dawes and Keith Whitwell.
915G and 915GM support added by Alan Hourihane and Keith Whitwell.
Dual Head, Clone and lid status support added by Alan Hourihane.
support reworked for XFree86 4.3 by David Dawes and Keith Whitwell. 852GM,
855GM, and 865G support added by David Dawes and Keith Whitwell. 915G,
915GM, 945G, 945GM, 965G, 965Q and 946GZ support added by Alan Hourihane and
Keith Whitwell. Dual Head, Clone and lid status support added by Alan
Hourihane. Textured video support for 915G and later chips added by Keith
Packard and Eric Anholt.

25
src/Makefile.am
View File

@ -31,6 +31,10 @@ i810_drv_la_LDFLAGS = -module -avoid-version
i810_drv_ladir = @moduledir@/drivers
i810_drv_la_SOURCES = \
brw_defines.h \
brw_structs.h \
sf_prog.h \
wm_prog.h \
common.h \
i2c_vid.h \
i810_accel.c \
@ -44,6 +48,7 @@ i810_drv_la_SOURCES = \
i810_reg.h \
i810_video.c \
i810_wmark.c \
i830_3d.c \
i830_accel.c \
i830_bios.c \
i830_bios.h \
@ -63,13 +68,27 @@ i810_drv_la_SOURCES = \
i830_memory.c \
i830_modes.c \
i830_video.c \
i830_video.h \
i830_reg.h \
i830_rotate.c \
i830_randr.c \
i830_sdvo.c \
i830_sdvo.h \
i830_sdvo_regs.h \
i830_xf86Modes.h \
i830_xf86Modes.c
i830_xf86Modes.c \
i915_3d.c \
i915_3d.h \
i915_reg.h \
i915_video.c
if HAVE_GEN4ASM
sf_prog.h: packed_yuv_sf.g4a
intel-gen4asm -o sf_prog.h packed_yuv_sf.g4a
wm_prog.h: packed_yuv_wm.g4a
intel-gen4asm -o wm_prog.h packed_yuv_wm.g4a
endif
if DRI
i810_drv_la_SOURCES += \
i810_dri.c \
@ -78,3 +97,7 @@ i810_drv_la_SOURCES += \
i810_hwmc.c \
i830_dri.h
endif
EXTRA_DIST = \
packed_yuv_sf.g4a \
packed_yuv_wm.g4a

847
src/brw_defines.h Normal file
View File

@ -0,0 +1,847 @@
/**************************************************************************
*
* Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifndef BRW_DEFINES_H
#define BRW_DEFINES_H
/*
*/
#if 0
#define MI_NOOP 0x00
#define MI_USER_INTERRUPT 0x02
#define MI_WAIT_FOR_EVENT 0x03
#define MI_FLUSH 0x04
#define MI_REPORT_HEAD 0x07
#define MI_ARB_ON_OFF 0x08
#define MI_BATCH_BUFFER_END 0x0A
#define MI_OVERLAY_FLIP 0x11
#define MI_LOAD_SCAN_LINES_INCL 0x12
#define MI_LOAD_SCAN_LINES_EXCL 0x13
#define MI_DISPLAY_BUFFER_INFO 0x14
#define MI_SET_CONTEXT 0x18
#define MI_STORE_DATA_IMM 0x20
#define MI_STORE_DATA_INDEX 0x21
#define MI_LOAD_REGISTER_IMM 0x22
#define MI_STORE_REGISTER_MEM 0x24
#define MI_BATCH_BUFFER_START 0x31
#define MI_SYNCHRONOUS_FLIP 0x0
#define MI_ASYNCHRONOUS_FLIP 0x1
#define MI_BUFFER_SECURE 0x0
#define MI_BUFFER_NONSECURE 0x1
#define MI_ARBITRATE_AT_CHAIN_POINTS 0x0
#define MI_ARBITRATE_BETWEEN_INSTS 0x1
#define MI_NO_ARBITRATION 0x3
#define MI_CONDITION_CODE_WAIT_DISABLED 0x0
#define MI_CONDITION_CODE_WAIT_0 0x1
#define MI_CONDITION_CODE_WAIT_1 0x2
#define MI_CONDITION_CODE_WAIT_2 0x3
#define MI_CONDITION_CODE_WAIT_3 0x4
#define MI_CONDITION_CODE_WAIT_4 0x5
#define MI_DISPLAY_PIPE_A 0x0
#define MI_DISPLAY_PIPE_B 0x1
#define MI_DISPLAY_PLANE_A 0x0
#define MI_DISPLAY_PLANE_B 0x1
#define MI_DISPLAY_PLANE_C 0x2
#define MI_STANDARD_FLIP 0x0
#define MI_ENQUEUE_FLIP_PERFORM_BASE_FRAME_NUMBER_LOAD 0x1
#define MI_ENQUEUE_FLIP_TARGET_FRAME_NUMBER_RELATIVE 0x2
#define MI_ENQUEUE_FLIP_ABSOLUTE_TARGET_FRAME_NUMBER 0x3
#define MI_PHYSICAL_ADDRESS 0x0
#define MI_VIRTUAL_ADDRESS 0x1
#define MI_BUFFER_MEMORY_MAIN 0x0
#define MI_BUFFER_MEMORY_GTT 0x2
#define MI_BUFFER_MEMORY_PER_PROCESS_GTT 0x3
#define MI_FLIP_CONTINUE 0x0
#define MI_FLIP_ON 0x1
#define MI_FLIP_OFF 0x2
#define MI_UNTRUSTED_REGISTER_SPACE 0x0
#define MI_TRUSTED_REGISTER_SPACE 0x1
#endif
/* 3D state:
*/
#define _3DOP_3DSTATE_PIPELINED 0x0
#define _3DOP_3DSTATE_NONPIPELINED 0x1
#define _3DOP_3DCONTROL 0x2
#define _3DOP_3DPRIMITIVE 0x3
#define _3DSTATE_PIPELINED_POINTERS 0x00
#define _3DSTATE_BINDING_TABLE_POINTERS 0x01
#define _3DSTATE_VERTEX_BUFFERS 0x08
#define _3DSTATE_VERTEX_ELEMENTS 0x09
#define _3DSTATE_INDEX_BUFFER 0x0A
#define _3DSTATE_VF_STATISTICS 0x0B
#define _3DSTATE_DRAWING_RECTANGLE 0x00
#define _3DSTATE_CONSTANT_COLOR 0x01
#define _3DSTATE_SAMPLER_PALETTE_LOAD 0x02
#define _3DSTATE_CHROMA_KEY 0x04
#define _3DSTATE_DEPTH_BUFFER 0x05
#define _3DSTATE_POLY_STIPPLE_OFFSET 0x06
#define _3DSTATE_POLY_STIPPLE_PATTERN 0x07
#define _3DSTATE_LINE_STIPPLE 0x08
#define _3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP 0x09
#define _3DCONTROL 0x00
#define _3DPRIMITIVE 0x00
#define PIPE_CONTROL_NOWRITE 0x00
#define PIPE_CONTROL_WRITEIMMEDIATE 0x01
#define PIPE_CONTROL_WRITEDEPTH 0x02
#define PIPE_CONTROL_WRITETIMESTAMP 0x03
#define PIPE_CONTROL_GTTWRITE_PROCESS_LOCAL 0x00
#define PIPE_CONTROL_GTTWRITE_GLOBAL 0x01
#define _3DPRIM_POINTLIST 0x01
#define _3DPRIM_LINELIST 0x02
#define _3DPRIM_LINESTRIP 0x03
#define _3DPRIM_TRILIST 0x04
#define _3DPRIM_TRISTRIP 0x05
#define _3DPRIM_TRIFAN 0x06
#define _3DPRIM_QUADLIST 0x07
#define _3DPRIM_QUADSTRIP 0x08
#define _3DPRIM_LINELIST_ADJ 0x09
#define _3DPRIM_LINESTRIP_ADJ 0x0A
#define _3DPRIM_TRILIST_ADJ 0x0B
#define _3DPRIM_TRISTRIP_ADJ 0x0C
#define _3DPRIM_TRISTRIP_REVERSE 0x0D
#define _3DPRIM_POLYGON 0x0E
#define _3DPRIM_RECTLIST 0x0F
#define _3DPRIM_LINELOOP 0x10
#define _3DPRIM_POINTLIST_BF 0x11
#define _3DPRIM_LINESTRIP_CONT 0x12
#define _3DPRIM_LINESTRIP_BF 0x13
#define _3DPRIM_LINESTRIP_CONT_BF 0x14
#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0
#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1
#define BRW_ANISORATIO_2 0
#define BRW_ANISORATIO_4 1
#define BRW_ANISORATIO_6 2
#define BRW_ANISORATIO_8 3
#define BRW_ANISORATIO_10 4
#define BRW_ANISORATIO_12 5
#define BRW_ANISORATIO_14 6
#define BRW_ANISORATIO_16 7
#define BRW_BLENDFACTOR_ONE 0x1
#define BRW_BLENDFACTOR_SRC_COLOR 0x2
#define BRW_BLENDFACTOR_SRC_ALPHA 0x3
#define BRW_BLENDFACTOR_DST_ALPHA 0x4
#define BRW_BLENDFACTOR_DST_COLOR 0x5
#define BRW_BLENDFACTOR_SRC_ALPHA_SATURATE 0x6
#define BRW_BLENDFACTOR_CONST_COLOR 0x7
#define BRW_BLENDFACTOR_CONST_ALPHA 0x8
#define BRW_BLENDFACTOR_SRC1_COLOR 0x9
#define BRW_BLENDFACTOR_SRC1_ALPHA 0x0A
#define BRW_BLENDFACTOR_ZERO 0x11
#define BRW_BLENDFACTOR_INV_SRC_COLOR 0x12
#define BRW_BLENDFACTOR_INV_SRC_ALPHA 0x13
#define BRW_BLENDFACTOR_INV_DST_ALPHA 0x14
#define BRW_BLENDFACTOR_INV_DST_COLOR 0x15
#define BRW_BLENDFACTOR_INV_CONST_COLOR 0x17
#define BRW_BLENDFACTOR_INV_CONST_ALPHA 0x18
#define BRW_BLENDFACTOR_INV_SRC1_COLOR 0x19
#define BRW_BLENDFACTOR_INV_SRC1_ALPHA 0x1A
#define BRW_BLENDFUNCTION_ADD 0
#define BRW_BLENDFUNCTION_SUBTRACT 1
#define BRW_BLENDFUNCTION_REVERSE_SUBTRACT 2
#define BRW_BLENDFUNCTION_MIN 3
#define BRW_BLENDFUNCTION_MAX 4
#define BRW_ALPHATEST_FORMAT_UNORM8 0
#define BRW_ALPHATEST_FORMAT_FLOAT32 1
#define BRW_CHROMAKEY_KILL_ON_ANY_MATCH 0
#define BRW_CHROMAKEY_REPLACE_BLACK 1
#define BRW_CLIP_API_OGL 0
#define BRW_CLIP_API_DX 1
#define BRW_CLIPMODE_NORMAL 0
#define BRW_CLIPMODE_CLIP_ALL 1
#define BRW_CLIPMODE_CLIP_NON_REJECTED 2
#define BRW_CLIPMODE_REJECT_ALL 3
#define BRW_CLIPMODE_ACCEPT_ALL 4
#define BRW_CLIP_NDCSPACE 0
#define BRW_CLIP_SCREENSPACE 1
#define BRW_COMPAREFUNCTION_ALWAYS 0
#define BRW_COMPAREFUNCTION_NEVER 1
#define BRW_COMPAREFUNCTION_LESS 2
#define BRW_COMPAREFUNCTION_EQUAL 3
#define BRW_COMPAREFUNCTION_LEQUAL 4
#define BRW_COMPAREFUNCTION_GREATER 5
#define BRW_COMPAREFUNCTION_NOTEQUAL 6
#define BRW_COMPAREFUNCTION_GEQUAL 7
#define BRW_COVERAGE_PIXELS_HALF 0
#define BRW_COVERAGE_PIXELS_1 1
#define BRW_COVERAGE_PIXELS_2 2
#define BRW_COVERAGE_PIXELS_4 3
#define BRW_CULLMODE_BOTH 0
#define BRW_CULLMODE_NONE 1
#define BRW_CULLMODE_FRONT 2
#define BRW_CULLMODE_BACK 3
#define BRW_DEFAULTCOLOR_R8G8B8A8_UNORM 0
#define BRW_DEFAULTCOLOR_R32G32B32A32_FLOAT 1
#define BRW_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
#define BRW_DEPTHFORMAT_D32_FLOAT 1
#define BRW_DEPTHFORMAT_D24_UNORM_S8_UINT 2
#define BRW_DEPTHFORMAT_D16_UNORM 5
#define BRW_FLOATING_POINT_IEEE_754 0
#define BRW_FLOATING_POINT_NON_IEEE_754 1
#define BRW_FRONTWINDING_CW 0
#define BRW_FRONTWINDING_CCW 1
#define BRW_INDEX_BYTE 0
#define BRW_INDEX_WORD 1
#define BRW_INDEX_DWORD 2
#define BRW_LOGICOPFUNCTION_CLEAR 0
#define BRW_LOGICOPFUNCTION_NOR 1
#define BRW_LOGICOPFUNCTION_AND_INVERTED 2
#define BRW_LOGICOPFUNCTION_COPY_INVERTED 3
#define BRW_LOGICOPFUNCTION_AND_REVERSE 4
#define BRW_LOGICOPFUNCTION_INVERT 5
#define BRW_LOGICOPFUNCTION_XOR 6
#define BRW_LOGICOPFUNCTION_NAND 7
#define BRW_LOGICOPFUNCTION_AND 8
#define BRW_LOGICOPFUNCTION_EQUIV 9
#define BRW_LOGICOPFUNCTION_NOOP 10
#define BRW_LOGICOPFUNCTION_OR_INVERTED 11
#define BRW_LOGICOPFUNCTION_COPY 12
#define BRW_LOGICOPFUNCTION_OR_REVERSE 13
#define BRW_LOGICOPFUNCTION_OR 14
#define BRW_LOGICOPFUNCTION_SET 15
#define BRW_MAPFILTER_NEAREST 0x0
#define BRW_MAPFILTER_LINEAR 0x1
#define BRW_MAPFILTER_ANISOTROPIC 0x2
#define BRW_MIPFILTER_NONE 0
#define BRW_MIPFILTER_NEAREST 1
#define BRW_MIPFILTER_LINEAR 3
#define BRW_POLYGON_FRONT_FACING 0
#define BRW_POLYGON_BACK_FACING 1
#define BRW_PREFILTER_ALWAYS 0x0
#define BRW_PREFILTER_NEVER 0x1
#define BRW_PREFILTER_LESS 0x2
#define BRW_PREFILTER_EQUAL 0x3
#define BRW_PREFILTER_LEQUAL 0x4
#define BRW_PREFILTER_GREATER 0x5
#define BRW_PREFILTER_NOTEQUAL 0x6
#define BRW_PREFILTER_GEQUAL 0x7
#define BRW_PROVOKING_VERTEX_0 0
#define BRW_PROVOKING_VERTEX_1 1
#define BRW_PROVOKING_VERTEX_2 2
#define BRW_RASTRULE_UPPER_LEFT 0
#define BRW_RASTRULE_UPPER_RIGHT 1
#define BRW_RENDERTARGET_CLAMPRANGE_UNORM 0
#define BRW_RENDERTARGET_CLAMPRANGE_SNORM 1
#define BRW_RENDERTARGET_CLAMPRANGE_FORMAT 2
#define BRW_STENCILOP_KEEP 0
#define BRW_STENCILOP_ZERO 1
#define BRW_STENCILOP_REPLACE 2
#define BRW_STENCILOP_INCRSAT 3
#define BRW_STENCILOP_DECRSAT 4
#define BRW_STENCILOP_INCR 5
#define BRW_STENCILOP_DECR 6
#define BRW_STENCILOP_INVERT 7
#define BRW_SURFACE_MIPMAPLAYOUT_BELOW 0
#define BRW_SURFACE_MIPMAPLAYOUT_RIGHT 1
#define BRW_SURFACEFORMAT_R32G32B32A32_FLOAT 0x000
#define BRW_SURFACEFORMAT_R32G32B32A32_SINT 0x001
#define BRW_SURFACEFORMAT_R32G32B32A32_UINT 0x002
#define BRW_SURFACEFORMAT_R32G32B32A32_UNORM 0x003
#define BRW_SURFACEFORMAT_R32G32B32A32_SNORM 0x004
#define BRW_SURFACEFORMAT_R64G64_FLOAT 0x005
#define BRW_SURFACEFORMAT_R32G32B32X32_FLOAT 0x006
#define BRW_SURFACEFORMAT_R32G32B32A32_SSCALED 0x007
#define BRW_SURFACEFORMAT_R32G32B32A32_USCALED 0x008
#define BRW_SURFACEFORMAT_R32G32B32_FLOAT 0x040
#define BRW_SURFACEFORMAT_R32G32B32_SINT 0x041
#define BRW_SURFACEFORMAT_R32G32B32_UINT 0x042
#define BRW_SURFACEFORMAT_R32G32B32_UNORM 0x043
#define BRW_SURFACEFORMAT_R32G32B32_SNORM 0x044
#define BRW_SURFACEFORMAT_R32G32B32_SSCALED 0x045
#define BRW_SURFACEFORMAT_R32G32B32_USCALED 0x046
#define BRW_SURFACEFORMAT_R16G16B16A16_UNORM 0x080
#define BRW_SURFACEFORMAT_R16G16B16A16_SNORM 0x081
#define BRW_SURFACEFORMAT_R16G16B16A16_SINT 0x082
#define BRW_SURFACEFORMAT_R16G16B16A16_UINT 0x083
#define BRW_SURFACEFORMAT_R16G16B16A16_FLOAT 0x084
#define BRW_SURFACEFORMAT_R32G32_FLOAT 0x085
#define BRW_SURFACEFORMAT_R32G32_SINT 0x086
#define BRW_SURFACEFORMAT_R32G32_UINT 0x087
#define BRW_SURFACEFORMAT_R32_FLOAT_X8X24_TYPELESS 0x088
#define BRW_SURFACEFORMAT_X32_TYPELESS_G8X24_UINT 0x089
#define BRW_SURFACEFORMAT_L32A32_FLOAT 0x08A
#define BRW_SURFACEFORMAT_R32G32_UNORM 0x08B
#define BRW_SURFACEFORMAT_R32G32_SNORM 0x08C
#define BRW_SURFACEFORMAT_R64_FLOAT 0x08D
#define BRW_SURFACEFORMAT_R16G16B16X16_UNORM 0x08E
#define BRW_SURFACEFORMAT_R16G16B16X16_FLOAT 0x08F
#define BRW_SURFACEFORMAT_A32X32_FLOAT 0x090
#define BRW_SURFACEFORMAT_L32X32_FLOAT 0x091
#define BRW_SURFACEFORMAT_I32X32_FLOAT 0x092
#define BRW_SURFACEFORMAT_R16G16B16A16_SSCALED 0x093
#define BRW_SURFACEFORMAT_R16G16B16A16_USCALED 0x094
#define BRW_SURFACEFORMAT_R32G32_SSCALED 0x095
#define BRW_SURFACEFORMAT_R32G32_USCALED 0x096
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM 0x0C0
#define BRW_SURFACEFORMAT_B8G8R8A8_UNORM_SRGB 0x0C1
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM 0x0C2
#define BRW_SURFACEFORMAT_R10G10B10A2_UNORM_SRGB 0x0C3
#define BRW_SURFACEFORMAT_R10G10B10A2_UINT 0x0C4
#define BRW_SURFACEFORMAT_R10G10B10_SNORM_A2_UNORM 0x0C5
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM 0x0C7
#define BRW_SURFACEFORMAT_R8G8B8A8_UNORM_SRGB 0x0C8
#define BRW_SURFACEFORMAT_R8G8B8A8_SNORM 0x0C9
#define BRW_SURFACEFORMAT_R8G8B8A8_SINT 0x0CA
#define BRW_SURFACEFORMAT_R8G8B8A8_UINT 0x0CB
#define BRW_SURFACEFORMAT_R16G16_UNORM 0x0CC
#define BRW_SURFACEFORMAT_R16G16_SNORM 0x0CD
#define BRW_SURFACEFORMAT_R16G16_SINT 0x0CE
#define BRW_SURFACEFORMAT_R16G16_UINT 0x0CF
#define BRW_SURFACEFORMAT_R16G16_FLOAT 0x0D0
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM 0x0D1
#define BRW_SURFACEFORMAT_B10G10R10A2_UNORM_SRGB 0x0D2
#define BRW_SURFACEFORMAT_R11G11B10_FLOAT 0x0D3
#define BRW_SURFACEFORMAT_R32_SINT 0x0D6
#define BRW_SURFACEFORMAT_R32_UINT 0x0D7
#define BRW_SURFACEFORMAT_R32_FLOAT 0x0D8
#define BRW_SURFACEFORMAT_R24_UNORM_X8_TYPELESS 0x0D9
#define BRW_SURFACEFORMAT_X24_TYPELESS_G8_UINT 0x0DA
#define BRW_SURFACEFORMAT_L16A16_UNORM 0x0DF
#define BRW_SURFACEFORMAT_I24X8_UNORM 0x0E0
#define BRW_SURFACEFORMAT_L24X8_UNORM 0x0E1
#define BRW_SURFACEFORMAT_A24X8_UNORM 0x0E2
#define BRW_SURFACEFORMAT_I32_FLOAT 0x0E3
#define BRW_SURFACEFORMAT_L32_FLOAT 0x0E4
#define BRW_SURFACEFORMAT_A32_FLOAT 0x0E5
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM 0x0E9
#define BRW_SURFACEFORMAT_B8G8R8X8_UNORM_SRGB 0x0EA
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM 0x0EB
#define BRW_SURFACEFORMAT_R8G8B8X8_UNORM_SRGB 0x0EC
#define BRW_SURFACEFORMAT_R9G9B9E5_SHAREDEXP 0x0ED
#define BRW_SURFACEFORMAT_B10G10R10X2_UNORM 0x0EE
#define BRW_SURFACEFORMAT_L16A16_FLOAT 0x0F0
#define BRW_SURFACEFORMAT_R32_UNORM 0x0F1
#define BRW_SURFACEFORMAT_R32_SNORM 0x0F2
#define BRW_SURFACEFORMAT_R10G10B10X2_USCALED 0x0F3
#define BRW_SURFACEFORMAT_R8G8B8A8_SSCALED 0x0F4
#define BRW_SURFACEFORMAT_R8G8B8A8_USCALED 0x0F5
#define BRW_SURFACEFORMAT_R16G16_SSCALED 0x0F6
#define BRW_SURFACEFORMAT_R16G16_USCALED 0x0F7
#define BRW_SURFACEFORMAT_R32_SSCALED 0x0F8
#define BRW_SURFACEFORMAT_R32_USCALED 0x0F9
#define BRW_SURFACEFORMAT_B5G6R5_UNORM 0x100
#define BRW_SURFACEFORMAT_B5G6R5_UNORM_SRGB 0x101
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM 0x102
#define BRW_SURFACEFORMAT_B5G5R5A1_UNORM_SRGB 0x103
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM 0x104
#define BRW_SURFACEFORMAT_B4G4R4A4_UNORM_SRGB 0x105
#define BRW_SURFACEFORMAT_R8G8_UNORM 0x106
#define BRW_SURFACEFORMAT_R8G8_SNORM 0x107
#define BRW_SURFACEFORMAT_R8G8_SINT 0x108
#define BRW_SURFACEFORMAT_R8G8_UINT 0x109
#define BRW_SURFACEFORMAT_R16_UNORM 0x10A
#define BRW_SURFACEFORMAT_R16_SNORM 0x10B
#define BRW_SURFACEFORMAT_R16_SINT 0x10C
#define BRW_SURFACEFORMAT_R16_UINT 0x10D
#define BRW_SURFACEFORMAT_R16_FLOAT 0x10E
#define BRW_SURFACEFORMAT_I16_UNORM 0x111
#define BRW_SURFACEFORMAT_L16_UNORM 0x112
#define BRW_SURFACEFORMAT_A16_UNORM 0x113
#define BRW_SURFACEFORMAT_L8A8_UNORM 0x114
#define BRW_SURFACEFORMAT_I16_FLOAT 0x115
#define BRW_SURFACEFORMAT_L16_FLOAT 0x116
#define BRW_SURFACEFORMAT_A16_FLOAT 0x117
#define BRW_SURFACEFORMAT_R5G5_SNORM_B6_UNORM 0x119
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM 0x11A
#define BRW_SURFACEFORMAT_B5G5R5X1_UNORM_SRGB 0x11B
#define BRW_SURFACEFORMAT_R8G8_SSCALED 0x11C
#define BRW_SURFACEFORMAT_R8G8_USCALED 0x11D
#define BRW_SURFACEFORMAT_R16_SSCALED 0x11E
#define BRW_SURFACEFORMAT_R16_USCALED 0x11F
#define BRW_SURFACEFORMAT_R8_UNORM 0x140
#define BRW_SURFACEFORMAT_R8_SNORM 0x141
#define BRW_SURFACEFORMAT_R8_SINT 0x142
#define BRW_SURFACEFORMAT_R8_UINT 0x143
#define BRW_SURFACEFORMAT_A8_UNORM 0x144
#define BRW_SURFACEFORMAT_I8_UNORM 0x145
#define BRW_SURFACEFORMAT_L8_UNORM 0x146
#define BRW_SURFACEFORMAT_P4A4_UNORM 0x147
#define BRW_SURFACEFORMAT_A4P4_UNORM 0x148
#define BRW_SURFACEFORMAT_R8_SSCALED 0x149
#define BRW_SURFACEFORMAT_R8_USCALED 0x14A
#define BRW_SURFACEFORMAT_R1_UINT 0x181
#define BRW_SURFACEFORMAT_YCRCB_NORMAL 0x182
#define BRW_SURFACEFORMAT_YCRCB_SWAPUVY 0x183
#define BRW_SURFACEFORMAT_BC1_UNORM 0x186
#define BRW_SURFACEFORMAT_BC2_UNORM 0x187
#define BRW_SURFACEFORMAT_BC3_UNORM 0x188
#define BRW_SURFACEFORMAT_BC4_UNORM 0x189
#define BRW_SURFACEFORMAT_BC5_UNORM 0x18A
#define BRW_SURFACEFORMAT_BC1_UNORM_SRGB 0x18B
#define BRW_SURFACEFORMAT_BC2_UNORM_SRGB 0x18C
#define BRW_SURFACEFORMAT_BC3_UNORM_SRGB 0x18D
#define BRW_SURFACEFORMAT_MONO8 0x18E
#define BRW_SURFACEFORMAT_YCRCB_SWAPUV 0x18F
#define BRW_SURFACEFORMAT_YCRCB_SWAPY 0x190
#define BRW_SURFACEFORMAT_DXT1_RGB 0x191
#define BRW_SURFACEFORMAT_FXT1 0x192
#define BRW_SURFACEFORMAT_R8G8B8_UNORM 0x193
#define BRW_SURFACEFORMAT_R8G8B8_SNORM 0x194
#define BRW_SURFACEFORMAT_R8G8B8_SSCALED 0x195
#define BRW_SURFACEFORMAT_R8G8B8_USCALED 0x196
#define BRW_SURFACEFORMAT_R64G64B64A64_FLOAT 0x197
#define BRW_SURFACEFORMAT_R64G64B64_FLOAT 0x198
#define BRW_SURFACEFORMAT_BC4_SNORM 0x199
#define BRW_SURFACEFORMAT_BC5_SNORM 0x19A
#define BRW_SURFACEFORMAT_R16G16B16_UNORM 0x19C
#define BRW_SURFACEFORMAT_R16G16B16_SNORM 0x19D
#define BRW_SURFACEFORMAT_R16G16B16_SSCALED 0x19E
#define BRW_SURFACEFORMAT_R16G16B16_USCALED 0x19F
#define BRW_SURFACERETURNFORMAT_FLOAT32 0
#define BRW_SURFACERETURNFORMAT_S1 1
#define BRW_SURFACE_1D 0
#define BRW_SURFACE_2D 1
#define BRW_SURFACE_3D 2
#define BRW_SURFACE_CUBE 3
#define BRW_SURFACE_BUFFER 4
#define BRW_SURFACE_NULL 7
#define BRW_TEXCOORDMODE_WRAP 0
#define BRW_TEXCOORDMODE_MIRROR 1
#define BRW_TEXCOORDMODE_CLAMP 2
#define BRW_TEXCOORDMODE_CUBE 3
#define BRW_TEXCOORDMODE_CLAMP_BORDER 4
#define BRW_TEXCOORDMODE_MIRROR_ONCE 5
#define BRW_THREAD_PRIORITY_NORMAL 0
#define BRW_THREAD_PRIORITY_HIGH 1
#define BRW_TILEWALK_XMAJOR 0
#define BRW_TILEWALK_YMAJOR 1
#define BRW_VERTEX_SUBPIXEL_PRECISION_8BITS 0
#define BRW_VERTEX_SUBPIXEL_PRECISION_4BITS 1
#define BRW_VERTEXBUFFER_ACCESS_VERTEXDATA 0
#define BRW_VERTEXBUFFER_ACCESS_INSTANCEDATA 1
#define BRW_VFCOMPONENT_NOSTORE 0
#define BRW_VFCOMPONENT_STORE_SRC 1
#define BRW_VFCOMPONENT_STORE_0 2
#define BRW_VFCOMPONENT_STORE_1_FLT 3
#define BRW_VFCOMPONENT_STORE_1_INT 4
#define BRW_VFCOMPONENT_STORE_VID 5
#define BRW_VFCOMPONENT_STORE_IID 6
#define BRW_VFCOMPONENT_STORE_PID 7
/* Execution Unit (EU) defines
*/
#define BRW_ALIGN_1 0
#define BRW_ALIGN_16 1
#define BRW_ADDRESS_DIRECT 0
#define BRW_ADDRESS_REGISTER_INDIRECT_REGISTER 1
#define BRW_CHANNEL_X 0
#define BRW_CHANNEL_Y 1
#define BRW_CHANNEL_Z 2
#define BRW_CHANNEL_W 3
#define BRW_COMPRESSION_NONE 0
#define BRW_COMPRESSION_2NDHALF 1
#define BRW_COMPRESSION_COMPRESSED 2
#define BRW_CONDITIONAL_NONE 0
#define BRW_CONDITIONAL_Z 1
#define BRW_CONDITIONAL_NZ 2
#define BRW_CONDITIONAL_EQ 1 /* Z */
#define BRW_CONDITIONAL_NEQ 2 /* NZ */
#define BRW_CONDITIONAL_G 3
#define BRW_CONDITIONAL_GE 4
#define BRW_CONDITIONAL_L 5
#define BRW_CONDITIONAL_LE 6
#define BRW_CONDITIONAL_C 7
#define BRW_CONDITIONAL_O 8
#define BRW_DEBUG_NONE 0
#define BRW_DEBUG_BREAKPOINT 1
#define BRW_DEPENDENCY_NORMAL 0
#define BRW_DEPENDENCY_NOTCLEARED 1
#define BRW_DEPENDENCY_NOTCHECKED 2
#define BRW_DEPENDENCY_DISABLE 3
#define BRW_EXECUTE_1 0
#define BRW_EXECUTE_2 1
#define BRW_EXECUTE_4 2
#define BRW_EXECUTE_8 3
#define BRW_EXECUTE_16 4
#define BRW_EXECUTE_32 5
#define BRW_HORIZONTAL_STRIDE_0 0
#define BRW_HORIZONTAL_STRIDE_1 1
#define BRW_HORIZONTAL_STRIDE_2 2
#define BRW_HORIZONTAL_STRIDE_4 3
#define BRW_INSTRUCTION_NORMAL 0
#define BRW_INSTRUCTION_SATURATE 1
#define BRW_MASK_ENABLE 0
#define BRW_MASK_DISABLE 1
#define BRW_OPCODE_MOV 1
#define BRW_OPCODE_SEL 2
#define BRW_OPCODE_NOT 4
#define BRW_OPCODE_AND 5
#define BRW_OPCODE_OR 6
#define BRW_OPCODE_XOR 7
#define BRW_OPCODE_SHR 8
#define BRW_OPCODE_SHL 9
#define BRW_OPCODE_RSR 10
#define BRW_OPCODE_RSL 11
#define BRW_OPCODE_ASR 12
#define BRW_OPCODE_CMP 16
#define BRW_OPCODE_JMPI 32
#define BRW_OPCODE_IF 34
#define BRW_OPCODE_IFF 35
#define BRW_OPCODE_ELSE 36
#define BRW_OPCODE_ENDIF 37
#define BRW_OPCODE_DO 38
#define BRW_OPCODE_WHILE 39
#define BRW_OPCODE_BREAK 40
#define BRW_OPCODE_CONTINUE 41
#define BRW_OPCODE_HALT 42
#define BRW_OPCODE_MSAVE 44
#define BRW_OPCODE_MRESTORE 45
#define BRW_OPCODE_PUSH 46
#define BRW_OPCODE_POP 47
#define BRW_OPCODE_WAIT 48
#define BRW_OPCODE_SEND 49
#define BRW_OPCODE_ADD 64
#define BRW_OPCODE_MUL 65
#define BRW_OPCODE_AVG 66
#define BRW_OPCODE_FRC 67
#define BRW_OPCODE_RNDU 68
#define BRW_OPCODE_RNDD 69
#define BRW_OPCODE_RNDE 70
#define BRW_OPCODE_RNDZ 71
#define BRW_OPCODE_MAC 72
#define BRW_OPCODE_MACH 73
#define BRW_OPCODE_LZD 74
#define BRW_OPCODE_SAD2 80
#define BRW_OPCODE_SADA2 81
#define BRW_OPCODE_DP4 84
#define BRW_OPCODE_DPH 85
#define BRW_OPCODE_DP3 86
#define BRW_OPCODE_DP2 87
#define BRW_OPCODE_DPA2 88
#define BRW_OPCODE_LINE 89
#define BRW_OPCODE_NOP 126
#define BRW_PREDICATE_NONE 0
#define BRW_PREDICATE_NORMAL 1
#define BRW_PREDICATE_ALIGN1_ANYV 2
#define BRW_PREDICATE_ALIGN1_ALLV 3
#define BRW_PREDICATE_ALIGN1_ANY2H 4
#define BRW_PREDICATE_ALIGN1_ALL2H 5
#define BRW_PREDICATE_ALIGN1_ANY4H 6
#define BRW_PREDICATE_ALIGN1_ALL4H 7
#define BRW_PREDICATE_ALIGN1_ANY8H 8
#define BRW_PREDICATE_ALIGN1_ALL8H 9
#define BRW_PREDICATE_ALIGN1_ANY16H 10
#define BRW_PREDICATE_ALIGN1_ALL16H 11
#define BRW_PREDICATE_ALIGN16_REPLICATE_X 2
#define BRW_PREDICATE_ALIGN16_REPLICATE_Y 3
#define BRW_PREDICATE_ALIGN16_REPLICATE_Z 4
#define BRW_PREDICATE_ALIGN16_REPLICATE_W 5
#define BRW_PREDICATE_ALIGN16_ANY4H 6
#define BRW_PREDICATE_ALIGN16_ALL4H 7
#define BRW_ARCHITECTURE_REGISTER_FILE 0
#define BRW_GENERAL_REGISTER_FILE 1
#define BRW_MESSAGE_REGISTER_FILE 2
#define BRW_IMMEDIATE_VALUE 3
#define BRW_REGISTER_TYPE_UD 0
#define BRW_REGISTER_TYPE_D 1
#define BRW_REGISTER_TYPE_UW 2
#define BRW_REGISTER_TYPE_W 3
#define BRW_REGISTER_TYPE_UB 4
#define BRW_REGISTER_TYPE_B 5
#define BRW_REGISTER_TYPE_VF 5 /* packed float vector, immediates only? */
#define BRW_REGISTER_TYPE_HF 6
#define BRW_REGISTER_TYPE_V 6 /* packed int vector, immediates only, uword dest only */
#define BRW_REGISTER_TYPE_F 7
#define BRW_ARF_NULL 0x00
#define BRW_ARF_ADDRESS 0x10
#define BRW_ARF_ACCUMULATOR 0x20
#define BRW_ARF_FLAG 0x30
#define BRW_ARF_MASK 0x40
#define BRW_ARF_MASK_STACK 0x50
#define BRW_ARF_MASK_STACK_DEPTH 0x60
#define BRW_ARF_STATE 0x70
#define BRW_ARF_CONTROL 0x80
#define BRW_ARF_NOTIFICATION_COUNT 0x90
#define BRW_ARF_IP 0xA0
#define BRW_AMASK 0
#define BRW_IMASK 1
#define BRW_LMASK 2
#define BRW_CMASK 3
#define BRW_THREAD_NORMAL 0
#define BRW_THREAD_ATOMIC 1
#define BRW_THREAD_SWITCH 2
#define BRW_VERTICAL_STRIDE_0 0
#define BRW_VERTICAL_STRIDE_1 1
#define BRW_VERTICAL_STRIDE_2 2
#define BRW_VERTICAL_STRIDE_4 3
#define BRW_VERTICAL_STRIDE_8 4
#define BRW_VERTICAL_STRIDE_16 5
#define BRW_VERTICAL_STRIDE_32 6
#define BRW_VERTICAL_STRIDE_64 7
#define BRW_VERTICAL_STRIDE_128 8
#define BRW_VERTICAL_STRIDE_256 9
#define BRW_VERTICAL_STRIDE_ONE_DIMENSIONAL 0xF
#define BRW_WIDTH_1 0
#define BRW_WIDTH_2 1
#define BRW_WIDTH_4 2
#define BRW_WIDTH_8 3
#define BRW_WIDTH_16 4
#define BRW_STATELESS_BUFFER_BOUNDARY_1K 0
#define BRW_STATELESS_BUFFER_BOUNDARY_2K 1
#define BRW_STATELESS_BUFFER_BOUNDARY_4K 2
#define BRW_STATELESS_BUFFER_BOUNDARY_8K 3
#define BRW_STATELESS_BUFFER_BOUNDARY_16K 4
#define BRW_STATELESS_BUFFER_BOUNDARY_32K 5
#define BRW_STATELESS_BUFFER_BOUNDARY_64K 6
#define BRW_STATELESS_BUFFER_BOUNDARY_128K 7
#define BRW_STATELESS_BUFFER_BOUNDARY_256K 8
#define BRW_STATELESS_BUFFER_BOUNDARY_512K 9
#define BRW_STATELESS_BUFFER_BOUNDARY_1M 10
#define BRW_STATELESS_BUFFER_BOUNDARY_2M 11
#define BRW_POLYGON_FACING_FRONT 0
#define BRW_POLYGON_FACING_BACK 1
#define BRW_MESSAGE_TARGET_NULL 0
#define BRW_MESSAGE_TARGET_MATH 1
#define BRW_MESSAGE_TARGET_SAMPLER 2
#define BRW_MESSAGE_TARGET_GATEWAY 3
#define BRW_MESSAGE_TARGET_DATAPORT_READ 4
#define BRW_MESSAGE_TARGET_DATAPORT_WRITE 5
#define BRW_MESSAGE_TARGET_URB 6
#define BRW_MESSAGE_TARGET_THREAD_SPAWNER 7
#define BRW_SAMPLER_RETURN_FORMAT_FLOAT32 0
#define BRW_SAMPLER_RETURN_FORMAT_UINT32 2
#define BRW_SAMPLER_RETURN_FORMAT_SINT32 3
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_BIAS 0
#define BRW_SAMPLER_MESSAGE_SIMD8_KILLPIX 1
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_LOD 1
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_LOD 1
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_GRADIENTS 2
#define BRW_SAMPLER_MESSAGE_SIMD8_SAMPLE_GRADIENTS 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_SAMPLE_COMPARE 0
#define BRW_SAMPLER_MESSAGE_SIMD16_SAMPLE_COMPARE 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD8_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD16_RESINFO 2
#define BRW_SAMPLER_MESSAGE_SIMD4X2_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD8_LD 3
#define BRW_SAMPLER_MESSAGE_SIMD16_LD 3
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDLOW 0
#define BRW_DATAPORT_OWORD_BLOCK_1_OWORDHIGH 1
#define BRW_DATAPORT_OWORD_BLOCK_2_OWORDS 2
#define BRW_DATAPORT_OWORD_BLOCK_4_OWORDS 3
#define BRW_DATAPORT_OWORD_BLOCK_8_OWORDS 4
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_1OWORD 0
#define BRW_DATAPORT_OWORD_DUAL_BLOCK_4OWORDS 2
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_8DWORDS 2
#define BRW_DATAPORT_DWORD_SCATTERED_BLOCK_16DWORDS 3
#define BRW_DATAPORT_READ_MESSAGE_OWORD_BLOCK_READ 0
#define BRW_DATAPORT_READ_MESSAGE_OWORD_DUAL_BLOCK_READ 1
#define BRW_DATAPORT_READ_MESSAGE_DWORD_BLOCK_READ 2
#define BRW_DATAPORT_READ_MESSAGE_DWORD_SCATTERED_READ 3
#define BRW_DATAPORT_READ_TARGET_DATA_CACHE 0
#define BRW_DATAPORT_READ_TARGET_RENDER_CACHE 1
#define BRW_DATAPORT_READ_TARGET_SAMPLER_CACHE 2
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE 0
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD16_SINGLE_SOURCE_REPLICATED 1
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN01 2
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_DUAL_SOURCE_SUBSPAN23 3
#define BRW_DATAPORT_RENDER_TARGET_WRITE_SIMD8_SINGLE_SOURCE_SUBSPAN01 4
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_BLOCK_WRITE 0
#define BRW_DATAPORT_WRITE_MESSAGE_OWORD_DUAL_BLOCK_WRITE 1
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_BLOCK_WRITE 2
#define BRW_DATAPORT_WRITE_MESSAGE_DWORD_SCATTERED_WRITE 3
#define BRW_DATAPORT_WRITE_MESSAGE_RENDER_TARGET_WRITE 4
#define BRW_DATAPORT_WRITE_MESSAGE_STREAMED_VERTEX_BUFFER_WRITE 5
#define BRW_DATAPORT_WRITE_MESSAGE_FLUSH_RENDER_CACHE 7
#define BRW_MATH_FUNCTION_INV 1
#define BRW_MATH_FUNCTION_LOG 2
#define BRW_MATH_FUNCTION_EXP 3
#define BRW_MATH_FUNCTION_SQRT 4
#define BRW_MATH_FUNCTION_RSQ 5
#define BRW_MATH_FUNCTION_SIN 6 /* was 7 */
#define BRW_MATH_FUNCTION_COS 7 /* was 8 */
#define BRW_MATH_FUNCTION_SINCOS 8 /* was 6 */
#define BRW_MATH_FUNCTION_TAN 9
#define BRW_MATH_FUNCTION_POW 10
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT_AND_REMAINDER 11
#define BRW_MATH_FUNCTION_INT_DIV_QUOTIENT 12
#define BRW_MATH_FUNCTION_INT_DIV_REMAINDER 13
#define BRW_MATH_INTEGER_UNSIGNED 0
#define BRW_MATH_INTEGER_SIGNED 1
#define BRW_MATH_PRECISION_FULL 0
#define BRW_MATH_PRECISION_PARTIAL 1
#define BRW_MATH_SATURATE_NONE 0
#define BRW_MATH_SATURATE_SATURATE 1
#define BRW_MATH_DATA_VECTOR 0
#define BRW_MATH_DATA_SCALAR 1
#define BRW_URB_OPCODE_WRITE 0
#define BRW_URB_SWIZZLE_NONE 0
#define BRW_URB_SWIZZLE_INTERLEAVE 1
#define BRW_URB_SWIZZLE_TRANSPOSE 2
#define BRW_SCRATCH_SPACE_SIZE_1K 0
#define BRW_SCRATCH_SPACE_SIZE_2K 1
#define BRW_SCRATCH_SPACE_SIZE_4K 2
#define BRW_SCRATCH_SPACE_SIZE_8K 3
#define BRW_SCRATCH_SPACE_SIZE_16K 4
#define BRW_SCRATCH_SPACE_SIZE_32K 5
#define BRW_SCRATCH_SPACE_SIZE_64K 6
#define BRW_SCRATCH_SPACE_SIZE_128K 7
#define BRW_SCRATCH_SPACE_SIZE_256K 8
#define BRW_SCRATCH_SPACE_SIZE_512K 9
#define BRW_SCRATCH_SPACE_SIZE_1M 10
#define BRW_SCRATCH_SPACE_SIZE_2M 11
#define CMD_URB_FENCE 0x6000
#define CMD_CONST_BUFFER_STATE 0x6001
#define CMD_CONST_BUFFER 0x6002
#define CMD_STATE_BASE_ADDRESS 0x6101
#define CMD_STATE_INSN_POINTER 0x6102
#define CMD_PIPELINE_SELECT 0x6104
#define CMD_PIPELINED_STATE_POINTERS 0x7800
#define CMD_BINDING_TABLE_PTRS 0x7801
#define CMD_VERTEX_BUFFER 0x7808
#define CMD_VERTEX_ELEMENT 0x7809
#define CMD_INDEX_BUFFER 0x780a
#define CMD_VF_STATISTICS 0x780b
#define CMD_DRAW_RECT 0x7900
#define CMD_BLEND_CONSTANT_COLOR 0x7901
#define CMD_CHROMA_KEY 0x7904
#define CMD_DEPTH_BUFFER 0x7905
#define CMD_POLY_STIPPLE_OFFSET 0x7906
#define CMD_POLY_STIPPLE_PATTERN 0x7907
#define CMD_LINE_STIPPLE_PATTERN 0x7908
#define CMD_GLOBAL_DEPTH_OFFSET_CLAMP 0x7908
#define CMD_PIPE_CONTROL 0x7a00
#define CMD_3D_PRIM 0x7b00
#define CMD_MI_FLUSH 0x0200
/* Various values from the R0 vertex header:
*/
#define R02_PRIM_END 0x1
#define R02_PRIM_START 0x2
#endif

1340
src/brw_structs.h Normal file
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File diff suppressed because it is too large Load Diff

50
src/common.h
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@ -39,13 +39,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef _INTEL_COMMON_H_
#define _INTEL_COMMON_H_
#ifdef __GNUC__
/* Provide substitutes for gcc's __FUNCTION__ on other compilers */
#ifndef __GNUC__
# if defined(__STDC__) && (__STDC_VERSION__>=199901L) /* C99 */
# define __FUNCTION__ __func__
# else
# define __FUNCTION__ ""
# endif
#endif
#define PFX __FILE__,__LINE__,__FUNCTION__
#define FUNCTION_NAME __FUNCTION__
#else
#define PFX __FILE__,__LINE__,""
#define FUNCTION_NAME ""
#endif
#ifdef I830DEBUG
#define MARKER() ErrorF("\n### %s:%d: >>> %s <<< ###\n\n", \
@ -126,13 +131,17 @@ extern void I830DPRINTF_stub(const char *filename, int line,
#define ADVANCE_LP_RING() do { \
if (ringused > needed) \
ErrorF("%s: ADVANCE_LP_RING: exceeded allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
FatalError("%s: ADVANCE_LP_RING: exceeded allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
else if (ringused < needed) \
FatalError("%s: ADVANCE_LP_RING: under-used allocation %d/%d\n ", \
__FUNCTION__, ringused, needed); \
RecPtr->LpRing->tail = outring; \
RecPtr->LpRing->space -= ringused; \
if (outring & 0x07) \
ErrorF("ADVANCE_LP_RING: " \
"outring (0x%x) isn't on a QWord boundary\n", outring); \
FatalError("%s: ADVANCE_LP_RING: " \
"outring (0x%x) isn't on a QWord boundary\n", \
__FUNCTION__, outring); \
OUTREG(LP_RING + RING_TAIL, outring); \
} while (0)
@ -273,6 +282,26 @@ extern int I810_DEBUG;
#define PCI_CHIP_I945_GM_BRIDGE 0x27A0
#endif
#ifndef PCI_CHIP_I965_G_1
#define PCI_CHIP_I965_G_1 0x2982
#define PCI_CHIP_I965_G_1_BRIDGE 0x2980
#endif
#ifndef PCI_CHIP_I965_Q
#define PCI_CHIP_I965_Q 0x2992
#define PCI_CHIP_I965_Q_BRIDGE 0x2990
#endif
#ifndef PCI_CHIP_I965_G
#define PCI_CHIP_I965_G 0x29A2
#define PCI_CHIP_I965_G_BRIDGE 0x29A0
#endif
#ifndef PCI_CHIP_I946_GZ
#define PCI_CHIP_I946_GZ 0x2972
#define PCI_CHIP_I946_GZ_BRIDGE 0x2970
#endif
#define IS_I810(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I810 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_DC100 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_E)
@ -288,7 +317,8 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_GM)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810))
#define IS_I965G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_G || pI810->PciInfo->chipType == PCI_CHIP_I965_G_1 || pI810->PciInfo->chipType == PCI_CHIP_I965_Q || pI810->PciInfo->chipType == PCI_CHIP_I946_GZ)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810))
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))

4
src/i810.h
View File

@ -64,10 +64,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define I810_VERSION 4000
#define I810_NAME "I810"
#define I810_DRIVER_NAME "i810"
#define I810_MAJOR_VERSION 1
#define I810_MINOR_VERSION 6
#define I810_PATCHLEVEL 0
/* HWMC Surfaces */
#define I810_MAX_SURFACES 7

4
src/i810_dri.h
View File

@ -8,6 +8,10 @@
#define I810_MAX_DRAWABLES 256
#define I810_MAJOR_VERSION 1
#define I810_MINOR_VERSION 6
#define I810_PATCHLEVEL 3
typedef struct {
drm_handle_t regs;
drmSize regsSize;

19
src/i810_driver.c
View File

@ -140,6 +140,10 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I915_GM, "915GM"},
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_I965_G_1, "965G"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{-1, NULL}
};
@ -159,6 +163,10 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@ -324,7 +332,8 @@ const char *I810driSymbols[] = {
"DRICreatePCIBusID",
NULL
};
#endif
#endif /* I830_ONLY */
const char *I810shadowSymbols[] = {
"shadowInit",
@ -378,7 +387,7 @@ static XF86ModuleVersionInfo i810VersRec = {
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
I810_MAJOR_VERSION, I810_MINOR_VERSION, I810_PATCHLEVEL,
INTEL_VERSION_MAJOR, INTEL_VERSION_MINOR, INTEL_VERSION_PATCH,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_VIDEODRV,
@ -407,9 +416,9 @@ i810Setup(pointer module, pointer opts, int *errmaj, int *errmin)
#ifdef XF86DRI
I810drmSymbols,
I810driSymbols,
#endif
I810shadowSymbols,
I810shadowFBSymbols,
#endif
I810vbeSymbols, vbeOptionalSymbols,
I810ddcSymbols, I810int10Symbols, NULL);
@ -584,6 +593,10 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I915_GM:
case PCI_CHIP_I945_G:
case PCI_CHIP_I945_GM:
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_G_1:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */

334
src/i810_reg.h
View File

@ -314,8 +314,6 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define STATE_VAR_UPDATE_DISABLE 0x02
#define PAL_STIP_DISABLE 0x01
#define INST_DONE 0x2090
#define INST_PS 0x20c4
#define MEMMODE 0x20dc
@ -324,6 +322,66 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define IPEIR 0x2088
#define IPEHR 0x208C
#define INST_DONE 0x2090
#define INST_PS 0x20c4
#define IPEIR_I965 0x2064 /* i965 */
#define IPEHR_I965 0x2068 /* i965 */
#define INST_DONE_I965 0x206c
#define INST_PS_I965 0x2070
#define ACTHD 0x2074
#define DMA_FADD_P 0x2078
#define INST_DONE_1 0x207c
#define CACHE_MODE_0 0x2120
#define CACHE_MODE_1 0x2124
#define MI_ARB_STATE 0x20e4
#define WIZ_CTL 0x7c00
#define WIZ_CTL_SINGLE_SUBSPAN (1<<6)
#define WIZ_CTL_IGNORE_STALLS (1<<5)
#define SVG_WORK_CTL 0x7408
#define TS_CTL 0x7e00
#define TS_MUX_ERR_CODE (0<<8)
#define TS_MUX_URB_0 (1<<8)
#define TS_MUX_DISPATCH_ID_0 (10<<8)
#define TS_MUX_ERR_CODE_VALID (15<<8)
#define TS_MUX_TID_0 (16<<8)
#define TS_MUX_EUID_0 (18<<8)
#define TS_MUX_FFID_0 (22<<8)
#define TS_MUX_EOT (26<<8)
#define TS_MUX_SIDEBAND_0 (27<<8)
#define TS_SNAP_ALL_CHILD (1<<2)
#define TS_SNAP_ALL_ROOT (1<<1)
#define TS_SNAP_ENABLE (1<<0)
#define TS_DEBUG_DATA 0x7e0c
#define TD_CTL 0x8000
#define TD_CTL2 0x8004
#define ECOSKPD 0x21d0
#define EXCC 0x2028
/* I965 debug regs:
*/
#define IA_VERTICES_COUNT_QW 0x2310
#define IA_PRIMITIVES_COUNT_QW 0x2318
#define VS_INVOCATION_COUNT_QW 0x2320
#define GS_INVOCATION_COUNT_QW 0x2328
#define GS_PRIMITIVES_COUNT_QW 0x2330
#define CL_INVOCATION_COUNT_QW 0x2338
#define CL_PRIMITIVES_COUNT_QW 0x2340
#define PS_INVOCATION_COUNT_QW 0x2348
#define PS_DEPTH_COUNT_QW 0x2350
#define TIMESTAMP_QW 0x2358
#define CLKCMP_QW 0x2360
/* General error reporting regs, p296
@ -387,6 +445,13 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define FENCE 0x2000
#define FENCE_NR 8
#define FENCE_NEW 0x3000
#define FENCE_NEW_NR 16
#define FENCE_LINEAR 0
#define FENCE_XMAJOR 1
#define FENCE_YMAJOR 2
#define I915G_FENCE_START_MASK 0x0ff00000
#define I830_FENCE_START_MASK 0x07f80000
@ -923,6 +988,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define DSPBPOS 0x7118C
#define DSPBSIZE 0x71190
#define DSPASURF 0x7019C
#define DSPATILEOFF 0x701A4
#define DSPBSURF 0x7119C
#define DSPBTILEOFF 0x711A4
#define VGACNTRL 0x71400
# define VGA_DISP_DISABLE (1 << 31)
# define VGA_2X_MODE (1 << 30)
@ -1022,15 +1093,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define XY_MONO_SRC_BLT_WRITE_ALPHA (1<<21)
#define XY_MONO_SRC_BLT_WRITE_RGB (1<<20)
/* 3d state */
#define STATE3D_FOG_MODE ((3<<29)|(0x1d<<24)|(0x89<<16)|2)
#define FOG_MODE_VERTEX (1<<31)
#define STATE3D_MAP_COORD_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8c<<16))
#define DISABLE_TEX_TRANSFORM (1<<28)
#define TEXTURE_SET(x) (x<<29)
#define STATE3D_RASTERIZATION_RULES ((3<<29)|(0x07<<24))
#define POINT_RASTER_ENABLE (1<<15)
#define POINT_RASTER_OGL (1<<13)
#define STATE3D_VERTEX_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8b<<16))
#define DISABLE_VIEWPORT_TRANSFORM (1<<31)
#define DISABLE_PERSPECTIVE_DIVIDE (1<<29)
@ -1063,7 +1131,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define MI_WRITE_DIRTY_STATE (1<<4)
#define MI_END_SCENE (1<<3)
#define MI_INHIBIT_RENDER_CACHE_FLUSH (1<<2)
#define MI_STATE_INSTRUCTION_CACHE_FLUSH (1<<1)
#define MI_INVALIDATE_MAP_CACHE (1<<0)
/* broadwater flush bits */
#define BRW_MI_GLOBAL_SNAPSHOT_RESET (1 << 3)
/* Noop */
#define MI_NOOP 0x00
@ -1077,6 +1148,244 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define ENABLE_FOG_CONST (1<<24)
#define ENABLE_FOG_DENSITY (1<<23)
/*
* New regs for broadwater -- we need to split this file up sensibly somehow.
*/
#define BRW_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
((Pipeline) << 27) | \
((Opcode) << 24) | \
((Subopcode) << 16))
#define BRW_URB_FENCE BRW_3D(0, 0, 0)
#define BRW_CS_URB_STATE BRW_3D(0, 0, 1)
#define BRW_CONSTANT_BUFFER BRW_3D(0, 0, 2)
#define BRW_STATE_PREFETCH BRW_3D(0, 0, 3)
#define BRW_STATE_BASE_ADDRESS BRW_3D(0, 1, 1)
#define BRW_STATE_SIP BRW_3D(0, 1, 2)
#define BRW_PIPELINE_SELECT BRW_3D(0, 1, 4)
#define BRW_MEDIA_STATE_POINTERS BRW_3D(2, 0, 0)
#define BRW_MEDIA_OBJECT BRW_3D(2, 1, 0)
#define BRW_3DSTATE_PIPELINED_POINTERS BRW_3D(3, 0, 0)
#define BRW_3DSTATE_BINDING_TABLE_POINTERS BRW_3D(3, 0, 1)
#define BRW_3DSTATE_VERTEX_BUFFERS BRW_3D(3, 0, 8)
#define BRW_3DSTATE_VERTEX_ELEMENTS BRW_3D(3, 0, 9)
#define BRW_3DSTATE_INDEX_BUFFER BRW_3D(3, 0, 0xa)
#define BRW_3DSTATE_VF_STATISTICS BRW_3D(3, 0, 0xb)
#define BRW_3DSTATE_DRAWING_RECTANGLE BRW_3D(3, 1, 0)
#define BRW_3DSTATE_CONSTANT_COLOR BRW_3D(3, 1, 1)
#define BRW_3DSTATE_SAMPLER_PALETTE_LOAD BRW_3D(3, 1, 2)
#define BRW_3DSTATE_CHROMA_KEY BRW_3D(3, 1, 4)
#define BRW_3DSTATE_DEPTH_BUFFER BRW_3D(3, 1, 5)
#define BRW_3DSTATE_POLY_STIPPLE_OFFSET BRW_3D(3, 1, 6)
#define BRW_3DSTATE_POLY_STIPPLE_PATTERN BRW_3D(3, 1, 7)
#define BRW_3DSTATE_LINE_STIPPLE BRW_3D(3, 1, 8)
#define BRW_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP BRW_3D(3, 1, 9)
/* These two are BLC and CTG only, not BW or CL */
#define BRW_3DSTATE_AA_LINE_PARAMS BRW_3D(3, 1, 0xa)
#define BRW_3DSTATE_GS_SVB_INDEX BRW_3D(3, 1, 0xb)
#define BRW_PIPE_CONTROL BRW_3D(3, 2, 0)
#define BRW_3DPRIMITIVE BRW_3D(3, 3, 0)
#define PIPELINE_SELECT_3D 0
#define PIPELINE_SELECT_MEDIA 1
#define UF0_CS_REALLOC (1 << 13)
#define UF0_VFE_REALLOC (1 << 12)
#define UF0_SF_REALLOC (1 << 11)
#define UF0_CLIP_REALLOC (1 << 10)
#define UF0_GS_REALLOC (1 << 9)
#define UF0_VS_REALLOC (1 << 8)
#define UF1_CLIP_FENCE_SHIFT 20
#define UF1_GS_FENCE_SHIFT 10
#define UF1_VS_FENCE_SHIFT 0
#define UF2_CS_FENCE_SHIFT 20
#define UF2_VFE_FENCE_SHIFT 10
#define UF2_SF_FENCE_SHIFT 0
/* for BRW_STATE_BASE_ADDRESS */
#define BASE_ADDRESS_MODIFY (1 << 0)
/* for BRW_3DSTATE_PIPELINED_POINTERS */
#define BRW_GS_DISABLE 0
#define BRW_GS_ENABLE 1
#define BRW_CLIP_DISABLE 0
#define BRW_CLIP_ENABLE 1
/* for BRW_PIPE_CONTROL */
#define BRW_PIPE_CONTROL_NOWRITE (0 << 14)
#define BRW_PIPE_CONTROL_WRITE_QWORD (1 << 14)
#define BRW_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
#define BRW_PIPE_CONTROL_WRITE_TIME (3 << 14)
#define BRW_PIPE_CONTROL_DEPTH_STALL (1 << 13)
#define BRW_PIPE_CONTROL_WC_FLUSH (1 << 12)
#define BRW_PIPE_CONTROL_IS_FLUSH (1 << 11)
#define BRW_PIPE_CONTROL_NOTIFY_ENABLE (1 << 8)
#define BRW_PIPE_CONTROL_GLOBAL_GTT (1 << 2)
#define BRW_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
/* VERTEX_BUFFER_STATE Structure */
#define VB0_BUFFER_INDEX_SHIFT 27
#define VB0_VERTEXDATA (0 << 26)
#define VB0_INSTANCEDATA (1 << 26)
#define VB0_BUFFER_PITCH_SHIFT 0
/* VERTEX_ELEMENT_STATE Structure */
#define VE0_VERTEX_BUFFER_INDEX_SHIFT 27
#define VE0_VALID (1 << 26)
#define VE0_FORMAT_SHIFT 16
#define VE0_OFFSET_SHIFT 0
#define VE1_VFCOMPONENT_0_SHIFT 28
#define VE1_VFCOMPONENT_1_SHIFT 24
#define VE1_VFCOMPONENT_2_SHIFT 20
#define VE1_VFCOMPONENT_3_SHIFT 16
#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0
/* 3DPRIMITIVE bits */
#define BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
#define BRW_3DPRIMITIVE_VERTEX_RANDOM (1 << 15)
/* Primitive types are in brw_defines.h */
#define BRW_3DPRIMITIVE_TOPOLOGY_SHIFT 10
#define BRW_SVG_CTL 0x7400
#define BRW_SVG_CTL_GS_BA (0 << 8)
#define BRW_SVG_CTL_SS_BA (1 << 8)
#define BRW_SVG_CTL_IO_BA (2 << 8)
#define BRW_SVG_CTL_GS_AUB (3 << 8)
#define BRW_SVG_CTL_IO_AUB (4 << 8)
#define BRW_SVG_CTL_SIP (5 << 8)
#define BRW_SVG_RDATA 0x7404
#define BRW_SVG_WORK_CTL 0x7408
#define BRW_VF_CTL 0x7500
#define BRW_VF_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_THREADID (0 << 8)
#define BRW_VF_CTL_SNAPSHOT_MUX_SELECT_VF_DEBUG (1 << 8)
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_SEQUENCE (0 << 4)
#define BRW_VF_CTL_SNAPSHOT_TYPE_VERTEX_INDEX (1 << 4)
#define BRW_VF_CTL_SKIP_INITIAL_PRIMITIVES (1 << 3)
#define BRW_VF_CTL_MAX_PRIMITIVES_LIMIT_ENABLE (1 << 2)
#define BRW_VF_CTL_VERTEX_RANGE_LIMIT_ENABLE (1 << 1)
#define BRW_VF_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_VF_STRG_VAL 0x7504
#define BRW_VF_STR_VL_OVR 0x7508
#define BRW_VF_VC_OVR 0x750c
#define BRW_VF_STR_PSKIP 0x7510
#define BRW_VF_MAX_PRIM 0x7514
#define BRW_VF_RDATA 0x7518
#define BRW_VS_CTL 0x7600
#define BRW_VS_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_0 (0 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VERTEX_1 (1 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VALID_COUNT (2 << 8)
#define BRW_VS_CTL_SNAPSHOT_MUX_VS_KERNEL_POINTER (3 << 8)
#define BRW_VS_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_VS_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_VS_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_VS_STRG_VAL 0x7604
#define BRW_VS_RDATA 0x7608
#define BRW_SF_CTL 0x7b00
#define BRW_SF_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_FF_ID (0 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_0_REL_COUNT (1 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_FF_ID (2 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_1_REL_COUNT (3 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_FF_ID (4 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_2_REL_COUNT (5 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_VERTEX_COUNT (6 << 8)
#define BRW_SF_CTL_SNAPSHOT_MUX_SF_KERNEL_POINTER (7 << 8)
#define BRW_SF_CTL_MIN_MAX_PRIMITIVE_RANGE_ENABLE (1 << 4)
#define BRW_SF_CTL_DEBUG_CLIP_RECTANGLE_ENABLE (1 << 3)
#define BRW_SF_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_SF_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_SF_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_SF_STRG_VAL 0x7b04
#define BRW_SF_RDATA 0x7b18
#define BRW_WIZ_CTL 0x7c00
#define BRW_WIZ_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_WIZ_CTL_SUBSPAN_INSTANCE_SHIFT 16
#define BRW_WIZ_CTL_SNAPSHOT_MUX_WIZ_KERNEL_POINTER (0 << 8)
#define BRW_WIZ_CTL_SNAPSHOT_MUX_SUBSPAN_INSTANCE (1 << 8)
#define BRW_WIZ_CTL_SNAPSHOT_MUX_PRIMITIVE_SEQUENCE (2 << 8)
#define BRW_WIZ_CTL_SINGLE_SUBSPAN_DISPATCH (1 << 6)
#define BRW_WIZ_CTL_IGNORE_COLOR_SCOREBOARD_STALLS (1 << 5)
#define BRW_WIZ_CTL_ENABLE_SUBSPAN_INSTANCE_COMPARE (1 << 4)
#define BRW_WIZ_CTL_USE_UPSTREAM_SNAPSHOT_FLAG (1 << 3)
#define BRW_WIZ_CTL_SNAPSHOT_ALL_THREADS (1 << 2)
#define BRW_WIZ_CTL_THREAD_SNAPSHOT_ENABLE (1 << 1)
#define BRW_WIZ_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_WIZ_STRG_VAL 0x7c04
#define BRW_WIZ_RDATA 0x7c18
#define BRW_TS_CTL 0x7e00
#define BRW_TS_CTL_SNAPSHOT_COMPLETE (1 << 31)
#define BRW_TS_CTL_SNAPSHOT_MESSAGE_ERROR (0 << 8)
#define BRW_TS_CTL_SNAPSHOT_INTERFACE_DESCRIPTOR (3 << 8)
#define BRW_TS_CTL_SNAPSHOT_ALL_CHILD_THREADS (1 << 2)
#define BRW_TS_CTL_SNAPSHOT_ALL_ROOT_THREADS (1 << 1)
#define BRW_TS_CTL_SNAPSHOT_ENABLE (1 << 0)
#define BRW_TS_STRG_VAL 0x7e04
#define BRW_TS_RDATA 0x7e08
#define BRW_TD_CTL 0x8000
#define BRW_TD_CTL_MUX_SHIFT 8
#define BRW_TD_CTL_EXTERNAL_HALT_R0_DEBUG_MATCH (1 << 7)
#define BRW_TD_CTL_FORCE_EXTERNAL_HALT (1 << 6)
#define BRW_TD_CTL_EXCEPTION_MASK_OVERRIDE (1 << 5)
#define BRW_TD_CTL_FORCE_THREAD_BREAKPOINT_ENABLE (1 << 4)
#define BRW_TD_CTL_BREAKPOINT_ENABLE (1 << 2)
#define BRW_TD_CTL2 0x8004
#define BRW_TD_CTL2_ILLEGAL_OPCODE_EXCEPTION_OVERRIDE (1 << 28)
#define BRW_TD_CTL2_MASKSTACK_EXCEPTION_OVERRIDE (1 << 26)
#define BRW_TD_CTL2_SOFTWARE_EXCEPTION_OVERRIDE (1 << 25)
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_SHIFT 16
#define BRW_TD_CTL2_ACTIVE_THREAD_LIMIT_ENABLE (1 << 8)
#define BRW_TD_CTL2_THREAD_SPAWNER_EXECUTION_MASK_ENABLE (1 << 7)
#define BRW_TD_CTL2_WIZ_EXECUTION_MASK_ENABLE (1 << 6)
#define BRW_TD_CTL2_SF_EXECUTION_MASK_ENABLE (1 << 5)
#define BRW_TD_CTL2_CLIPPER_EXECUTION_MASK_ENABLE (1 << 4)
#define BRW_TD_CTL2_GS_EXECUTION_MASK_ENABLE (1 << 3)
#define BRW_TD_CTL2_VS_EXECUTION_MASK_ENABLE (1 << 0)
#define BRW_TD_VF_VS_EMSK 0x8008
#define BRW_TD_GS_EMSK 0x800c
#define BRW_TD_CLIP_EMSK 0x8010
#define BRW_TD_SF_EMSK 0x8014
#define BRW_TD_WIZ_EMSK 0x8018
#define BRW_TD_0_6_EHTRG_VAL 0x801c
#define BRW_TD_0_7_EHTRG_VAL 0x8020
#define BRW_TD_0_6_EHTRG_MSK 0x8024
#define BRW_TD_0_7_EHTRG_MSK 0x8028
#define BRW_TD_RDATA 0x802c
#define BRW_TD_TS_EMSK 0x8030
#define BRW_EU_CTL 0x8800
#define BRW_EU_CTL_SELECT_SHIFT 16
#define BRW_EU_CTL_DATA_MUX_SHIFT 8
#define BRW_EU_ATT_0 0x8810
#define BRW_EU_ATT_1 0x8814
#define BRW_EU_ATT_DATA_0 0x8820
#define BRW_EU_ATT_DATA_1 0x8824
#define BRW_EU_ATT_CLR_0 0x8830
#define BRW_EU_ATT_CLR_1 0x8834
#define BRW_EU_RDATA 0x8840
/* End regs for broadwater */
#define MAX_DISPLAY_PIPES 2
@ -1085,12 +1394,11 @@ typedef enum {
TvIndex,
DfpIndex,
LfpIndex,
Crt2Index,
Tv2Index,
Dfp2Index,
UnknownIndex,
Unknown2Index,
NumDisplayTypes,
NumKnownDisplayTypes = UnknownIndex
Lfp2Index,
NumDisplayTypes
} DisplayType;
/* What's connected to the pipes (as reported by the BIOS) */
@ -1099,10 +1407,10 @@ typedef enum {
#define PIPE_TV_ACTIVE (1 << TvIndex)
#define PIPE_DFP_ACTIVE (1 << DfpIndex)
#define PIPE_LCD_ACTIVE (1 << LfpIndex)
#define PIPE_CRT2_ACTIVE (1 << Crt2Index)
#define PIPE_TV2_ACTIVE (1 << Tv2Index)
#define PIPE_DFP2_ACTIVE (1 << Dfp2Index)
#define PIPE_UNKNOWN_ACTIVE ((1 << UnknownIndex) | \
(1 << Unknown2Index))
#define PIPE_LCD2_ACTIVE (1 << Lfp2Index)
#define PIPE_SIZED_DISP_MASK (PIPE_DFP_ACTIVE | \
PIPE_LCD_ACTIVE | \

25
src/i830.h
View File

@ -47,6 +47,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifndef _I830_H_
#define _I830_H_
#include "xf86_OSproc.h"
#include "compiler.h"
#include "xf86PciInfo.h"
#include "xf86Pci.h"
@ -73,6 +74,10 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i2c_vid.h"
/* I830 Video support */
#define NEED_REPLIES /* ? */
#define EXTENSION_PROC_ARGS void *
#include "extnsionst.h" /* required */
#include <X11/extensions/panoramiXproto.h> /* required */
/*
* The mode handling is based upon the VESA driver written by
@ -151,7 +156,7 @@ typedef struct {
} I830RingBuffer;
typedef struct {
unsigned int Fence[8];
unsigned int Fence[FENCE_NEW_NR * 2];
} I830RegRec, *I830RegPtr;
typedef struct {
@ -296,7 +301,6 @@ typedef struct _I830Rec {
I830MemRange LinearMem;
#endif
unsigned long LinearAlloc;
XF86ModReqInfo shadowReq; /* to test for later libshadow */
I830MemRange RotatedMem;
I830MemRange RotatedMem2;
@ -307,14 +311,20 @@ typedef struct _I830Rec {
CreateScreenResourcesProcPtr CreateScreenResources;
int *used3D;
I830MemRange ContextMem;
#ifdef XF86DRI
I830MemRange BackBuffer;
I830MemRange DepthBuffer;
I830MemRange TexMem;
int TexGranularity;
I830MemRange ContextMem;
int drmMinor;
Bool have3DWindows;
unsigned int front_tiled;
unsigned int back_tiled;
unsigned int depth_tiled;
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
#endif
Bool NeedRingBufferLow;
@ -474,6 +484,7 @@ typedef struct _I830Rec {
CARD32 saveDSPASIZE;
CARD32 saveDSPAPOS;
CARD32 saveDSPABASE;
CARD32 saveDSPASURF;
CARD32 saveFPB0;
CARD32 saveFPB1;
CARD32 saveDPLL_B;
@ -487,6 +498,7 @@ typedef struct _I830Rec {
CARD32 saveDSPBSIZE;
CARD32 saveDSPBPOS;
CARD32 saveDSPBBASE;
CARD32 saveDSPBSURF;
CARD32 saveVCLK_DIVISOR_VGA0;
CARD32 saveVCLK_DIVISOR_VGA1;
CARD32 saveVCLK_POST_DIV;
@ -519,11 +531,14 @@ extern int I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis);
extern void I830SetPIOAccess(I830Ptr pI830);
extern void I830SetMMIOAccess(I830Ptr pI830);
extern void I830PrintErrorState(ScrnInfoPtr pScrn);
extern void I965PrintErrorState(ScrnInfoPtr pScrn);
extern void I830Sync(ScrnInfoPtr pScrn);
extern void I830InitHWCursor(ScrnInfoPtr pScrn);
extern void I830SetPipeCursor (ScrnInfoPtr pScrn, int pipe, Bool force);
extern Bool I830CursorInit(ScreenPtr pScreen);
extern void IntelEmitInvarientState(ScrnInfoPtr pScrn);
extern void I830EmitInvarientState(ScrnInfoPtr pScrn);
extern void I915EmitInvarientState(ScrnInfoPtr pScrn);
extern void I830SelectBuffer(ScrnInfoPtr pScrn, int buffer);
extern void I830RefreshRing(ScrnInfoPtr pScrn);
@ -578,8 +593,8 @@ extern long I830GetExcessMemoryAllocations(ScrnInfoPtr pScrn);
extern Bool I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags);
extern Bool I830DoPoolAllocation(ScrnInfoPtr pScrn, I830MemPool *pool);
extern Bool I830FixupOffsets(ScrnInfoPtr pScrn);
extern Bool I830BindGARTMemory(ScrnInfoPtr pScrn);
extern Bool I830UnbindGARTMemory(ScrnInfoPtr pScrn);
extern Bool I830BindAGPMemory(ScrnInfoPtr pScrn);
extern Bool I830UnbindAGPMemory(ScrnInfoPtr pScrn);
extern unsigned long I830AllocVidMem(ScrnInfoPtr pScrn, I830MemRange *result,
I830MemPool *pool, long size,
unsigned long alignment, int flags);

131
src/i830_3d.c Normal file
View File

@ -0,0 +1,131 @@
/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i830_reg.h"
#define CMD_3D (0x3<<29)
void I830EmitInvarientState( ScrnInfoPtr pScrn )
{
I830Ptr pI830 = I830PTR(pScrn);
BEGIN_LP_RING(38);
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(0));
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(1));
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(2));
OUT_RING(_3DSTATE_MAP_CUBE | MAP_UNIT(3));
OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_RING(0);
OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
OUT_RING(0);
OUT_RING(_3DSTATE_DFLT_Z_CMD);
OUT_RING(0);
OUT_RING(_3DSTATE_FOG_MODE_CMD);
OUT_RING(FOGFUNC_ENABLE |
FOG_LINEAR_CONST |
FOGSRC_INDEX_Z |
ENABLE_FOG_DENSITY);
OUT_RING(0);
OUT_RING(0);
OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(0) |
DISABLE_TEX_STREAM_BUMP |
ENABLE_TEX_STREAM_COORD_SET |
TEX_STREAM_COORD_SET(0) |
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(0));
OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(1) |
DISABLE_TEX_STREAM_BUMP |
ENABLE_TEX_STREAM_COORD_SET |
TEX_STREAM_COORD_SET(1) |
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(1));
OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(2) |
DISABLE_TEX_STREAM_BUMP |
ENABLE_TEX_STREAM_COORD_SET |
TEX_STREAM_COORD_SET(2) |
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(2));
OUT_RING(_3DSTATE_MAP_TEX_STREAM_CMD |
MAP_UNIT(3) |
DISABLE_TEX_STREAM_BUMP |
ENABLE_TEX_STREAM_COORD_SET |
TEX_STREAM_COORD_SET(3) |
ENABLE_TEX_STREAM_MAP_IDX | TEX_STREAM_MAP_IDX(3));
OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(0));
OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(1));
OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(2));
OUT_RING(_3DSTATE_MAP_COORD_TRANSFORM);
OUT_RING(DISABLE_TEX_TRANSFORM | TEXTURE_SET(3));
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
ENABLE_TRI_STRIP_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
TRI_STRIP_PROVOKE_VRTX(2));
OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_RING(0);
OUT_RING(0);
OUT_RING(_3DSTATE_VERTEX_TRANSFORM);
OUT_RING(DISABLE_VIEWPORT_TRANSFORM | DISABLE_PERSPECTIVE_DIVIDE);
OUT_RING(_3DSTATE_W_STATE_CMD);
OUT_RING(MAGIC_W_STATE_DWORD1);
OUT_RING(0x3f800000 /* 1.0 in IEEE float */ );
OUT_RING(_3DSTATE_COLOR_FACTOR_CMD);
OUT_RING(0x80808080); /* .5 required in alpha for GL_DOT3_RGBA_EXT */
ADVANCE_LP_RING();
}

79
src/i830_accel.c
View File

@ -133,6 +133,7 @@ void
I830Sync(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
ErrorF("I830Sync\n");
@ -147,13 +148,17 @@ I830Sync(ScrnInfoPtr pScrn)
if (pI830->entityPrivate && !pI830->entityPrivate->RingRunning) return;
if (IS_I965G(pI830))
flags = 0;
/* Send a flush instruction and then wait till the ring is empty.
* This is stronger than waiting for the blitter to finish as it also
* flushes the internal graphics caches.
*/
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@ -168,9 +173,13 @@ void
I830EmitFlush(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (IS_I965G(pI830))
flags = 0;
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
@ -386,6 +395,32 @@ I830AccelInit(ScreenPtr pScreen)
return XAAInit(pScreen, infoPtr);
}
#ifdef XF86DRI
static unsigned int
CheckTiling(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = 0;
/* Check tiling */
if (IS_I965G(pI830)) {
if (pI830->bufferOffset == pScrn->fbOffset && pI830->front_tiled == FENCE_XMAJOR)
tiled = 1;
if (pI830->bufferOffset == pI830->RotatedMem.Start && pI830->rotated_tiled == FENCE_XMAJOR)
tiled = 1;
if (pI830->bufferOffset == pI830->BackBuffer.Start && pI830->back_tiled == FENCE_XMAJOR)
tiled = 1;
/* not really supported as it's always YMajor tiled */
if (pI830->bufferOffset == pI830->DepthBuffer.Start && pI830->depth_tiled == FENCE_XMAJOR)
tiled = 1;
}
return tiled;
}
#else
#define CheckTiling(pScrn) 0
#endif
void
I830SetupForSolidFill(ScrnInfoPtr pScrn, int color, int rop,
unsigned int planemask)
@ -439,6 +474,9 @@ I830SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y, int w, int h)
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
void
@ -473,6 +511,7 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
{
I830Ptr pI830 = I830PTR(pScrn);
int dst_x2, dst_y2;
unsigned int tiled = CheckTiling(pScrn);
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
ErrorF("I830SubsequentScreenToScreenCopy %d,%d - %d,%d %dx%d\n",
@ -481,14 +520,18 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
dst_x2 = dst_x1 + w;
dst_y2 = dst_y1 + h;
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(8);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
XY_SRC_COPY_BLT_WRITE_RGB);
XY_SRC_COPY_BLT_WRITE_RGB | tiled << 15 | tiled << 11);
} else {
OUT_RING(XY_SRC_COPY_BLT_CMD);
OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 15 | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING((dst_y1 << 16) | (dst_x1 & 0xffff));
@ -500,6 +543,9 @@ I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int src_x1, int src_y1,
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
static void
@ -541,6 +587,7 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
{
I830Ptr pI830 = I830PTR(pScrn);
int x1, x2, y1, y2;
unsigned int tiled = CheckTiling(pScrn);
x1 = x;
x2 = x + w;
@ -550,16 +597,22 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
ErrorF("I830SubsequentMono8x8PatternFillRect\n");
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(10);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_MONO_PAT_BLT_CMD | XY_MONO_PAT_BLT_WRITE_ALPHA |
XY_MONO_PAT_BLT_WRITE_RGB |
tiled << 11 |
((patty << 8) & XY_MONO_PAT_VERT_SEED) |
((pattx << 12) & XY_MONO_PAT_HORT_SEED));
} else {
OUT_RING(XY_MONO_PAT_BLT_CMD |
tiled << 11 |
((patty << 8) & XY_MONO_PAT_VERT_SEED) |
((pattx << 12) & XY_MONO_PAT_HORT_SEED));
}
@ -574,6 +627,9 @@ I830SubsequentMono8x8PatternFillRect(ScrnInfoPtr pScrn, int pattx, int patty,
OUT_RING(0);
ADVANCE_LP_RING();
}
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
static void
@ -649,6 +705,7 @@ static void
I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = CheckTiling(pScrn);
if (pI830->init == 0) {
pI830->BR[12] = (pI830->AccelInfoRec->ScanlineColorExpandBuffers[0] -
@ -666,14 +723,19 @@ I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
ErrorF("I830SubsequentColorExpandScanline %d (addr %x)\n",
bufno, pI830->BR[12]);
if (tiled)
pI830->BR[13] = ((pI830->BR[13] & 0xFFFF) >> 2) |
(pI830->BR[13] & 0xFFFF0000);
{
BEGIN_LP_RING(8);
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_MONO_SRC_BLT_CMD | XY_MONO_SRC_BLT_WRITE_ALPHA |
tiled << 11 |
XY_MONO_SRC_BLT_WRITE_RGB);
} else {
OUT_RING(XY_MONO_SRC_BLT_CMD);
OUT_RING(XY_MONO_SRC_BLT_CMD | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING(0); /* x1 = 0, y1 = 0 */
@ -690,6 +752,9 @@ I830SubsequentColorExpandScanline(ScrnInfoPtr pScrn, int bufno)
*/
pI830->BR[9] += pScrn->displayWidth * pI830->cpp;
I830GetNextScanlineColorExpandBuffer(pScrn);
if (IS_I965G(pI830))
I830EmitFlush(pScrn);
}
#if DO_SCANLINE_IMAGE_WRITE
@ -741,6 +806,7 @@ static void
I830SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned int tiled = CheckTiling(pScrn);
if (pI830->init == 0) {
pI830->BR[12] = (pI830->AccelInfoRec->ScanlineColorExpandBuffers[0] -
@ -763,9 +829,10 @@ I830SubsequentImageWriteScanline(ScrnInfoPtr pScrn, int bufno)
if (pScrn->bitsPerPixel == 32) {
OUT_RING(XY_SRC_COPY_BLT_CMD | XY_SRC_COPY_BLT_WRITE_ALPHA |
tiled << 11 |
XY_SRC_COPY_BLT_WRITE_RGB);
} else {
OUT_RING(XY_SRC_COPY_BLT_CMD);
OUT_RING(XY_SRC_COPY_BLT_CMD | tiled << 11);
}
OUT_RING(pI830->BR[13]);
OUT_RING(0); /* x1 = 0, y1 = 0 */

8
src/i830_common.h
View File

@ -84,7 +84,7 @@ typedef struct {
drmTextureRegion texList[I830_NR_TEX_REGIONS+1];
int last_upload; /* last time texture was uploaded */
int last_enqueue; /* last time a buffer was enqueued */
int last_dispatch; /* age of the most recently dispatched buffer */
volatile int last_dispatch; /* age of the most recently dispatched buffer */
int ctxOwner; /* last context to upload state */
int texAge;
int pf_enabled; /* is pageflipping allowed? */
@ -115,6 +115,12 @@ typedef struct {
int rotated_size;
int rotated_pitch;
int virtualX, virtualY;
unsigned int front_tiled;
unsigned int back_tiled;
unsigned int depth_tiled;
unsigned int rotated_tiled;
unsigned int rotated2_tiled;
} drmI830Sarea;
/* Flags for perf_boxes

70
src/i830_cursor.c
View File

@ -116,10 +116,17 @@ I830SetPipeCursor (ScrnInfoPtr pScrn, int pipe, Bool force)
temp |= (pipe << 28); /* Connect to correct pipe */
/* Need to set mode, then address. */
OUTREG(cursor_control, temp);
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Start);
else
OUTREG(cursor_base, pI830->CursorMem->Start);
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_FORMAT_MASK);
@ -158,10 +165,17 @@ I830SetPipeCursor (ScrnInfoPtr pScrn, int pipe, Bool force)
temp |= CURSOR_MODE_DISABLE;
OUTREG(cursor_control, temp);
/* This is needed to flush the above change. */
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Start);
else
OUTREG(cursor_base, pI830->CursorMem->Start);
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_ENABLE|CURSOR_GAMMA_ENABLE);
@ -190,20 +204,33 @@ I830InitHWCursor(ScrnInfoPtr pScrn)
temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE |
MCURSOR_MEM_TYPE_LOCAL |
MCURSOR_PIPE_SELECT);
temp |= CURSOR_MODE_DISABLE;
temp |= (i << 28);
if (pI830->CursorIsARGB)
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_MODE_64_4C_AX;
/* Need to set control, then address. */
OUTREG(cursor_control, temp);
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Physical);
else
OUTREG(cursor_base, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(cursor_base, pI830->CursorMemARGB->Start);
else
OUTREG(cursor_base, pI830->CursorMem->Start);
}
}
} else {
temp = INREG(CURSOR_CONTROL);
temp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
CURSOR_ENABLE | CURSOR_STRIDE_MASK);
temp |= (CURSOR_FORMAT_3C);
if (pI830->CursorIsARGB)
temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_FORMAT_3C;
/* This initialises the format and leave the cursor disabled. */
OUTREG(CURSOR_CONTROL, temp);
/* Need to set address and size after disabling. */
@ -532,10 +559,17 @@ I830SetCursorPosition(ScrnInfoPtr pScrn, int x, int y)
/* have to upload the base for the new position */
if (IS_I9XX(pI830)) {
int base = pipe == 0 ? CURSOR_A_BASE : CURSOR_B_BASE;
if (pI830->CursorIsARGB)
OUTREG(base, pI830->CursorMemARGB->Physical);
else
OUTREG(base, pI830->CursorMem->Physical);
if (pI830->CursorNeedsPhysical) {
if (pI830->CursorIsARGB)
OUTREG(base, pI830->CursorMemARGB->Physical);
else
OUTREG(base, pI830->CursorMem->Physical);
} else {
if (pI830->CursorIsARGB)
OUTREG(base, pI830->CursorMemARGB->Start);
else
OUTREG(base, pI830->CursorMem->Start);
}
}
}
}

19
src/i830_dga.c
View File

@ -253,12 +253,25 @@ static void
I830_Sync(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
MARKER();
if (pI830->AccelInfoRec) {
(*pI830->AccelInfoRec->Sync) (pScrn);
}
if (pI830->noAccel)
return;
if (IS_I965G(pI830))
flags = 0;
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | flags);
OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
I830WaitLpRing(pScrn, pI830->LpRing->mem.Size - 8, 0);
pI830->LpRing->space = pI830->LpRing->mem.Size - 8;
pI830->nextColorExpandBuf = 0;
}
static void

13
src/i830_display.c
View File

@ -238,6 +238,8 @@ i830PipeSetBase(ScrnInfoPtr pScrn, int pipe, int x, int y)
{
I830Ptr pI830 = I830PTR(pScrn);
unsigned long Start;
int dspbase = (pipe == 0 ? DSPABASE : DSPBBASE);
int dspsurf = (pipe == 0 ? DSPASURF : DSPBSURF);
if (I830IsPrimary(pScrn))
Start = pI830->FrontBuffer.Start;
@ -246,10 +248,13 @@ i830PipeSetBase(ScrnInfoPtr pScrn, int pipe, int x, int y)
Start = pI8301->FrontBuffer2.Start;
}
if (pipe == 0)
OUTREG(DSPABASE, Start + ((y * pScrn->displayWidth + x) * pI830->cpp));
else
OUTREG(DSPBBASE, Start + ((y * pScrn->displayWidth + x) * pI830->cpp));
if (IS_I965G(pI830)) {
OUTREG(dspbase, 0);
OUTREG(dspsurf, Start + ((y * pScrn->displayWidth + x) * pI830->cpp));
} else {
OUTREG(dspbase, Start + ((y * pScrn->displayWidth + x) * pI830->cpp));
}
pI830->pipeX[pipe] = x;
pI830->pipeY[pipe] = y;
}

139
src/i830_dri.c
View File

@ -81,8 +81,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830.h"
#include "i830_dri.h"
#include "dristruct.h"
static char I830KernelDriverName[] = "i915";
static char I830ClientDriverName[] = "i915";
static char I965ClientDriverName[] = "i965";
static Bool I830InitVisualConfigs(ScreenPtr pScreen);
static Bool I830CreateContext(ScreenPtr pScreen, VisualPtr visual,
@ -424,11 +427,13 @@ I830CheckDRIAvailable(ScrnInfoPtr pScrn)
* for known symbols in each module. */
if (!xf86LoaderCheckSymbol("GlxSetVisualConfigs"))
return FALSE;
if (!xf86LoaderCheckSymbol("DRIScreenInit"))
return FALSE;
if (!xf86LoaderCheckSymbol("drmAvailable"))
return FALSE;
if (!xf86LoaderCheckSymbol("DRIQueryVersion")) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] %s failed (libdri.a too old)\n", "I830DRIScreenInit");
"[dri] %s failed (libdri.a too old)\n", "I830CheckDRIAvailable");
return FALSE;
}
@ -440,10 +445,10 @@ I830CheckDRIAvailable(ScrnInfoPtr pScrn)
if (major != DRIINFO_MAJOR_VERSION || minor < DRIINFO_MINOR_VERSION) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[dri] %s failed because of a version mismatch.\n"
"[dri] libdri version is %d.%d.%d bug version %d.%d.x is needed.\n"
"[dri] libDRI version is %d.%d.%d but version %d.%d.x is needed.\n"
"[dri] Disabling DRI.\n",
"I830DRIScreenInit", major, minor, patch,
DRIINFO_MAJOR_VERSION, DRIINFO_MINOR_VERSION);
"I830CheckDRIAvailable", major, minor, patch,
DRIINFO_MAJOR_VERSION, DRIINFO_MINOR_VERSION);
return FALSE;
}
}
@ -475,7 +480,11 @@ I830DRIScreenInit(ScreenPtr pScreen)
pI830->LockHeld = 0;
pDRIInfo->drmDriverName = I830KernelDriverName;
pDRIInfo->clientDriverName = I830ClientDriverName;
if (IS_I965G(pI830))
pDRIInfo->clientDriverName = I965ClientDriverName;
else
pDRIInfo->clientDriverName = I830ClientDriverName;
if (xf86LoaderCheckSymbol("DRICreatePCIBusID")) {
pDRIInfo->busIdString = DRICreatePCIBusID(pI830->PciInfo);
} else {
@ -488,13 +497,16 @@ I830DRIScreenInit(ScreenPtr pScreen)
pDRIInfo->ddxDriverMajorVersion = I830_MAJOR_VERSION;
pDRIInfo->ddxDriverMinorVersion = I830_MINOR_VERSION;
pDRIInfo->ddxDriverPatchVersion = I830_PATCHLEVEL;
#if 1 /* temporary until this gets removed from the libdri layer */
#if 1 /* Remove this soon - see bug 5714 */
pDRIInfo->frameBufferPhysicalAddress = (char *) pI830->LinearAddr +
pI830->FrontBuffer.Start;
pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth *
pScrn->virtualY * pI830->cpp);
pDRIInfo->frameBufferStride = pScrn->displayWidth * pI830->cpp;
#else
/* For rotation we map a 0 length framebuffer as we remap ourselves later */
pDRIInfo->frameBufferSize = 0;
#endif
pDRIInfo->frameBufferStride = pScrn->displayWidth * pI830->cpp;
pDRIInfo->ddxDrawableTableEntry = I830_MAX_DRAWABLES;
if (SAREA_MAX_DRAWABLES < I830_MAX_DRAWABLES)
@ -534,6 +546,7 @@ I830DRIScreenInit(ScreenPtr pScreen)
pDRIInfo->TransitionSingleToMulti3D = I830DRITransitionSingleToMulti3d;
pDRIInfo->TransitionMultiToSingle3D = I830DRITransitionMultiToSingle3d;
/* do driver-independent DRI screen initialization here */
if (!DRIScreenInit(pScreen, pDRIInfo, &pI830->drmSubFD)) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] DRIScreenInit failed. Disabling DRI.\n");
@ -544,6 +557,27 @@ I830DRIScreenInit(ScreenPtr pScreen)
return FALSE;
}
#if 0 /* disabled now, see frameBufferSize above being set to 0 */
/* for this driver, get rid of the front buffer mapping now */
if (xf86LoaderCheckSymbol("DRIGetScreenPrivate")) {
DRIScreenPrivPtr pDRIPriv
= (DRIScreenPrivPtr) DRIGetScreenPrivate(pScreen);
if (pDRIPriv && pDRIPriv->drmFD && pDRIPriv->hFrameBuffer) {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] removing original screen mapping\n");
drmRmMap(pDRIPriv->drmFD, pDRIPriv->hFrameBuffer);
pDRIPriv->hFrameBuffer = 0;
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] done removing original screen mapping\n");
}
}
else {
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[intel] DRIGetScreenPrivate not found!!!!\n");
}
#endif
/* Check the i915 DRM versioning */
{
drmVersionPtr version;
@ -589,11 +623,11 @@ I830DRIScreenInit(ScreenPtr pScreen)
/* Check the i915 DRM version */
version = drmGetVersion(pI830->drmSubFD);
if (version) {
if (version->version_major != 1 || version->version_minor < 4) {
if (version->version_major != 1 || version->version_minor < 3) {
/* incompatible drm version */
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[dri] %s failed because of a version mismatch.\n"
"[dri] i915 kernel module version is %d.%d.%d but version 1.4 or greater is needed.\n"
"[dri] i915 kernel module version is %d.%d.%d but version 1.3 or greater is needed.\n"
"[dri] Disabling DRI.\n",
"I830DRIScreenInit",
version->version_major,
@ -623,21 +657,31 @@ I830DRIMapScreenRegions(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
ScreenPtr pScreen = pScrn->pScreen;
I830Ptr pI830 = I830PTR(pScrn);
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] Mapping front buffer\n");
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
sarea->front_size,
DRM_FRAME_BUFFER, /*DRM_AGP,*/
0,
(drmAddress) &sarea->front_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
#if 1 /* Remove this soon - see bug 5714 */
pI830->pDRIInfo->frameBufferSize = ROUND_TO_PAGE(pScrn->displayWidth *
pScrn->virtualY * pI830->cpp);
#endif
/* The I965G isn't ready for the front buffer mapping to be moved around,
* because of issues with rmmap, it seems.
*/
if (!IS_I965G(pI830)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"[drm] Mapping front buffer\n");
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->front_offset + pI830->LinearAddr),
sarea->front_size,
DRM_AGP,
0,
(drmAddress) &sarea->front_handle) < 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"[drm] drmAddMap(front_handle) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[drm] Front Buffer = 0x%08x\n",
(int)sarea->front_handle);
}
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "[drm] Front Buffer = 0x%08x\n",
(int)sarea->front_handle);
if (drmAddMap(pI830->drmSubFD,
(drm_handle_t)(sarea->back_offset + pI830->LinearAddr),
@ -684,12 +728,10 @@ I830DRIUnmapScreenRegions(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
{
I830Ptr pI830 = I830PTR(pScrn);
#if 1
if (sarea->front_handle) {
drmRmMap(pI830->drmSubFD, sarea->front_handle);
sarea->front_handle = 0;
}
#endif
if (sarea->back_handle) {
drmRmMap(pI830->drmSubFD, sarea->back_handle);
sarea->back_handle = 0;
@ -785,7 +827,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
/* screen mappings probably failed */
xf86DrvMsg(pScreen->myNum, X_ERROR,
"[drm] drmAddMap(screen mappings) failed. Disabling DRI\n");
DRICloseScreen(pScreen);
return FALSE;
}
@ -824,9 +865,6 @@ I830DRIDoMappings(ScreenPtr pScreen)
pI830DRI->mem = pScrn->videoRam * 1024;
pI830DRI->cpp = pI830->cpp;
pI830DRI->fbOffset = pI830->FrontBuffer.Start;
pI830DRI->fbStride = pI830->backPitch;
pI830DRI->bitsPerPixel = pScrn->bitsPerPixel;
pI830DRI->sarea_priv_offset = sizeof(XF86DRISAREARec);
@ -1166,8 +1204,10 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
I830SelectBuffer(pScrn, I830_SELECT_BACK);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
if (!IS_I965G(pI830)) {
I830SelectBuffer(pScrn, I830_SELECT_DEPTH);
I830SubsequentScreenToScreenCopy(pScrn, x1, y1, destx, desty, w, h);
}
}
I830SelectBuffer(pScrn, I830_SELECT_FRONT);
I830EmitFlush(pScrn);
@ -1184,28 +1224,6 @@ I830DRIMoveBuffers(WindowPtr pParent, DDXPointRec ptOldOrg,
pI830->AccelInfoRec->NeedToSync = TRUE;
}
/* Initialize the first context */
void
I830EmitInvarientState(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 ctx_addr;
ctx_addr = pI830->ContextMem.Start;
/* Align to a 2k boundry */
ctx_addr = ((ctx_addr + 2048 - 1) / 2048) * 2048;
{
BEGIN_LP_RING(2);
OUT_RING(MI_SET_CONTEXT);
OUT_RING(ctx_addr |
CTXT_NO_RESTORE |
CTXT_PALETTE_SAVE_DISABLE | CTXT_PALETTE_RESTORE_DISABLE);
ADVANCE_LP_RING();
}
}
/* Use callbacks from dri.c to support pageflipping mode for a single
* 3d context without need for any specific full-screen extension.
*
@ -1229,6 +1247,7 @@ I830EmitInvarientState(ScrnInfoPtr pScrn)
* might be faster, but seems like a lot more work...
*/
#if 0
/* This should be done *before* XAA syncs,
* Otherwise will have to sync again???
@ -1238,7 +1257,7 @@ I830DRIShadowUpdate (ScreenPtr pScreen, shadowBufPtr pBuf)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
RegionPtr damage = (RegionPtr) shadowDamage(pBuf);
RegionPtr damage = &pBuf->damage;
int i, num = REGION_NUM_RECTS(damage);
BoxPtr pbox = REGION_RECTS(damage);
drmI830Sarea *pSAREAPriv = DRIGetSAREAPrivate(pScreen);
@ -1368,6 +1387,7 @@ I830DRITransitionTo2d(ScreenPtr pScreen)
}
pI830->have3DWindows = 0;
}
@ -1384,6 +1404,14 @@ I830UpdateDRIBuffers(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
I830DRIUnmapScreenRegions(pScrn, sarea);
sarea->front_tiled = pI830->front_tiled;
sarea->back_tiled = pI830->back_tiled;
sarea->depth_tiled = pI830->depth_tiled;
sarea->rotated_tiled = pI830->rotated_tiled;
#if 0
sarea->rotated2_tiled = pI830->rotated2_tiled;
#endif
if (pI830->rotation == RR_Rotate_0) {
sarea->front_offset = pI830->FrontBuffer.Start;
/* Don't use FrontBuffer.Size here as it includes the pixmap cache area
@ -1443,7 +1471,8 @@ I830UpdateDRIBuffers(ScrnInfoPtr pScrn, drmI830Sarea *sarea)
success = I830DRIMapScreenRegions(pScrn, sarea);
I830InitTextureHeap(pScrn, sarea);
if (success)
I830InitTextureHeap(pScrn, sarea);
return success;
}

40
src/i830_dri.h
View File

@ -9,8 +9,8 @@
#define I830_MAX_DRAWABLES 256
#define I830_MAJOR_VERSION 1
#define I830_MINOR_VERSION 5
#define I830_PATCHLEVEL 1
#define I830_MINOR_VERSION 6
#define I830_PATCHLEVEL 4
#define I830_REG_SIZE 0x80000
@ -18,20 +18,20 @@ typedef struct _I830DRIRec {
drm_handle_t regs;
drmSize regsSize;
drmSize backbufferSize;
drm_handle_t backbuffer;
drmSize unused1; /* backbufferSize */
drm_handle_t unused2; /* backbuffer */
drmSize depthbufferSize;
drm_handle_t depthbuffer;
drmSize unused3; /* depthbufferSize */
drm_handle_t unused4; /* depthbuffer */
drmSize rotatedSize;
drm_handle_t rotatedbuffer;
drmSize unused5; /* rotatedSize /*/
drm_handle_t unused6; /* rotatedbuffer */
drm_handle_t textures;
int textureSize;
drm_handle_t unused7; /* textures */
int unused8; /* textureSize */
drm_handle_t agp_buffers;
drmSize agp_buf_size;
drm_handle_t unused9; /* agp_buffers */
drmSize unused10; /* agp_buf_size */
int deviceID;
int width;
@ -40,20 +40,10 @@ typedef struct _I830DRIRec {
int cpp;
int bitsPerPixel;
int fbOffset;
int fbStride;
int unused11[8]; /* was front/back/depth/rotated offset/pitch */
int backOffset;
int backPitch;
int depthOffset;
int depthPitch;
int rotatedOffset;
int rotatedPitch;
int logTextureGranularity;
int textureOffset;
int unused12; /* logTextureGranularity */
int unused13; /* textureOffset */
int irq;
int sarea_priv_offset;

471
src/i830_driver.c
View File

@ -150,6 +150,11 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
* 09/2005 Alan Hourihane
* - Add Intel(R) 945GM support.
*
* 10/2005 Alan Hourihane, Keith Whitwell, Brian Paul
* - Added Rotation support
*
* 12/2005 Alan Hourihane, Keith Whitwell
* - Add Intel(R) 965G support.
*/
#ifdef HAVE_CONFIG_H
@ -161,6 +166,7 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#endif
#include <string.h>
#include <stdio.h>
#include <unistd.h>
#include <stdlib.h>
#include <stdio.h>
@ -179,10 +185,10 @@ USE OR OTHER DEALINGS IN THE SOFTWARE.
#include <X11/extensions/randr.h>
#include "fb.h"
#include "miscstruct.h"
#include "dixstruct.h"
#include "xf86xv.h"
#include <X11/extensions/Xv.h>
#include "vbe.h"
#include "vbeModes.h"
#include "shadow.h"
#include "i830.h"
#include "i830_display.h"
@ -208,6 +214,10 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I915_GM, "915GM"},
{PCI_CHIP_I945_G, "945G"},
{PCI_CHIP_I945_GM, "945GM"},
{PCI_CHIP_I965_G, "965G"},
{PCI_CHIP_I965_G_1, "965G"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{-1, NULL}
};
@ -221,6 +231,10 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I915_GM, PCI_CHIP_I915_GM, RES_SHARED_VGA},
{PCI_CHIP_I945_G, PCI_CHIP_I945_G, RES_SHARED_VGA},
{PCI_CHIP_I945_GM, PCI_CHIP_I945_GM, RES_SHARED_VGA},
{PCI_CHIP_I965_G, PCI_CHIP_I965_G, RES_SHARED_VGA},
{PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@ -248,7 +262,7 @@ typedef enum {
OPTION_CHECKDEVICES,
OPTION_FIXEDPIPE,
OPTION_ROTATE,
OPTION_LINEARALLOC
OPTION_LINEARALLOC,
} I830Opts;
static OptionInfoRec I830Options[] = {
@ -298,7 +312,6 @@ extern int I830EntityIndex;
/* temporary */
extern void xf86SetCursor(ScreenPtr pScreen, CursorPtr pCurs, int x, int y);
#ifdef I830DEBUG
void
I830DPRINTF_stub(const char *filename, int line, const char *function,
@ -353,7 +366,6 @@ I830FreeRec(ScrnInfoPtr pScrn)
{
I830Ptr pI830;
VESAPtr pVesa;
DisplayModePtr mode;
if (!pScrn)
return;
@ -361,21 +373,6 @@ I830FreeRec(ScrnInfoPtr pScrn)
return;
pI830 = I830PTR(pScrn);
mode = pScrn->modes;
if (mode) {
do {
if (mode->Private) {
VbeModeInfoData *data = (VbeModeInfoData *) mode->Private;
if (data->block)
xfree(data->block);
xfree(data);
mode->Private = NULL;
}
mode = mode->next;
} while (mode && mode != pScrn->modes);
}
if (I830IsPrimary(pScrn)) {
if (pI830->vbeInfo)
@ -385,8 +382,6 @@ I830FreeRec(ScrnInfoPtr pScrn)
}
pVesa = pI830->vesa;
if (pVesa->monitor)
xfree(pVesa->monitor);
if (pVesa->savedPal)
xfree(pVesa->savedPal);
xfree(pVesa);
@ -587,10 +582,6 @@ PrintDisplayDeviceInfo(ScrnInfoPtr pScrn)
name = DeviceToString(-1);
} while (name);
if (pipe & PIPE_UNKNOWN_ACTIVE)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"\tSome unknown display devices may also be present\n");
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"No active displays on Pipe %c.\n", PIPE_NAME(n));
@ -658,6 +649,12 @@ I830DetectMemory(ScrnInfoPtr pScrn)
break;
}
}
#if 0
/* And 64KB page aligned */
memsize &= ~0xFFFF;
#endif
if (memsize > 0) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"detected %d kB stolen memory.\n", memsize / 1024);
@ -742,7 +739,7 @@ I830LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
unsigned char r, g, b;
CARD32 val, temp;
int palreg;
int dspreg, dspbase;
int dspreg, dspbase, dspsurf;
int p;
DPRINTF(PFX, "I830LoadPalette: numColors: %d\n", numColors);
@ -754,10 +751,12 @@ I830LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
palreg = PALETTE_A;
dspreg = DSPACNTR;
dspbase = DSPABASE;
dspsurf = DSPASURF;
} else {
palreg = PALETTE_B;
dspreg = DSPBCNTR;
dspbase = DSPBBASE;
dspsurf = DSPBSURF;
}
if (pI830->planeEnabled[p] == 0)
@ -771,6 +770,8 @@ I830LoadPalette(ScrnInfoPtr pScrn, int numColors, int *indices,
OUTREG(dspbase, INREG(dspbase));
OUTREG(dspreg, temp | DISPPLANE_GAMMA_ENABLE);
OUTREG(dspbase, INREG(dspbase));
if (IS_I965G(pI830))
OUTREG(dspsurf, INREG(dspsurf));
/* It seems that an initial read is needed. */
temp = INREG(palreg);
@ -1315,6 +1316,16 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_I945_GM:
chipname = "945GM";
break;
case PCI_CHIP_I965_G:
case PCI_CHIP_I965_G_1:
chipname = "965G";
break;
case PCI_CHIP_I965_Q:
chipname = "965Q";
break;
case PCI_CHIP_I946_GZ:
chipname = "946GZ";
break;
default:
chipname = "unknown chipset";
break;
@ -1339,6 +1350,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
from = X_CONFIG;
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "ChipID override: 0x%04X\n",
pI830->pEnt->device->chipID);
pI830->PciInfo->chipType = pI830->pEnt->device->chipID;
} else {
from = X_PROBED;
pScrn->chipset = (char *)xf86TokenToString(I830Chipsets,
@ -1518,8 +1530,11 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->LinearAlloc = 0;
if (xf86GetOptValULong(pI830->Options, OPTION_LINEARALLOC,
&(pI830->LinearAlloc))) {
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Allocating %luKbytes of memory\n",
if (pI830->LinearAlloc > 0)
xf86DrvMsg(pScrn->scrnIndex, X_CONFIG, "Allocating %luKbytes of memory\n",
pI830->LinearAlloc);
else
pI830->LinearAlloc = 0;
}
pI830->fixedPipe = -1;
@ -1593,7 +1608,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->MonType1 |= PIPE_DFP;
else if (strcmp(sub, "LFP") == 0)
pI830->MonType1 |= PIPE_LFP;
else if (strcmp(sub, "CRT2") == 0)
else if (strcmp(sub, "Second") == 0)
pI830->MonType1 |= PIPE_CRT2;
else if (strcmp(sub, "TV2") == 0)
pI830->MonType1 |= PIPE_TV2;
@ -1622,7 +1637,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
pI830->MonType2 |= PIPE_DFP;
else if (strcmp(sub, "LFP") == 0)
pI830->MonType2 |= PIPE_LFP;
else if (strcmp(sub, "CRT2") == 0)
else if (strcmp(sub, "Second") == 0)
pI830->MonType2 |= PIPE_CRT2;
else if (strcmp(sub, "TV2") == 0)
pI830->MonType2 |= PIPE_TV2;
@ -1756,9 +1771,16 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
}
if ((pI830->entityPrivate && I830IsPrimary(pScrn)) || pI830->Clone) {
if ((!xf86GetOptValString(pI830->Options, OPTION_MONITOR_LAYOUT))) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "You must have a MonitorLayout "
"defined for use in a DualHead, Clone or MergedFB setup.\n");
PreInitCleanup(pScrn);
return FALSE;
}
if (pI830->MonType1 == PIPE_NONE || pI830->MonType2 == PIPE_NONE) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR, "Monitor 1 or Monitor 2 "
"cannot be type NONE in Dual or Clone setup.\n");
"cannot be type NONE in DualHead or Clone setup.\n");
PreInitCleanup(pScrn);
return FALSE;
}
@ -2004,6 +2026,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
else
pI830->CursorNeedsPhysical = FALSE;
if (IS_I965G(pI830))
pI830->CursorNeedsPhysical = FALSE;
/* Force ring buffer to be in low memory for all chipsets */
pI830->NeedRingBufferLow = TRUE;
@ -2345,8 +2370,12 @@ CheckInheritedState(ScrnInfoPtr pScrn)
}
#if 0
if (errors)
I830PrintErrorState(pScrn);
if (errors) {
if (IS_I965G(pI830))
I965PrintErrorState(pScrn);
else
I830PrintErrorState(pScrn);
}
#endif
if (fatal)
@ -2376,8 +2405,15 @@ ResetState(ScrnInfoPtr pScrn, Bool flush)
pI830->entityPrivate->RingRunning = 0;
/* Reset the fence registers to 0 */
for (i = 0; i < 8; i++)
OUTREG(FENCE + i * 4, 0);
if (IS_I965G(pI830)) {
for (i = 0; i < FENCE_NEW_NR; i++) {
OUTREG(FENCE_NEW + i * 8, 0);
OUTREG(FENCE_NEW + 4 + i * 8, 0);
}
} else {
for (i = 0; i < FENCE_NR; i++)
OUTREG(FENCE + i * 4, 0);
}
/* Flush the ring buffer (if enabled), then disable it. */
if (pI830->AccelInfoRec != NULL && flush) {
@ -2407,10 +2443,21 @@ SetFenceRegs(ScrnInfoPtr pScrn)
if (!I830IsPrimary(pScrn)) return;
for (i = 0; i < 8; i++) {
OUTREG(FENCE + i * 4, pI830->ModeReg.Fence[i]);
if (I810_DEBUG & DEBUG_VERBOSE_VGA)
ErrorF("Fence Register : %x\n", pI830->ModeReg.Fence[i]);
if (IS_I965G(pI830)) {
for (i = 0; i < FENCE_NEW_NR; i++) {
OUTREG(FENCE_NEW + i * 8, pI830->ModeReg.Fence[i]);
OUTREG(FENCE_NEW + 4 + i * 8, pI830->ModeReg.Fence[i+FENCE_NEW_NR]);
if (I810_DEBUG & DEBUG_VERBOSE_VGA) {
ErrorF("Fence Start Register : %x\n", pI830->ModeReg.Fence[i]);
ErrorF("Fence End Register : %x\n", pI830->ModeReg.Fence[i+FENCE_NEW_NR]);
}
}
} else {
for (i = 0; i < FENCE_NR; i++) {
OUTREG(FENCE + i * 4, pI830->ModeReg.Fence[i]);
if (I810_DEBUG & DEBUG_VERBOSE_VGA)
ErrorF("Fence Register : %x\n", pI830->ModeReg.Fence[i]);
}
}
}
@ -2543,6 +2590,11 @@ SaveHWState(ScrnInfoPtr pScrn)
}
}
if (IS_I965G(pI830)) {
pI830->saveDSPASURF = INREG(DSPASURF);
pI830->saveDSPBSURF = INREG(DSPBSURF);
}
pI830->saveVCLK_DIVISOR_VGA0 = INREG(VCLK_DIVISOR_VGA0);
pI830->saveVCLK_DIVISOR_VGA1 = INREG(VCLK_DIVISOR_VGA1);
pI830->saveVCLK_POST_DIV = INREG(VCLK_POST_DIV);
@ -2566,7 +2618,6 @@ SaveHWState(ScrnInfoPtr pScrn)
pI830->backlight_duty_cycle = ((pI830->saveBLC_PWM_CTL &
BACKLIGHT_MODULATION_FREQ_MASK) >>
BACKLIGHT_MODULATION_FREQ_SHIFT);
if (!IS_I9XX(pI830)) {
pI830->saveDVOA = INREG(DVOA);
@ -2682,6 +2733,11 @@ RestoreHWState(ScrnInfoPtr pScrn)
}
}
if (IS_I965G(pI830)) {
OUTREG(DSPASURF, pI830->saveDSPABASE);
OUTREG(DSPBSURF, pI830->saveDSPBBASE);
}
OUTREG(BLC_PWM_CTL, pI830->saveBLC_PWM_CTL);
OUTREG(LVDSPP_ON, pI830->savePP_ON);
OUTREG(LVDSPP_OFF, pI830->savePP_OFF);
@ -2781,6 +2837,72 @@ I830PrintErrorState(ScrnInfoPtr pScrn)
INREG16(HWSTAM), INREG16(IER), INREG16(IMR), INREG16(IIR));
}
void
I965PrintErrorState(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
ErrorF("pgetbl_ctl: 0x%lx pgetbl_err: 0x%lx\n",
INREG(PGETBL_CTL), INREG(PGE_ERR));
ErrorF("ipeir: %lx iphdr: %lx\n", INREG(IPEIR_I965), INREG(IPEHR_I965));
ErrorF("LP ring tail: %lx head: %lx len: %lx start %lx\n",
INREG(LP_RING + RING_TAIL),
INREG(LP_RING + RING_HEAD) & HEAD_ADDR,
INREG(LP_RING + RING_LEN), INREG(LP_RING + RING_START));
ErrorF("Err ID (eir): %x Err Status (esr): %x Err Mask (emr): %x\n",
(int)INREG(EIR), (int)INREG(ESR), (int)INREG(EMR));
ErrorF("instdone: %x instdone_1: %x\n", (int)INREG(INST_DONE_I965),
(int)INREG(INST_DONE_1));
ErrorF("instpm: %x\n", (int)INREG(INST_PM));
ErrorF("memmode: %lx instps: %lx\n", INREG(MEMMODE), INREG(INST_PS_I965));
ErrorF("HW Status mask (hwstam): %x\nIRQ enable (ier): %x imr: %x iir: %x\n",
(int)INREG(HWSTAM), (int)INREG(IER), (int)INREG(IMR),
(int)INREG(IIR));
ErrorF("acthd: %lx dma_fadd_p: %lx\n", INREG(ACTHD), INREG(DMA_FADD_P));
ErrorF("ecoskpd: %lx excc: %lx\n", INREG(ECOSKPD), INREG(EXCC));
ErrorF("cache_mode: %x/%x\n", (int)INREG(CACHE_MODE_0),
(int)INREG(CACHE_MODE_1));
ErrorF("mi_arb_state: %x\n", (int)INREG(MI_ARB_STATE));
ErrorF("IA_VERTICES_COUNT_QW %x/%x\n", (int)INREG(IA_VERTICES_COUNT_QW),
(int)INREG(IA_VERTICES_COUNT_QW+4));
ErrorF("IA_PRIMITIVES_COUNT_QW %x/%x\n", (int)INREG(IA_PRIMITIVES_COUNT_QW),
(int)INREG(IA_PRIMITIVES_COUNT_QW+4));
ErrorF("VS_INVOCATION_COUNT_QW %x/%x\n", (int)INREG(VS_INVOCATION_COUNT_QW),
(int)INREG(VS_INVOCATION_COUNT_QW+4));
ErrorF("GS_INVOCATION_COUNT_QW %x/%x\n", (int)INREG(GS_INVOCATION_COUNT_QW),
(int)INREG(GS_INVOCATION_COUNT_QW+4));
ErrorF("GS_PRIMITIVES_COUNT_QW %x/%x\n", (int)INREG(GS_PRIMITIVES_COUNT_QW),
(int)INREG(GS_PRIMITIVES_COUNT_QW+4));
ErrorF("CL_INVOCATION_COUNT_QW %x/%x\n", (int)INREG(CL_INVOCATION_COUNT_QW),
(int)INREG(CL_INVOCATION_COUNT_QW+4));
ErrorF("CL_PRIMITIVES_COUNT_QW %x/%x\n", (int)INREG(CL_PRIMITIVES_COUNT_QW),
(int)INREG(CL_PRIMITIVES_COUNT_QW+4));
ErrorF("PS_INVOCATION_COUNT_QW %x/%x\n", (int)INREG(PS_INVOCATION_COUNT_QW),
(int)INREG(PS_INVOCATION_COUNT_QW+4));
ErrorF("PS_DEPTH_COUNT_QW %x/%x\n", (int)INREG(PS_DEPTH_COUNT_QW),
(int)INREG(PS_DEPTH_COUNT_QW+4));
ErrorF("WIZ_CTL %x\n", (int)INREG(WIZ_CTL));
ErrorF("TS_CTL %x TS_DEBUG_DATA %x\n", (int)INREG(TS_CTL),
(int)INREG(TS_DEBUG_DATA));
ErrorF("TD_CTL %x / %x\n", (int)INREG(TD_CTL), (int)INREG(TD_CTL2));
}
#ifdef I830DEBUG
static void
dump_DSPACNTR(ScrnInfoPtr pScrn)
@ -3053,6 +3175,38 @@ I830InitFBManager(
return ret;
}
/* Initialize the first context */
void
IntelEmitInvarientState(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 ctx_addr;
if (pI830->noAccel)
return;
ctx_addr = pI830->ContextMem.Start;
/* Align to a 2k boundry */
ctx_addr = ((ctx_addr + 2048 - 1) / 2048) * 2048;
{
BEGIN_LP_RING(2);
OUT_RING(MI_SET_CONTEXT);
OUT_RING(ctx_addr |
CTXT_NO_RESTORE |
CTXT_PALETTE_SAVE_DISABLE | CTXT_PALETTE_RESTORE_DISABLE);
ADVANCE_LP_RING();
}
if (!IS_I965G(pI830))
{
if (IS_I9XX(pI830))
I915EmitInvarientState(pScrn);
else
I830EmitInvarientState(pScrn);
}
}
static Bool
I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
{
@ -3070,28 +3224,6 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
hwp = VGAHWPTR(pScrn);
pScrn->displayWidth = pI830->displayWidth;
switch (pI830->InitialRotation) {
case 0:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 0 degrees\n");
pI830->rotation = RR_Rotate_0;
break;
case 90:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 90 degrees\n");
pI830->rotation = RR_Rotate_90;
break;
case 180:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 180 degrees\n");
pI830->rotation = RR_Rotate_180;
break;
case 270:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 270 degrees\n");
pI830->rotation = RR_Rotate_270;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad rotation setting - defaulting to 0 degrees\n");
pI830->rotation = RR_Rotate_0;
break;
}
if (I830IsPrimary(pScrn)) {
/* Rotated Buffer */
@ -3102,6 +3234,47 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
pI830->RotatedMem2.Key = -1;
}
#ifdef HAS_MTRR_SUPPORT
{
int fd;
struct mtrr_gentry gentry;
struct mtrr_sentry sentry;
if ( ( fd = open ("/proc/mtrr", O_RDONLY, 0) ) != -1 ) {
for (gentry.regnum = 0; ioctl (fd, MTRRIOC_GET_ENTRY, &gentry) == 0;
++gentry.regnum) {
if (gentry.size < 1) {
/* DISABLED */
continue;
}
/* Check the MTRR range is one we like and if not - remove it.
* The Xserver common layer will then setup the right range
* for us.
*/
if (gentry.base == pI830->LinearAddr &&
gentry.size < pI830->FbMapSize) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Removing bad MTRR range (base 0x%lx, size 0x%x)\n",
gentry.base, gentry.size);
sentry.base = gentry.base;
sentry.size = gentry.size;
sentry.type = gentry.type;
if (ioctl (fd, MTRRIOC_DEL_ENTRY, &sentry) == -1) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"Failed to remove bad MTRR range\n");
}
}
}
close(fd);
}
}
#endif
if (xf86IsEntityShared(pScrn->entityList[0])) {
/* PreInit failed on the second head, so make sure we turn it off */
if (I830IsPrimary(pScrn) && !pI830->entityPrivate->pScrn_2) {
@ -3428,12 +3601,13 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
}
#endif
/* Setup 3D engine, needed for rotation too */
IntelEmitInvarientState(pScrn);
#ifdef XF86DRI
if (pI830->directRenderingEnabled) {
pI830->directRenderingOpen = TRUE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "direct rendering: Enabled\n");
/* Setup 3D engine */
I830EmitInvarientState(pScrn);
} else {
if (driDisabled)
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "direct rendering: Disabled\n");
@ -3454,7 +3628,11 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
xf86DisableRandR(); /* Disable built-in RandR extension */
shadowSetup(pScreen);
/* support all rotations */
I830RandRInit(pScreen, RR_Rotate_0 | RR_Rotate_90 | RR_Rotate_180 | RR_Rotate_270);
if (IS_I965G(pI830)) {
I830RandRInit(pScreen, RR_Rotate_0); /* only 0 degrees for I965G */
} else {
I830RandRInit(pScreen, RR_Rotate_0 | RR_Rotate_90 | RR_Rotate_180 | RR_Rotate_270);
}
pI830->PointerMoved = pScrn->PointerMoved;
pScrn->PointerMoved = I830PointerMoved;
pI830->CreateScreenResources = pScreen->CreateScreenResources;
@ -3471,10 +3649,47 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
I830_dump_registers(pScrn);
#endif
if (IS_I965G(pI830)) {
/* turn off clock gating */
#if 0
OUTREG(0x6204, 0x70804000);
OUTREG(0x6208, 0x00000001);
#else
OUTREG(0x6204, 0x70000000);
#endif
/* Enable DAP stateless accesses.
* Required for all i965 steppings.
*/
OUTREG(SVG_WORK_CTL, 0x00000010);
}
pI830->starting = FALSE;
pI830->closing = FALSE;
pI830->suspended = FALSE;
switch (pI830->InitialRotation) {
case 0:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 0 degrees\n");
pI830->rotation = RR_Rotate_0;
break;
case 90:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 90 degrees\n");
pI830->rotation = RR_Rotate_90;
break;
case 180:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 180 degrees\n");
pI830->rotation = RR_Rotate_180;
break;
case 270:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Rotating to 270 degrees\n");
pI830->rotation = RR_Rotate_270;
break;
default:
xf86DrvMsg(pScrn->scrnIndex, X_INFO, "Bad rotation setting - defaulting to 0 degrees\n");
pI830->rotation = RR_Rotate_0;
break;
}
return TRUE;
}
@ -3482,9 +3697,7 @@ static void
i830AdjustFrame(int scrnIndex, int x, int y, int flags)
{
ScrnInfoPtr pScrn = xf86Screens[scrnIndex];
I830Ptr pI830;
pI830 = I830PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
DPRINTF(PFX, "i830AdjustFrame: y = %d (+ %d), x = %d (+ %d)\n",
x, pI830->xoffset, y, pI830->yoffset);
@ -3544,7 +3757,9 @@ I830LeaveVT(int scrnIndex, int flags)
#ifdef XF86DRI
if (pI830->directRenderingOpen) {
I830DRILock(pScrn);
DRILock(screenInfo.screens[pScrn->scrnIndex], 0);
I830DRISetVBlankInterrupt (pScrn, FALSE);
drmCtlUninstHandler(pI830->drmSubFD);
}
@ -3571,10 +3786,11 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
pointer pDDCModule = NULL;
DisplayModePtr p, pMon;
int memsize;
int DDCclock = 0;
int DDCclock = 0, DDCclock2 = 0;
int displayWidth = pScrn->displayWidth;
int curHDisplay = pScrn->currentMode->HDisplay;
int curVDisplay = pScrn->currentMode->VDisplay;
xf86MonPtr monitor = NULL;
DPRINTF(PFX, "Detect Monitor Change\n");
@ -3582,19 +3798,16 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
/* Re-read EDID */
pDDCModule = xf86LoadSubModule(pScrn, "ddc");
if (pI830->vesa->monitor)
xfree(pI830->vesa->monitor);
pI830->vesa->monitor = vbeDoEDID(pI830->pVbe, pDDCModule);
xf86UnloadSubModule(pDDCModule);
if ((pScrn->monitor->DDC = pI830->vesa->monitor) != NULL) {
xf86PrintEDID(pI830->vesa->monitor);
xf86SetDDCproperties(pScrn, pI830->vesa->monitor);
} else
/* No DDC, so get out of here, and continue to use the current settings */
return FALSE;
if (!(DDCclock = I830UseDDC(pScrn)))
return FALSE;
pI830->pVbe->ddc = DDC_UNCHECKED;
monitor = vbeDoEDID(pI830->pVbe, pDDCModule);
xf86UnloadSubModule(pDDCModule);
if ((pScrn->monitor->DDC = monitor) != NULL) {
xf86PrintEDID(monitor);
xf86SetDDCproperties(pScrn, monitor);
}
DDCclock = I830UseDDC(pScrn);
/* Revalidate the modes */
@ -3602,6 +3815,8 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
* Note: VBE modes (> 0x7f) won't work with Intel's extended BIOS
* functions.
*/
SetPipeAccess(pScrn);
pScrn->modePool = I830GetModePool(pScrn, pI830->pVbe, pI830->vbeInfo);
if (!pScrn->modePool) {
@ -3612,7 +3827,6 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
return FALSE;
}
SetPipeAccess(pScrn);
VBESetModeNames(pScrn->modePool);
if (pScrn->videoRam > (pI830->vbeInfo->TotalMemory * 64))
@ -3627,6 +3841,16 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
pScrn->display->virtualY,
memsize, LOOKUP_BEST_REFRESH);
if (pI830->MergedFB) {
VBEValidateModes(pI830->pScrn_2, pI830->pScrn_2->monitor->Modes,
pI830->pScrn_2->display->modes, NULL,
NULL, 0, MAX_DISPLAY_PITCH, 1,
0, MAX_DISPLAY_HEIGHT,
pScrn->display->virtualX,
pScrn->display->virtualY,
memsize, LOOKUP_BEST_REFRESH);
}
if (DDCclock > 0) {
p = pScrn->modes;
if (p == NULL)
@ -3657,7 +3881,36 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
} while (p != NULL && p != pScrn->modes);
}
pScrn->displayWidth = displayWidth; /* restore old displayWidth */
/* Only use this if we've got DDC available */
if (pI830->MergedFB && DDCclock2 > 0) {
p = pI830->pScrn_2->modes;
if (p == NULL)
return FALSE;
do {
int Clock = 100000000; /* incredible value */
if (p->status == MODE_OK) {
for (pMon = pI830->pScrn_2->monitor->Modes; pMon != NULL; pMon = pMon->next) {
if ((pMon->HDisplay != p->HDisplay) ||
(pMon->VDisplay != p->VDisplay) ||
(pMon->Flags & (V_INTERLACE | V_DBLSCAN | V_CLKDIV2)))
continue;
/* Find lowest supported Clock for this resolution */
if (Clock > pMon->Clock)
Clock = pMon->Clock;
}
if (Clock != 100000000 && DDCclock2 < 2550 && Clock / 1000.0 > DDCclock2) {
ErrorF("(%s,%s) mode clock %gMHz exceeds DDC maximum %dMHz\n",
p->name, pI830->pScrn_2->monitor->id,
Clock/1000.0, DDCclock2);
p->status = MODE_BAD;
}
}
p = p->next;
} while (p != NULL && p != pI830->pScrn_2->modes);
}
xf86PruneDriverModes(pScrn);
I830PrintModes(pScrn);
@ -3667,6 +3920,21 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
* and reconnecting monitors */
pScrn->currentMode = pScrn->modes;
if (pI830->MergedFB) {
/* If no virtual dimension was given by the user,
* calculate a sane one now. Adapts pScrn->virtualX,
* pScrn->virtualY and pScrn->displayWidth.
*/
I830RecalcDefaultVirtualSize(pScrn);
pScrn->modes = pScrn->modes->next; /* We get the last from GenerateModeList(), skip to first */
pScrn->currentMode = pScrn->modes;
pI830->currentMode = pScrn->currentMode;
}
pScrn->displayWidth = displayWidth; /* restore old displayWidth */
p = pScrn->modes;
if (p == NULL)
return FALSE;
@ -3679,6 +3947,8 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
p = p->next;
} while (p != NULL && p != pScrn->modes);
I830PrintModes(pScrn);
/* Now readjust for panning if necessary */
{
pScrn->frameX0 = (pScrn->frameX0 + pScrn->frameX1 + 1 - pScrn->currentMode->HDisplay) / 2;
@ -3704,6 +3974,9 @@ I830DetectMonitorChange(ScrnInfoPtr pScrn)
}
}
if (pI830->MergedFB)
I830AdjustFrameMerged(pScrn->scrnIndex, pScrn->frameX0, pScrn->frameY0, 0);
return TRUE;
#endif /* 0 */
}
@ -3766,16 +4039,26 @@ I830EnterVT(int scrnIndex, int flags)
#ifdef XF86DRI
if (pI830->directRenderingEnabled) {
I830DRISetVBlankInterrupt (pScrn, TRUE);
if (!pI830->starting) {
ScreenPtr pScreen = pScrn->pScreen;
drmI830Sarea *sarea = (drmI830Sarea *) DRIGetSAREAPrivate(pScreen);
int i;
I830DRIResume(screenInfo.screens[scrnIndex]);
I830EmitInvarientState(pScrn);
I830RefreshRing(pScrn);
I830Sync(pScrn);
DO_RING_IDLE();
sarea->texAge++;
for(i = 0; i < I830_NR_TEX_REGIONS+1 ; i++)
sarea->texList[i].age = sarea->texAge;
DPRINTF(PFX, "calling dri unlock\n");
I830DRIUnlock(pScrn);
DRIUnlock(screenInfo.screens[pScrn->scrnIndex]);
}
pI830->LockHeld = 0;
}
@ -3788,6 +4071,9 @@ I830EnterVT(int scrnIndex, int flags)
*/
i830SetHotkeyControl(pScrn, HOTKEY_DRIVER_NOTIFY);
/* Needed for rotation */
IntelEmitInvarientState(pScrn);
if (pI830->checkDevices)
pI830->devicesTimer = TimerSet(NULL, 0, 1000, I830CheckDevicesTimer, pScrn);
@ -3837,7 +4123,8 @@ I830SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
* The extra WindowTable check detects a rotation at startup.
*/
if ( (!WindowTable[pScrn->scrnIndex] || pspix->devPrivate.ptr == NULL) &&
!pI830->DGAactive ) {
!pI830->DGAactive && (pScrn->PointerMoved == I830PointerMoved) &&
!IS_I965G(pI830)) {
if (!I830Rotate(pScrn, mode))
ret = FALSE;
}
@ -3873,7 +4160,7 @@ I830SaveScreen(ScreenPtr pScreen, int mode)
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
Bool on = xf86IsUnblank(mode);
CARD32 temp, ctrl, base;
CARD32 temp, ctrl, base, surf;
int i;
DPRINTF(PFX, "I830SaveScreen: %d, on is %s\n", mode, BOOLTOSTRING(on));
@ -3883,9 +4170,11 @@ I830SaveScreen(ScreenPtr pScreen, int mode)
if (i == 0) {
ctrl = DSPACNTR;
base = DSPABASE;
surf = DSPASURF;
} else {
ctrl = DSPBCNTR;
base = DSPBADDR;
surf = DSPBSURF;
}
if (pI830->planeEnabled[i]) {
temp = INREG(ctrl);
@ -3897,6 +4186,10 @@ I830SaveScreen(ScreenPtr pScreen, int mode)
/* Flush changes */
temp = INREG(base);
OUTREG(base, temp);
if (IS_I965G(pI830)) {
temp = INREG(surf);
OUTREG(surf, temp);
}
}
}
@ -4060,9 +4353,7 @@ I830CloseScreen(int scrnIndex, ScreenPtr pScreen)
pI830->used3D = NULL;
}
if (pI830->shadowReq.minorversion >= 1)
pScrn->PointerMoved = pI830->PointerMoved;
pScrn->PointerMoved = pI830->PointerMoved;
pScrn->vtSema = FALSE;
pI830->closing = FALSE;
pScreen->CloseScreen = pI830->CloseScreen;

111
src/i830_memory.c
View File

@ -205,12 +205,12 @@ AllocFromAGP(ScrnInfoPtr pScrn, I830MemRange *result, long size,
if (newApStart > newApEnd)
return 0;
if (flags & NEED_PHYSICAL_ADDR) {
if (flags & NEED_PHYSICAL_ADDR)
result->Key = xf86AllocateGARTMemory(pScrn->scrnIndex, size, 2,
&(result->Physical));
} else {
else
result->Key = xf86AllocateGARTMemory(pScrn->scrnIndex, size, 0, NULL);
}
if (result->Key == -1)
return 0;
}
@ -490,7 +490,7 @@ I830AllocateRotatedBuffer(ScrnInfoPtr pScrn, int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->RotatedMem),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -555,7 +555,7 @@ I830AllocateRotated2Buffer(ScrnInfoPtr pScrn, int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->RotatedMem2),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -665,6 +665,7 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
memset(&(pI830->FrontBuffer2), 0, sizeof(pI830->FrontBuffer2));
pI830->FrontBuffer2.Key = -1;
#if 1 /* ROTATION */
pI830->FbMemBox2.x1 = 0;
pI830->FbMemBox2.x2 = pI830Ent->pScrn_2->displayWidth;
pI830->FbMemBox2.y1 = 0;
@ -672,6 +673,12 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualX;
else
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualY;
#else
pI830->FbMemBox2.x1 = 0;
pI830->FbMemBox2.x2 = pI830Ent->pScrn_2->displayWidth;
pI830->FbMemBox2.y1 = 0;
pI830->FbMemBox2.y2 = pI830Ent->pScrn_2->virtualY;
#endif
/*
* Calculate how much framebuffer memory to allocate. For the
@ -723,19 +730,26 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI8302->allowPageFlip &&
IsTileable(pI830Ent->pScrn_2->displayWidth * pI8302->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
alignflags = 0;
}
#if 1 /* ROTATION */
if (pI830Ent->pScrn_2->virtualX > pI830Ent->pScrn_2->virtualY)
size = lineSize * (pI830Ent->pScrn_2->virtualX + cacheLines);
else
size = lineSize * (pI830Ent->pScrn_2->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#else
size = lineSize * (pI830Ent->pScrn_2->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sSecondary framebuffer allocation size: %ld kByte\n", s,
size / 1024);
@ -757,6 +771,7 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
memset(&(pI830->FrontBuffer), 0, sizeof(pI830->FrontBuffer));
pI830->FrontBuffer.Key = -1;
#if 1 /* ROTATION */
pI830->FbMemBox.x1 = 0;
pI830->FbMemBox.x2 = pScrn->displayWidth;
pI830->FbMemBox.y1 = 0;
@ -764,6 +779,12 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
pI830->FbMemBox.y2 = pScrn->virtualX;
else
pI830->FbMemBox.y2 = pScrn->virtualY;
#else
pI830->FbMemBox.x1 = 0;
pI830->FbMemBox.x2 = pScrn->displayWidth;
pI830->FbMemBox.y1 = 0;
pI830->FbMemBox.y2 = pScrn->virtualY;
#endif
/*
* Calculate how much framebuffer memory to allocate. For the
@ -815,19 +836,26 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
IsTileable(pScrn->displayWidth * pI830->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
alignflags = 0;
}
#if 1 /* ROTATION */
if (pScrn->virtualX > pScrn->virtualY)
size = lineSize * (pScrn->virtualX + cacheLines);
else
size = lineSize * (pScrn->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#else
size = lineSize * (pScrn->virtualY + cacheLines);
size = ROUND_TO_PAGE(size);
#endif
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sInitial framebuffer allocation size: %ld kByte\n", s,
size / 1024);
@ -901,7 +929,10 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
IsTileable(pScrn->displayWidth * pI830->cpp);
if (tileable) {
align = KB(512);
if (IS_I9XX(pI830))
align = MB(1);
else
align = KB(512);
alignflags = ALIGN_BOTH_ENDS;
} else {
align = KB(64);
@ -1132,7 +1163,7 @@ I830AllocateBackBuffer(ScrnInfoPtr pScrn, const int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->BackBuffer),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -1195,7 +1226,7 @@ I830AllocateDepthBuffer(ScrnInfoPtr pScrn, const int flags)
alloced = 0;
if (tileable) {
align = GetBestTileAlignment(size);
for (align = GetBestTileAlignment(size); align >= KB(512); align >>= 1) {
for (align = GetBestTileAlignment(size); align >= (IS_I9XX(pI830) ? MB(1) : KB(512)); align >>= 1) {
alloced = I830AllocVidMem(pScrn, &(pI830->DepthBuffer),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP |
@ -1629,7 +1660,7 @@ SetFence(ScrnInfoPtr pScrn, int nr, unsigned int start, unsigned int pitch,
}
static Bool
MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem)
MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem, unsigned int fence)
{
I830Ptr pI830 = I830PTR(pScrn);
int pitch, ntiles, i;
@ -1647,6 +1678,31 @@ MakeTiles(ScrnInfoPtr pScrn, I830MemRange *pMem)
}
pitch = pScrn->displayWidth * pI830->cpp;
if (IS_I965G(pI830)) {
I830RegPtr i830Reg = &pI830->ModeReg;
switch (fence) {
case FENCE_XMAJOR:
i830Reg->Fence[nextTile] = (((pitch / 128) - 1) << 2) | pMem->Start | 1;
break;
case FENCE_YMAJOR:
/* YMajor can be 128B aligned but the current code dictates
* otherwise. This isn't a problem apart from memory waste.
* FIXME */
i830Reg->Fence[nextTile] = (((pitch / 128) - 1) << 2) | pMem->Start | 1;
i830Reg->Fence[nextTile] |= (1<<1);
break;
default:
case FENCE_LINEAR:
break;
}
i830Reg->Fence[nextTile+FENCE_NEW_NR] = pMem->End;
nextTile++;
return TRUE;
}
/*
* Simply try to break the region up into at most four pieces of size
* equal to the alignment.
@ -1688,20 +1744,27 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
return;
}
pI830->front_tiled = FENCE_LINEAR;
pI830->back_tiled = FENCE_LINEAR;
pI830->depth_tiled = FENCE_LINEAR;
pI830->rotated_tiled = FENCE_LINEAR;
pI830->rotated2_tiled = FENCE_LINEAR;
if (pI830->allowPageFlip) {
if (pI830->allowPageFlip && pI830->FrontBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->FrontBuffer))) {
if (MakeTiles(pScrn, &(pI830->FrontBuffer), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the FRONT buffer\n");
"Activating tiled memory for the front buffer\n");
pI830->front_tiled = FENCE_XMAJOR;
} else {
pI830->allowPageFlip = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the FRONT buffer\n");
"MakeTiles failed for the front buffer\n");
}
} else {
pI830->allowPageFlip = FALSE;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Alignment bad for the FRONT buffer\n");
"Alignment bad for the front buffer\n");
}
}
@ -1712,9 +1775,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
* value.
*/
if (pI830->BackBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->BackBuffer))) {
if (MakeTiles(pScrn, &(pI830->BackBuffer), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the back buffer.\n");
pI830->back_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the back buffer.\n");
@ -1723,9 +1787,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
}
if (pI830->DepthBuffer.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->DepthBuffer))) {
if (MakeTiles(pScrn, &(pI830->DepthBuffer), FENCE_YMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the depth buffer.\n");
"Activating tiled memory for the depth buffer.\n");
pI830->depth_tiled = FENCE_YMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the depth buffer.\n");
@ -1733,9 +1798,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
}
if (pI830->RotatedMem.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem))) {
if (MakeTiles(pScrn, &(pI830->RotatedMem), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the rotated buffer.\n");
pI830->rotated_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the rotated buffer.\n");
@ -1744,9 +1810,10 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
#if 0
if (pI830->RotatedMem2.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem2))) {
if (MakeTiles(pScrn, &(pI830->RotatedMem2), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Activating tiled memory for the rotated2 buffer.\n");
pI830->rotated2_tiled = FENCE_XMAJOR;
} else {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"MakeTiles failed for the rotated buffer.\n");

637
src/i830_reg.h Normal file
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@ -0,0 +1,637 @@
/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifndef _I830_REG_H_
#define _I830_REG_H_
#define I830_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value)
#define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24))
#define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16)
#define AA_LINE_ECAAR_WIDTH_0_5 0
#define AA_LINE_ECAAR_WIDTH_1_0 (1<<14)
#define AA_LINE_ECAAR_WIDTH_2_0 (2<<14)
#define AA_LINE_ECAAR_WIDTH_4_0 (3<<14)
#define AA_LINE_REGION_WIDTH_ENABLE (1<<8)
#define AA_LINE_REGION_WIDTH_0_5 0
#define AA_LINE_REGION_WIDTH_1_0 (1<<6)
#define AA_LINE_REGION_WIDTH_2_0 (2<<6)
#define AA_LINE_REGION_WIDTH_4_0 (3<<6)
#define AA_LINE_ENABLE ((1<<1) | 1)
#define AA_LINE_DISABLE (1<<1)
#define _3DSTATE_BUF_INFO_CMD (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1)
/* Dword 1 */
#define BUF_3D_ID_COLOR_BACK (0x3<<24)
#define BUF_3D_ID_DEPTH (0x7<<24)
#define BUF_3D_USE_FENCE (1<<23)
#define BUF_3D_TILED_SURFACE (1<<22)
#define BUF_3D_TILE_WALK_X 0
#define BUF_3D_TILE_WALK_Y (1<<21)
#define BUF_3D_PITCH(x) (((x)/4)<<2)
/* Dword 2 */
#define BUF_3D_ADDR(x) ((x) & ~0x3)
#define _3DSTATE_COLOR_FACTOR_CMD (CMD_3D | (0x1d<<24) | (0x1<<16))
#define _3DSTATE_COLOR_FACTOR_N_CMD(stage) (CMD_3D | (0x1d<<24) | \
((0x90+(stage))<<16))
#define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16))
#define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16))
#define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16))
#define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16))
#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16))
/* Dword 1 */
#define DSTORG_HORT_BIAS(x) ((x)<<20)
#define DSTORG_VERT_BIAS(x) ((x)<<16)
#define COLOR_4_2_2_CHNL_WRT_ALL 0
#define COLOR_4_2_2_CHNL_WRT_Y (1<<12)
#define COLOR_4_2_2_CHNL_WRT_CR (2<<12)
#define COLOR_4_2_2_CHNL_WRT_CB (3<<12)
#define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12)
#define COLR_BUF_8BIT 0
#define COLR_BUF_RGB555 (1<<8)
#define COLR_BUF_RGB565 (2<<8)
#define COLR_BUF_ARGB8888 (3<<8)
#define DEPTH_IS_Z 0
#define DEPTH_IS_W (1<<6)
#define DEPTH_FRMT_16_FIXED 0
#define DEPTH_FRMT_16_FLOAT (1<<2)
#define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2)
#define DEPTH_FRMT_24_FLOAT_8_OTHER (3<<2)
#define VERT_LINE_STRIDE_1 (1<<1)
#define VERT_LINE_STRIDE_0 0
#define VERT_LINE_STRIDE_OFS_1 1
#define VERT_LINE_STRIDE_OFS_0 0
#define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3)
/* Dword 1 */
#define DRAW_RECT_DIS_DEPTH_OFS (1<<30)
#define DRAW_DITHER_OFS_X(x) ((x)<<26)
#define DRAW_DITHER_OFS_Y(x) ((x)<<24)
/* Dword 2 */
#define DRAW_YMIN(x) ((x)<<16)
#define DRAW_XMIN(x) (x)
/* Dword 3 */
#define DRAW_YMAX(x) ((x)<<16)
#define DRAW_XMAX(x) (x)
/* Dword 4 */
#define DRAW_YORG(x) ((x)<<16)
#define DRAW_XORG(x) (x)
#define _3DSTATE_ENABLES_1_CMD (CMD_3D|(0x3<<24))
#define ENABLE_LOGIC_OP_MASK ((1<<23)|(1<<22))
#define ENABLE_LOGIC_OP ((1<<23)|(1<<22))
#define DISABLE_LOGIC_OP (1<<23)
#define ENABLE_STENCIL_TEST ((1<<21)|(1<<20))
#define DISABLE_STENCIL_TEST (1<<21)
#define ENABLE_DEPTH_BIAS ((1<<11)|(1<<10))
#define DISABLE_DEPTH_BIAS (1<<11)
#define ENABLE_SPEC_ADD_MASK ((1<<9)|(1<<8))
#define ENABLE_SPEC_ADD ((1<<9)|(1<<8))
#define DISABLE_SPEC_ADD (1<<9)
#define ENABLE_DIS_FOG_MASK ((1<<7)|(1<<6))
#define ENABLE_FOG ((1<<7)|(1<<6))
#define DISABLE_FOG (1<<7)
#define ENABLE_DIS_ALPHA_TEST_MASK ((1<<5)|(1<<4))
#define ENABLE_ALPHA_TEST ((1<<5)|(1<<4))
#define DISABLE_ALPHA_TEST (1<<5)
#define ENABLE_DIS_CBLEND_MASK ((1<<3)|(1<<2))
#define ENABLE_COLOR_BLEND ((1<<3)|(1<<2))
#define DISABLE_COLOR_BLEND (1<<3)
#define ENABLE_DIS_DEPTH_TEST_MASK ((1<<1)|1)
#define ENABLE_DEPTH_TEST ((1<<1)|1)
#define DISABLE_DEPTH_TEST (1<<1)
/* _3DSTATE_ENABLES_2, p138 */
#define _3DSTATE_ENABLES_2_CMD (CMD_3D|(0x4<<24))
#define ENABLE_STENCIL_WRITE ((1<<21)|(1<<20))
#define DISABLE_STENCIL_WRITE (1<<21)
#define ENABLE_TEX_CACHE ((1<<17)|(1<<16))
#define DISABLE_TEX_CACHE (1<<17)
#define ENABLE_DITHER ((1<<9)|(1<<8))
#define DISABLE_DITHER (1<<9)
#define ENABLE_COLOR_MASK (1<<10)
#define WRITEMASK_ALPHA (1<<7)
#define WRITEMASK_ALPHA_SHIFT 7
#define WRITEMASK_RED (1<<6)
#define WRITEMASK_RED_SHIFT 6
#define WRITEMASK_GREEN (1<<5)
#define WRITEMASK_GREEN_SHIFT 5
#define WRITEMASK_BLUE (1<<4)
#define WRITEMASK_BLUE_SHIFT 4
#define WRITEMASK_MASK ((1<<4)|(1<<5)|(1<<6)|(1<<7))
#define ENABLE_COLOR_WRITE ((1<<3)|(1<<2))
#define DISABLE_COLOR_WRITE (1<<3)
#define ENABLE_DIS_DEPTH_WRITE_MASK 0x3
#define ENABLE_DEPTH_WRITE ((1<<1)|1)
#define DISABLE_DEPTH_WRITE (1<<1)
/* _3DSTATE_FOG_COLOR, p139 */
#define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24))
#define FOG_COLOR_RED(x) ((x)<<16)
#define FOG_COLOR_GREEN(x) ((x)<<8)
#define FOG_COLOR_BLUE(x) (x)
/* _3DSTATE_FOG_MODE, p140 */
#define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2)
/* Dword 1 */
#define FOGFUNC_ENABLE (1<<31)
#define FOGFUNC_VERTEX 0
#define FOGFUNC_PIXEL_EXP (1<<28)
#define FOGFUNC_PIXEL_EXP2 (2<<28)
#define FOGFUNC_PIXEL_LINEAR (3<<28)
#define FOGSRC_INDEX_Z (1<<27)
#define FOGSRC_INDEX_W ((1<<27)|(1<<25))
#define FOG_LINEAR_CONST (1<<24)
#define FOG_CONST_1(x) ((x)<<4)
#define ENABLE_FOG_DENSITY (1<<23)
/* Dword 2 */
#define FOG_CONST_2(x) (x)
/* Dword 3 */
#define FOG_DENSITY(x) (x)
/* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p142 */
#define _3DSTATE_INDPT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24))
#define ENABLE_INDPT_ALPHA_BLEND ((1<<23)|(1<<22))
#define DISABLE_INDPT_ALPHA_BLEND (1<<23)
#define ALPHA_BLENDFUNC_MASK 0x3f0000
#define ENABLE_ALPHA_BLENDFUNC (1<<21)
#define ABLENDFUNC_ADD 0
#define ABLENDFUNC_SUB (1<<16)
#define ABLENDFUNC_RVSE_SUB (2<<16)
#define ABLENDFUNC_MIN (3<<16)
#define ABLENDFUNC_MAX (4<<16)
#define SRC_DST_ABLEND_MASK 0xfff
#define ENABLE_SRC_ABLEND_FACTOR (1<<11)
#define SRC_ABLEND_FACT(x) ((x)<<6)
#define ENABLE_DST_ABLEND_FACTOR (1<<5)
#define DST_ABLEND_FACT(x) (x)
/* _3DSTATE_MAP_BLEND_ARG, p152 */
#define _3DSTATE_MAP_BLEND_ARG_CMD(stage) (CMD_3D|(0x0e<<24)|((stage)<<20))
#define TEXPIPE_COLOR 0
#define TEXPIPE_ALPHA (1<<18)
#define TEXPIPE_KILL (2<<18)
#define TEXBLEND_ARG0 0
#define TEXBLEND_ARG1 (1<<15)
#define TEXBLEND_ARG2 (2<<15)
#define TEXBLEND_ARG3 (3<<15)
#define TEXBLENDARG_MODIFY_PARMS (1<<6)
#define TEXBLENDARG_REPLICATE_ALPHA (1<<5)
#define TEXBLENDARG_INV_ARG (1<<4)
#define TEXBLENDARG_ONE 0
#define TEXBLENDARG_FACTOR 0x01
#define TEXBLENDARG_ACCUM 0x02
#define TEXBLENDARG_DIFFUSE 0x03
#define TEXBLENDARG_SPEC 0x04
#define TEXBLENDARG_CURRENT 0x05
#define TEXBLENDARG_TEXEL0 0x06
#define TEXBLENDARG_TEXEL1 0x07
#define TEXBLENDARG_TEXEL2 0x08
#define TEXBLENDARG_TEXEL3 0x09
#define TEXBLENDARG_FACTOR_N 0x0e
/* _3DSTATE_MAP_BLEND_OP, p155 */
#define _3DSTATE_MAP_BLEND_OP_CMD(stage) (CMD_3D|(0x0d<<24)|((stage)<<20))
#if 0
# define TEXPIPE_COLOR 0
# define TEXPIPE_ALPHA (1<<18)
# define TEXPIPE_KILL (2<<18)
#endif
#define ENABLE_TEXOUTPUT_WRT_SEL (1<<17)
#define TEXOP_OUTPUT_CURRENT 0
#define TEXOP_OUTPUT_ACCUM (1<<15)
#define ENABLE_TEX_CNTRL_STAGE ((1<<12)|(1<<11))
#define DISABLE_TEX_CNTRL_STAGE (1<<12)
#define TEXOP_SCALE_SHIFT 9
#define TEXOP_SCALE_1X (0 << TEXOP_SCALE_SHIFT)
#define TEXOP_SCALE_2X (1 << TEXOP_SCALE_SHIFT)
#define TEXOP_SCALE_4X (2 << TEXOP_SCALE_SHIFT)
#define TEXOP_MODIFY_PARMS (1<<8)
#define TEXOP_LAST_STAGE (1<<7)
#define TEXBLENDOP_KILLPIXEL 0x02
#define TEXBLENDOP_ARG1 0x01
#define TEXBLENDOP_ARG2 0x02
#define TEXBLENDOP_MODULATE 0x03
#define TEXBLENDOP_ADD 0x06
#define TEXBLENDOP_ADDSIGNED 0x07
#define TEXBLENDOP_BLEND 0x08
#define TEXBLENDOP_BLEND_AND_ADD 0x09
#define TEXBLENDOP_SUBTRACT 0x0a
#define TEXBLENDOP_DOT3 0x0b
#define TEXBLENDOP_DOT4 0x0c
#define TEXBLENDOP_MODULATE_AND_ADD 0x0d
#define TEXBLENDOP_MODULATE_2X_AND_ADD 0x0e
#define TEXBLENDOP_MODULATE_4X_AND_ADD 0x0f
/* _3DSTATE_MAP_BUMP_TABLE, p160 TODO */
/* _3DSTATE_MAP_COLOR_CHROMA_KEY, p161 TODO */
#define _3DSTATE_MAP_COORD_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8c<<16))
#define DISABLE_TEX_TRANSFORM (1<<28)
#define TEXTURE_SET(x) (x<<29)
#define _3DSTATE_VERTEX_TRANSFORM ((3<<29)|(0x1d<<24)|(0x8b<<16))
#define DISABLE_VIEWPORT_TRANSFORM (1<<31)
#define DISABLE_PERSPECTIVE_DIVIDE (1<<29)
/* _3DSTATE_MAP_COORD_SET_BINDINGS, p162 */
#define _3DSTATE_MAP_COORD_SETBIND_CMD (CMD_3D|(0x1d<<24)|(0x02<<16))
#define TEXBIND_MASK3 ((1<<15)|(1<<14)|(1<<13)|(1<<12))
#define TEXBIND_MASK2 ((1<<11)|(1<<10)|(1<<9)|(1<<8))
#define TEXBIND_MASK1 ((1<<7)|(1<<6)|(1<<5)|(1<<4))
#define TEXBIND_MASK0 ((1<<3)|(1<<2)|(1<<1)|1)
#define TEXBIND_SET3(x) ((x)<<12)
#define TEXBIND_SET2(x) ((x)<<8)
#define TEXBIND_SET1(x) ((x)<<4)
#define TEXBIND_SET0(x) (x)
#define TEXCOORDSRC_KEEP 0
#define TEXCOORDSRC_DEFAULT 0x01
#define TEXCOORDSRC_VTXSET_0 0x08
#define TEXCOORDSRC_VTXSET_1 0x09
#define TEXCOORDSRC_VTXSET_2 0x0a
#define TEXCOORDSRC_VTXSET_3 0x0b
#define TEXCOORDSRC_VTXSET_4 0x0c
#define TEXCOORDSRC_VTXSET_5 0x0d
#define TEXCOORDSRC_VTXSET_6 0x0e
#define TEXCOORDSRC_VTXSET_7 0x0f
#define MAP_UNIT(unit) ((unit)<<16)
#define MAP_UNIT_MASK (0x7<<16)
/* _3DSTATE_MAP_COORD_SETS, p164 */
#define _3DSTATE_MAP_COORD_SET_CMD (CMD_3D|(0x1c<<24)|(0x01<<19))
#define ENABLE_TEXCOORD_PARAMS (1<<15)
#define TEXCOORDS_ARE_NORMAL (1<<14)
#define TEXCOORDS_ARE_IN_TEXELUNITS 0
#define TEXCOORDTYPE_CARTESIAN 0
#define TEXCOORDTYPE_HOMOGENEOUS (1<<11)
#define TEXCOORDTYPE_VECTOR (2<<11)
#define TEXCOORDTYPE_MASK (0x7<<11)
#define ENABLE_ADDR_V_CNTL (1<<7)
#define ENABLE_ADDR_U_CNTL (1<<3)
#define TEXCOORD_ADDR_V_MODE(x) ((x)<<4)
#define TEXCOORD_ADDR_U_MODE(x) (x)
#define TEXCOORDMODE_WRAP 0
#define TEXCOORDMODE_MIRROR 1
#define TEXCOORDMODE_CLAMP 2
#define TEXCOORDMODE_WRAP_SHORTEST 3
#define TEXCOORDMODE_CLAMP_BORDER 4
#define TEXCOORD_ADDR_V_MASK 0x70
#define TEXCOORD_ADDR_U_MASK 0x7
/* _3DSTATE_MAP_CUBE, p168 TODO */
#define _3DSTATE_MAP_CUBE (CMD_3D|(0x1c<<24)|(0x0a<<19))
#define CUBE_NEGX_ENABLE (1<<5)
#define CUBE_POSX_ENABLE (1<<4)
#define CUBE_NEGY_ENABLE (1<<3)
#define CUBE_POSY_ENABLE (1<<2)
#define CUBE_NEGZ_ENABLE (1<<1)
#define CUBE_POSZ_ENABLE (1<<0)
/* _3DSTATE_MODES_1, p190 */
#define _3DSTATE_MODES_1_CMD (CMD_3D|(0x08<<24))
#define BLENDFUNC_MASK 0x3f0000
#define ENABLE_COLR_BLND_FUNC (1<<21)
#define BLENDFUNC_ADD 0
#define BLENDFUNC_SUB (1<<16)
#define BLENDFUNC_RVRSE_SUB (2<<16)
#define BLENDFUNC_MIN (3<<16)
#define BLENDFUNC_MAX (4<<16)
#define SRC_DST_BLND_MASK 0xfff
#define ENABLE_SRC_BLND_FACTOR (1<<11)
#define ENABLE_DST_BLND_FACTOR (1<<5)
#define SRC_BLND_FACT(x) ((x)<<6)
#define DST_BLND_FACT(x) (x)
/* _3DSTATE_MODES_2, p192 */
#define _3DSTATE_MODES_2_CMD (CMD_3D|(0x0f<<24))
#define ENABLE_GLOBAL_DEPTH_BIAS (1<<22)
#define GLOBAL_DEPTH_BIAS(x) ((x)<<14)
#define ENABLE_ALPHA_TEST_FUNC (1<<13)
#define ENABLE_ALPHA_REF_VALUE (1<<8)
#define ALPHA_TEST_FUNC(x) ((x)<<9)
#define ALPHA_REF_VALUE(x) (x)
#define ALPHA_TEST_REF_MASK 0x3fff
/* _3DSTATE_MODES_3, p193 */
#define _3DSTATE_MODES_3_CMD (CMD_3D|(0x02<<24))
#define DEPTH_TEST_FUNC_MASK 0x1f0000
#define ENABLE_DEPTH_TEST_FUNC (1<<20)
/* Uses COMPAREFUNC */
#define DEPTH_TEST_FUNC(x) ((x)<<16)
#define ENABLE_ALPHA_SHADE_MODE (1<<11)
#define ENABLE_FOG_SHADE_MODE (1<<9)
#define ENABLE_SPEC_SHADE_MODE (1<<7)
#define ENABLE_COLOR_SHADE_MODE (1<<5)
#define ALPHA_SHADE_MODE(x) ((x)<<10)
#define FOG_SHADE_MODE(x) ((x)<<8)
#define SPEC_SHADE_MODE(x) ((x)<<6)
#define COLOR_SHADE_MODE(x) ((x)<<4)
#define CULLMODE_MASK 0xf
#define ENABLE_CULL_MODE (1<<3)
#define CULLMODE_BOTH 0
#define CULLMODE_NONE 1
#define CULLMODE_CW 2
#define CULLMODE_CCW 3
#define SHADE_MODE_LINEAR 0
#define SHADE_MODE_FLAT 0x1
/* _3DSTATE_MODES_4, p195 */
#define _3DSTATE_MODES_4_CMD (CMD_3D|(0x16<<24))
#define ENABLE_LOGIC_OP_FUNC (1<<23)
#define LOGIC_OP_FUNC(x) ((x)<<18)
#define LOGICOP_MASK ((1<<18)|(1<<19)|(1<<20)|(1<<21))
#define LOGICOP_CLEAR 0
#define LOGICOP_NOR 0x1
#define LOGICOP_AND_INV 0x2
#define LOGICOP_COPY_INV 0x3
#define LOGICOP_AND_RVRSE 0x4
#define LOGICOP_INV 0x5
#define LOGICOP_XOR 0x6
#define LOGICOP_NAND 0x7
#define LOGICOP_AND 0x8
#define LOGICOP_EQUIV 0x9
#define LOGICOP_NOOP 0xa
#define LOGICOP_OR_INV 0xb
#define LOGICOP_COPY 0xc
#define LOGICOP_OR_RVRSE 0xd
#define LOGICOP_OR 0xe
#define LOGICOP_SET 0xf
#define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00))
#define ENABLE_STENCIL_TEST_MASK (1<<17)
#define STENCIL_TEST_MASK(x) ((x)<<8)
#define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff))
#define ENABLE_STENCIL_WRITE_MASK (1<<16)
#define STENCIL_WRITE_MASK(x) ((x)&0xff)
/* _3DSTATE_MODES_5, p196 */
#define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24))
#define ENABLE_SPRITE_POINT_TEX (1<<23)
#define SPRITE_POINT_TEX_ON (1<<22)
#define SPRITE_POINT_TEX_OFF 0
#define FLUSH_RENDER_CACHE (1<<18)
#define FLUSH_TEXTURE_CACHE (1<<16)
#define FIXED_LINE_WIDTH_MASK 0xfc00
#define ENABLE_FIXED_LINE_WIDTH (1<<15)
#define FIXED_LINE_WIDTH(x) ((x)<<10)
#define FIXED_POINT_WIDTH_MASK 0x3ff
#define ENABLE_FIXED_POINT_WIDTH (1<<9)
#define FIXED_POINT_WIDTH(x) (x)
/* _3DSTATE_RASTERIZATION_RULES, p198 */
#define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24))
#define ENABLE_POINT_RASTER_RULE (1<<15)
#define OGL_POINT_RASTER_RULE (1<<13)
#define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8)
#define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5)
#define ENABLE_TRI_STRIP_PROVOKE_VRTX (1<<2)
#define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6)
#define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3)
#define TRI_STRIP_PROVOKE_VRTX(x) (x)
/* _3DSTATE_SCISSOR_ENABLE, p200 */
#define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19))
#define ENABLE_SCISSOR_RECT ((1<<1) | 1)
#define DISABLE_SCISSOR_RECT (1<<1)
/* _3DSTATE_SCISSOR_RECTANGLE_0, p201 */
#define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1)
/* Dword 1 */
#define SCISSOR_RECT_0_YMIN(x) ((x)<<16)
#define SCISSOR_RECT_0_XMIN(x) (x)
/* Dword 2 */
#define SCISSOR_RECT_0_YMAX(x) ((x)<<16)
#define SCISSOR_RECT_0_XMAX(x) (x)
/* _3DSTATE_STENCIL_TEST, p202 */
#define _3DSTATE_STENCIL_TEST_CMD (CMD_3D|(0x09<<24))
#define ENABLE_STENCIL_PARMS (1<<23)
#define STENCIL_OPS_MASK (0xffc000)
#define STENCIL_FAIL_OP(x) ((x)<<20)
#define STENCIL_PASS_DEPTH_FAIL_OP(x) ((x)<<17)
#define STENCIL_PASS_DEPTH_PASS_OP(x) ((x)<<14)
#define ENABLE_STENCIL_TEST_FUNC_MASK ((1<<13)|(1<<12)|(1<<11)|(1<<10)|(1<<9))
#define ENABLE_STENCIL_TEST_FUNC (1<<13)
/* Uses COMPAREFUNC */
#define STENCIL_TEST_FUNC(x) ((x)<<9)
#define STENCIL_REF_VALUE_MASK ((1<<8)|0xff)
#define ENABLE_STENCIL_REF_VALUE (1<<8)
#define STENCIL_REF_VALUE(x) (x)
/* _3DSTATE_VERTEX_FORMAT, p204 */
#define _3DSTATE_VFT0_CMD (CMD_3D|(0x05<<24))
#define VFT0_POINT_WIDTH (1<<12)
#define VFT0_TEX_COUNT_MASK (7<<8)
#define VFT0_TEX_COUNT_SHIFT 8
#define VFT0_TEX_COUNT(x) ((x)<<8)
#define VFT0_SPEC (1<<7)
#define VFT0_DIFFUSE (1<<6)
#define VFT0_DEPTH_OFFSET (1<<5)
#define VFT0_XYZ (1<<1)
#define VFT0_XYZW (2<<1)
#define VFT0_XY (3<<1)
#define VFT0_XYW (4<<1)
#define VFT0_XYZW_MASK (7<<1)
/* _3DSTATE_VERTEX_FORMAT_2, p206 */
#define _3DSTATE_VFT1_CMD (CMD_3D|(0x0a<<24))
#define VFT1_TEX7_FMT(x) ((x)<<14)
#define VFT1_TEX6_FMT(x) ((x)<<12)
#define VFT1_TEX5_FMT(x) ((x)<<10)
#define VFT1_TEX4_FMT(x) ((x)<<8)
#define VFT1_TEX3_FMT(x) ((x)<<6)
#define VFT1_TEX2_FMT(x) ((x)<<4)
#define VFT1_TEX1_FMT(x) ((x)<<2)
#define VFT1_TEX0_FMT(x) (x)
#define VFT1_TEX0_MASK 3
#define VFT1_TEX1_SHIFT 2
#define TEXCOORDFMT_2D 0
#define TEXCOORDFMT_3D 1
#define TEXCOORDFMT_4D 2
#define TEXCOORDFMT_1D 3
/*New stuff picked up along the way */
#define MLC_LOD_BIAS_MASK ((1<<7)-1)
/* _3DSTATE_VERTEX_TRANSFORM, p207 */
#define _3DSTATE_VERTEX_TRANS_CMD (CMD_3D|(0x1d<<24)|(0x8b<<16)|0)
#define _3DSTATE_VERTEX_TRANS_MTX_CMD (CMD_3D|(0x1d<<24)|(0x8b<<16)|6)
/* Dword 1 */
#define ENABLE_VIEWPORT_TRANSFORM ((1<<31)|(1<<30))
#define DISABLE_VIEWPORT_TRANSFORM (1<<31)
#define ENABLE_PERSP_DIVIDE ((1<<29)|(1<<28))
#define DISABLE_PERSP_DIVIDE (1<<29)
#define VRTX_TRANS_LOAD_MATRICES 0x7421
#define VRTX_TRANS_NO_LOAD_MATRICES 0x0000
/* Dword 2 -> 7 are matrix elements */
/* _3DSTATE_W_STATE, p209 */
#define _3DSTATE_W_STATE_CMD (CMD_3D|(0x1d<<24)|(0x8d<<16)|1)
/* Dword 1 */
#define MAGIC_W_STATE_DWORD1 0x00000008
/* Dword 2 */
#define WFAR_VALUE(x) (x)
/* Stipple command, carried over from the i810, apparently:
*/
#define _3DSTATE_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define ST1_ENABLE (1<<16)
#define ST1_MASK (0xffff)
#define _3DSTATE_LOAD_STATE_IMMEDIATE_2 ((0x3<<29)|(0x1d<<24)|(0x03<<16))
#define LOAD_TEXTURE_MAP0 (1<<11)
#define LOAD_GLOBAL_COLOR_FACTOR (1<<6)
#define TM0S0_ADDRESS_MASK 0xfffffffc
#define TM0S0_USE_FENCE (1<<1)
#define TM0S1_HEIGHT_SHIFT 21
#define TM0S1_WIDTH_SHIFT 10
#define TM0S1_PALETTE_SELECT (1<<9)
#define TM0S1_MAPSURF_FORMAT_MASK (0x7 << 6)
#define TM0S1_MAPSURF_FORMAT_SHIFT 6
#define MAPSURF_8BIT_INDEXED (0<<6)
#define MAPSURF_8BIT (1<<6)
#define MAPSURF_16BIT (2<<6)
#define MAPSURF_32BIT (3<<6)
#define MAPSURF_411 (4<<6)
#define MAPSURF_422 (5<<6)
#define MAPSURF_COMPRESSED (6<<6)
#define MAPSURF_4BIT_INDEXED (7<<6)
#define TM0S1_MT_FORMAT_MASK (0x7 << 3)
#define TM0S1_MT_FORMAT_SHIFT 3
#define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */
#define MT_8BIT_IDX_RGB565 (0<<3) /* SURFACE_8BIT_INDEXED */
#define MT_8BIT_IDX_ARGB1555 (1<<3)
#define MT_8BIT_IDX_ARGB4444 (2<<3)
#define MT_8BIT_IDX_AY88 (3<<3)
#define MT_8BIT_IDX_ABGR8888 (4<<3)
#define MT_8BIT_IDX_BUMP_88DVDU (5<<3)
#define MT_8BIT_IDX_BUMP_655LDVDU (6<<3)
#define MT_8BIT_IDX_ARGB8888 (7<<3)
#define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */
#define MT_8BIT_L8 (1<<3)
#define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */
#define MT_16BIT_ARGB1555 (1<<3)
#define MT_16BIT_ARGB4444 (2<<3)
#define MT_16BIT_AY88 (3<<3)
#define MT_16BIT_DIB_ARGB1555_8888 (4<<3)
#define MT_16BIT_BUMP_88DVDU (5<<3)
#define MT_16BIT_BUMP_655LDVDU (6<<3)
#define MT_16BIT_DIB_RGB565_8888 (7<<3)
#define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */
#define MT_32BIT_ABGR8888 (1<<3)
#define MT_32BIT_BUMP_XLDVDU_8888 (6<<3)
#define MT_32BIT_DIB_8888 (7<<3)
#define MT_411_YUV411 (0<<3) /* SURFACE_411 */
#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */
#define MT_422_YCRCB_NORMAL (1<<3)
#define MT_422_YCRCB_SWAPUV (2<<3)
#define MT_422_YCRCB_SWAPUVY (3<<3)
#define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */
#define MT_COMPRESS_DXT2_3 (1<<3)
#define MT_COMPRESS_DXT4_5 (2<<3)
#define MT_COMPRESS_FXT1 (3<<3)
#define TM0S1_COLORSPACE_CONVERSION (1 << 2)
#define TM0S1_TILED_SURFACE (1 << 1)
#define TM0S1_TILE_WALK (1 << 0)
#define TM0S2_PITCH_SHIFT 21
#define TM0S2_CUBE_FACE_ENA_SHIFT 15
#define TM0S2_CUBE_FACE_ENA_MASK (1<<15)
#define TM0S2_MAP_FORMAT (1<<14)
#define TM0S2_VERTICAL_LINE_STRIDE (1<<13)
#define TM0S2_VERITCAL_LINE_STRIDE_OFF (1<<12)
#define TM0S2_OUTPUT_CHAN_SHIFT 10
#define TM0S2_OUTPUT_CHAN_MASK (3<<10)
#define TM0S3_MIP_FILTER_MASK (0x3<<30)
#define TM0S3_MIP_FILTER_SHIFT 30
#define MIPFILTER_NONE 0
#define MIPFILTER_NEAREST 1
#define MIPFILTER_LINEAR 3
#define TM0S3_MAG_FILTER_MASK (0x3<<28)
#define TM0S3_MAG_FILTER_SHIFT 28
#define TM0S3_MIN_FILTER_MASK (0x3<<26)
#define TM0S3_MIN_FILTER_SHIFT 26
#define FILTER_NEAREST 0
#define FILTER_LINEAR 1
#define FILTER_ANISOTROPIC 2
#define TM0S3_LOD_BIAS_SHIFT 17
#define TM0S3_LOD_BIAS_MASK (0x1ff<<17)
#define TM0S3_MAX_MIP_SHIFT 9
#define TM0S3_MAX_MIP_MASK (0xff<<9)
#define TM0S3_MIN_MIP_SHIFT 3
#define TM0S3_MIN_MIP_MASK (0x3f<<3)
#define TM0S3_KILL_PIXEL (1<<2)
#define TM0S3_KEYED_FILTER (1<<1)
#define TM0S3_CHROMA_KEY (1<<0)
/* _3DSTATE_MAP_TEXEL_STREAM, p188 */
#define _3DSTATE_MAP_TEX_STREAM_CMD (CMD_3D|(0x1c<<24)|(0x05<<19))
#define DISABLE_TEX_STREAM_BUMP (1<<12)
#define ENABLE_TEX_STREAM_BUMP ((1<<12)|(1<<11))
#define TEX_MODIFY_UNIT_0 0
#define TEX_MODIFY_UNIT_1 (1<<8)
#define ENABLE_TEX_STREAM_COORD_SET (1<<7)
#define TEX_STREAM_COORD_SET(x) ((x)<<4)
#define ENABLE_TEX_STREAM_MAP_IDX (1<<3)
#define TEX_STREAM_MAP_IDX(x) (x)
#define FLUSH_MAP_CACHE (1<<0)
#endif

215
src/i830_rotate.c
View File

@ -1,3 +1,4 @@
/* -*- c-basic-offset: 3 -*- */
/**************************************************************************
Copyright 2005 Tungsten Graphics, Inc., Cedar Park, Texas.
@ -57,6 +58,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "shadow.h"
#include "i830.h"
#include "i915_reg.h"
#include "i915_3d.h"
#ifdef XF86DRI
#include "dri.h"
@ -259,93 +262,138 @@ I915UpdateRotate (ScreenPtr pScreen,
#endif
if (updateInvarient) {
FS_LOCALS(3);
*pI830->used3D = pScrn->scrnIndex;
#ifdef XF86DRI
if (sarea)
sarea->ctxOwner = myContext;
#endif
BEGIN_LP_RING(64);
BEGIN_LP_RING(54);
/* invarient state */
OUT_RING(MI_NOOP);
OUT_RING(0x66014140);
OUT_RING(0x7d990000);
OUT_RING(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE | AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_RING(0x00000000);
OUT_RING(0x7d9a0000);
OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
OUT_RING(0x00000000);
OUT_RING(0x7d980000);
OUT_RING(_3DSTATE_DFLT_Z_CMD);
OUT_RING(0x00000000);
OUT_RING(0x76fac688);
OUT_RING(0x6700a770);
OUT_RING(0x7d040081);
OUT_RING(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) | CSB_TCB(1, 1) |
CSB_TCB(2, 2) | CSB_TCB(3, 3) |
CSB_TCB(4, 4) | CSB_TCB(5, 5) |
CSB_TCB(6, 6) | CSB_TCB(7, 7));
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_TRI_FAN_PROVOKE_VRTX | TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_LINE_STRIP_PROVOKE_VRTX | LINE_STRIP_PROVOKE_VRTX(1) |
ENABLE_TEXKILL_3D_4D | TEXKILL_4D |
ENABLE_POINT_RASTER_RULE | OGL_POINT_RASTER_RULE);
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 1);
OUT_RING(0x00000000);
/* flush map & render cache */
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
/* draw rect */
OUT_RING(0x7d800003);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING((pScrn->virtualX - 1) | (pScrn->virtualY - 1) << 16);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
/* scissor */
OUT_RING(0x7c800002);
OUT_RING(0x7d810001);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(0x7c000003);
OUT_RING(_3DSTATE_DRAW_RECT_CMD);
OUT_RING(DRAW_DITHER_OFS_X(0) | DRAW_DITHER_OFS_Y(0));
OUT_RING(DRAW_XMIN(0) | DRAW_YMIN(0));
OUT_RING(DRAW_XMAX(pScrn->virtualX - 1) |
DRAW_YMAX(pScrn->virtualY - 1));
OUT_RING(DRAW_XORG(0) | DRAW_YORG(0));
OUT_RING(MI_NOOP);
OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING(0x00000000); /* ymax, xmax */
OUT_RING(0x7c000003); /* XXX: magic numbers */
OUT_RING(0x7d070000);
OUT_RING(0x00000000);
OUT_RING(0x68000002);
/* context setup */
OUT_RING(0x6db3ffff);
OUT_RING(0x7d040744);
OUT_RING(0xfffffff0);
OUT_RING(0x00902c80);
OUT_RING(_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
MODE4_ENABLE_STENCIL_WRITE_MASK |
MODE4_ENABLE_STENCIL_TEST_MASK);
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(2) | I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 4);
OUT_RING(S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D) |
S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT));
OUT_RING((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE | S4_VFMT_SPEC_FOG | S4_VFMT_COLOR |
S4_VFMT_XYZW);
OUT_RING(0x00000000); /* S5 -- enable bits */
OUT_RING((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
(2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
(1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
(2 << S6_TRISTRIP_PV_SHIFT));
OUT_RING(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR |
(BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR |
(BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
OUT_RING(0x00000000);
OUT_RING(0x00020216);
OUT_RING(0x6ba008a1);
OUT_RING(0x7d880000);
OUT_RING(0x00000000);
/* dv0 */
OUT_RING(0x7d850000);
/* dv1 */
if (pI830->cpp == 1)
OUT_RING(0x10880000);
else if (pI830->cpp == 2)
OUT_RING(0x10880200);
else
OUT_RING(0x10880308);
/* stipple */
OUT_RING(0x7d830000);
OUT_RING(0x00000000);
/* fragment program - texture blend replace*/
OUT_RING(0x7d050008);
OUT_RING(0x19180000);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(0x19083c00);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(0x15200000);
OUT_RING(0x01000000);
OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
if (pI830->cpp == 1) {
OUT_RING(LOD_PRECLAMP_OGL | DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) | COLR_BUF_8BIT);
} else if (pI830->cpp == 2) {
OUT_RING(LOD_PRECLAMP_OGL | DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) | COLR_BUF_RGB565);
} else {
OUT_RING(LOD_PRECLAMP_OGL | DSTORG_HORT_BIAS(0x8) |
DSTORG_VERT_BIAS(0x8) | COLR_BUF_ARGB8888 |
DEPTH_FRMT_24_FIXED_8_OTHER);
}
OUT_RING(_3DSTATE_STIPPLE);
OUT_RING(0x00000000);
/* texture sampler state */
OUT_RING(0x7d010003);
OUT_RING(_3DSTATE_SAMPLER_STATE | 3);
OUT_RING(0x00000001);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
/* front buffer, pitch, offset */
OUT_RING(0x7d8e0001);
OUT_RING(0x03800000 | (((pI830->displayWidth * pI830->cpp) / 4) << 2));
OUT_RING(_3DSTATE_BUF_INFO_CMD);
OUT_RING(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
BUF_3D_PITCH(pI830->displayWidth * pI830->cpp));
if (I830IsPrimary(pScrn))
OUT_RING(pI830->FrontBuffer.Start);
else
OUT_RING(pI8301->FrontBuffer2.Start);
/* Set the entire frontbuffer up as a texture */
OUT_RING(0x7d000003);
OUT_RING(_3DSTATE_MAP_STATE | 3);
OUT_RING(0x00000001);
if (I830IsPrimary(pScrn))
@ -356,18 +404,25 @@ I915UpdateRotate (ScreenPtr pScreen,
if (pI830->disableTiling)
use_fence = 0;
else
use_fence = 4;
use_fence = MS3_USE_FENCE_REGS;
if (pI830->cpp == 1)
use_fence |= 0x80; /* MAPSURF_8BIT */
use_fence |= MAPSURF_8BIT;
else
if (pI830->cpp == 2)
use_fence |= 0x100; /* MAPSURF_16BIT */
use_fence |= MAPSURF_16BIT;
else
use_fence |= 0x180; /* MAPSURF_32BIT */
use_fence |= MAPSURF_32BIT;
OUT_RING(use_fence | (pScreen->height - 1) << 21 | (pScreen->width - 1) << 10);
OUT_RING(((((pScrn->displayWidth * pI830->cpp) / 4) - 1) << 21));
ADVANCE_LP_RING();
/* fragment program - texture blend replace*/
FS_BEGIN();
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_T0);
i915_fs_texld(FS_OC, FS_S0, FS_T0);
FS_END();
}
{
@ -395,7 +450,7 @@ I915UpdateRotate (ScreenPtr pScreen,
OUT_RING(MI_NOOP);
/* vertex data */
OUT_RING(0x7f0c001f);
OUT_RING(PRIM3D_INLINE | PRIM3D_TRIFAN | (32 - 1));
verts[0][0] = box_x1; verts[0][1] = box_y1;
verts[1][0] = box_x2; verts[1][1] = box_y1;
verts[2][0] = box_x2; verts[2][1] = box_y2;
@ -520,15 +575,15 @@ I830UpdateRotate (ScreenPtr pScreen,
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
/* draw rect */
OUT_RING(0x7d800003);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING((pScrn->virtualX - 1) | (pScrn->virtualY - 1) << 16);
OUT_RING(0x00000000);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DRAW_RECT_CMD);
OUT_RING(0x00000000); /* flags */
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING((pScrn->virtualX - 1) | (pScrn->virtualY - 1) << 16); /* ymax, xmax */
OUT_RING(0x00000000); /* yorigin, xorigin */
OUT_RING(MI_NOOP);
/* front buffer */
OUT_RING(0x7d8e0001);
OUT_RING(_3DSTATE_BUF_INFO_CMD);
OUT_RING(0x03800000 | (((pI830->displayWidth * pI830->cpp) / 4) << 2));
if (I830IsPrimary(pScrn))
OUT_RING(pI830->FrontBuffer.Start);
@ -574,9 +629,9 @@ I830UpdateRotate (ScreenPtr pScreen,
OUT_RING(pI8301->RotatedMem2.Start | use_fence);
if (pI830->cpp == 1)
OUT_RING(0x00 | (pScreen->height - 1) << 21 | (pScreen->width - 1) << 10);
else if (pI830->cpp == 2)
OUT_RING(0x40 | (pScreen->height - 1) << 21 | (pScreen->width - 1) << 10);
else if (pI830->cpp == 2)
OUT_RING(0x80 | (pScreen->height - 1) << 21 | (pScreen->width - 1) << 10);
else
OUT_RING(0xc0 | (pScreen->height - 1) << 21 | (pScreen->width - 1) << 10);
@ -681,12 +736,12 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
};
if (pI830->noAccel)
func = LoaderSymbol("shadowUpdateRotatePacked");
func = LoaderSymbol("shadowUpdateRotatePacked");
else
if (IS_I9XX(pI830))
func = I915UpdateRotate;
else
func = I830UpdateRotate;
if (IS_I9XX(pI830))
func = I915UpdateRotate;
else
func = I830UpdateRotate;
if (I830IsPrimary(pScrn)) {
pI8301 = pI830;
@ -716,6 +771,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
* We grab the DRI lock when reallocating buffers to avoid DRI clients
* getting bogus information.
*/
#ifdef XF86DRI
if (pI8301->directRenderingEnabled && reAllocate) {
didLock = I830DRILock(pScrn1);
@ -734,6 +790,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
}
}
if (pI8301->TexMem.Key != -1)
xf86UnbindGARTMemory(pScrn1->scrnIndex, pI8301->TexMem.Key);
I830FreeVidMem(pScrn1, &(pI8301->TexMem));
@ -836,7 +893,7 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
if (pI8301->rotation != RR_Rotate_0) {
if (!I830AllocateRotatedBuffer(pScrn1,
(pI8301->disableTiling ? ALLOC_NO_TILING : 0)))
pI8301->disableTiling ? ALLOC_NO_TILING : 0))
goto BAIL1;
I830FixOffset(pScrn1, &(pI8301->RotatedMem));
@ -848,8 +905,8 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
shadowRemove (pScrn->pScreen, NULL);
if (pI830->rotation != RR_Rotate_0)
shadowAdd (pScrn->pScreen,
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
if (I830IsPrimary(pScrn)) {
if (pI830->rotation != RR_Rotate_0)
@ -1045,7 +1102,7 @@ BAIL0:
if (pI8301->rotation != RR_Rotate_0) {
if (!I830AllocateRotatedBuffer(pScrn1,
(pI8301->disableTiling ? ALLOC_NO_TILING : 0)))
pI8301->disableTiling ? ALLOC_NO_TILING : 0))
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"Oh dear, the rotated buffer failed - badness\n");
@ -1057,8 +1114,8 @@ BAIL0:
shadowRemove (pScrn->pScreen, NULL);
if (pI830->rotation != RR_Rotate_0)
shadowAdd (pScrn->pScreen,
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
(*pScrn->pScreen->GetScreenPixmap) (pScrn->pScreen),
func, I830WindowLinear, pI830->rotation, 0);
if (I830IsPrimary(pScrn)) {
if (pI830->rotation != RR_Rotate_0)

1435
src/i830_video.c
View File

File diff suppressed because it is too large Load Diff

77
src/i830_video.h Normal file
View File

@ -0,0 +1,77 @@
/***************************************************************************
Copyright 2000 Intel Corporation. All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL INTEL, AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR
THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#include "xf86.h"
#include "xf86_OSproc.h"
typedef struct {
CARD32 YBuf0offset;
CARD32 UBuf0offset;
CARD32 VBuf0offset;
CARD32 YBuf1offset;
CARD32 UBuf1offset;
CARD32 VBuf1offset;
unsigned char currentBuf;
int brightness;
int contrast;
int saturation;
int pipe;
int doubleBuffer;
RegionRec clip;
CARD32 colorKey;
CARD32 gamma0;
CARD32 gamma1;
CARD32 gamma2;
CARD32 gamma3;
CARD32 gamma4;
CARD32 gamma5;
CARD32 videoStatus;
Time offTime;
Time freeTime;
FBLinearPtr linear;
Bool overlayOK;
int oneLineMode;
int scaleRatio;
Bool textured;
} I830PortPrivRec, *I830PortPrivPtr;
#define GET_PORT_PRIVATE(pScrn) \
(I830PortPrivPtr)((I830PTR(pScrn))->adaptor->pPortPrivates[0].ptr)
void I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv,
int id, RegionPtr dstRegion, short width,
short height, int video_pitch,
int x1, int y1, int x2, int y2,
short src_w, short src_h,
short drw_w, short drw_h,
DrawablePtr pDraw);

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/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i915_reg.h"
void I915EmitInvarientState( ScrnInfoPtr pScrn )
{
I830Ptr pI830 = I830PTR(pScrn);
BEGIN_LP_RING(20);
OUT_RING(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE |
AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE |
AA_LINE_REGION_WIDTH_1_0);
OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_RING(0);
OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
OUT_RING(0);
OUT_RING(_3DSTATE_DFLT_Z_CMD);
OUT_RING(0);
/* Don't support texture crossbar yet */
OUT_RING(_3DSTATE_COORD_SET_BINDINGS |
CSB_TCB(0, 0) |
CSB_TCB(1, 1) |
CSB_TCB(2, 2) |
CSB_TCB(3, 3) |
CSB_TCB(4, 4) |
CSB_TCB(5, 5) |
CSB_TCB(6, 6) |
CSB_TCB(7, 7));
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_POINT_RASTER_RULE |
OGL_POINT_RASTER_RULE |
ENABLE_LINE_STRIP_PROVOKE_VRTX |
ENABLE_TRI_FAN_PROVOKE_VRTX |
LINE_STRIP_PROVOKE_VRTX(1) |
TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_TEXKILL_3D_4D |
TEXKILL_4D);
/* Need to initialize this to zero.
*/
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
I1_LOAD_S(3) |
(1));
OUT_RING(0);
/* XXX: Use this */
OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD |
DISABLE_SCISSOR_RECT);
OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_RING(0);
OUT_RING(0);
OUT_RING(_3DSTATE_DEPTH_SUBRECT_DISABLE);
OUT_RING(_3DSTATE_LOAD_INDIRECT | 0); /* disable indirect state */
OUT_RING(0);
/* Don't support twosided stencil yet */
OUT_RING(_3DSTATE_BACKFACE_STENCIL_OPS |
BFO_ENABLE_STENCIL_TWO_SIDE |
0 );
OUT_RING(0);
ADVANCE_LP_RING();
}

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/* -*- c-basic-offset: 4 -*- */
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
/* MASK_* are the unshifted bitmasks of the destination mask in arithmetic
* operations
*/
#define MASK_X 0x1
#define MASK_Y 0x2
#define MASK_Z 0x4
#define MASK_W 0x8
#define MASK_XYZ (MASK_X | MASK_Y | MASK_W)
#define MASK_XYZW (MASK_XYZ | MASK_W)
#define MASK_SATURATE 0x10
/* Temporary, undeclared regs. Preserved between phases */
#define FS_R0 ((REG_TYPE_R << 8) | 0)
#define FS_R1 ((REG_TYPE_R << 8) | 1)
#define FS_R2 ((REG_TYPE_R << 8) | 2)
#define FS_R3 ((REG_TYPE_R << 8) | 3)
/* Texture coordinate regs. Must be declared. */
#define FS_T0 ((REG_TYPE_T << 8) | 0)
#define FS_T1 ((REG_TYPE_T << 8) | 1)
#define FS_T2 ((REG_TYPE_T << 8) | 2)
#define FS_T3 ((REG_TYPE_T << 8) | 3)
#define FS_T4 ((REG_TYPE_T << 8) | 4)
#define FS_T5 ((REG_TYPE_T << 8) | 5)
#define FS_T6 ((REG_TYPE_T << 8) | 6)
#define FS_T7 ((REG_TYPE_T << 8) | 7)
#define FS_T8 ((REG_TYPE_T << 8) | 8)
#define FS_T9 ((REG_TYPE_T << 8) | 9)
#define FS_T10 ((REG_TYPE_T << 8) | 10)
/* Constant values */
#define FS_C0 ((REG_TYPE_CONST << 8) | 0)
#define FS_C1 ((REG_TYPE_CONST << 8) | 1)
#define FS_C2 ((REG_TYPE_CONST << 8) | 2)
#define FS_C3 ((REG_TYPE_CONST << 8) | 3)
/* Sampler regs */
#define FS_S0 ((REG_TYPE_S << 8) | 0)
#define FS_S1 ((REG_TYPE_S << 8) | 1)
#define FS_S2 ((REG_TYPE_S << 8) | 2)
#define FS_S3 ((REG_TYPE_S << 8) | 3)
/* Output color */
#define FS_OC ((REG_TYPE_OC << 8) | 0)
/* Output depth */
#define FS_OD ((REG_TYPE_OD << 8) | 0)
/* Unpreserved temporary regs */
#define FS_U0 ((REG_TYPE_U << 8) | 0)
#define FS_U1 ((REG_TYPE_U << 8) | 1)
#define FS_U2 ((REG_TYPE_U << 8) | 2)
#define FS_U3 ((REG_TYPE_U << 8) | 3)
#define REG_TYPE(reg) ((reg) >> 8)
#define REG_NR(reg) ((reg) & 0xff)
struct i915_fs_op {
CARD32 ui[3];
};
#define X_CHANNEL_VAL 1
#define Y_CHANNEL_VAL 2
#define Z_CHANNEL_VAL 3
#define W_CHANNEL_VAL 4
#define ZERO_CHANNEL_VAL 5
#define ONE_CHANNEL_VAL 6
/**
* This structure represents the contents of an operand to an i915 fragment
* shader.
*
* It is not a hardware representation, though closely related.
*/
struct i915_fs_operand {
/**< REG_TYPE_* register type */
int reg;
/**< *_CHANNEL_VAL swizzle value, with optional negation */
int x;
/**< *_CHANNEL_VAL swizzle value, with optional negation */
int y;
/**< *_CHANNEL_VAL swizzle value, with optional negation */
int z;
/**< *_CHANNEL_VAL swizzle value, with optional negation */
int w;
};
/**
* Construct an operand description for the fragment shader.
*
* \param regtype FS_* register used as the source value for X/Y/Z/W sources.
* \param x *_CHANNEL_VAL swizzle value prefix for operand X channel, with
* optional negation.
* \param y *_CHANNEL_VAL swizzle value prefix for operand Y channel, with
* optional negation.
* \param z *_CHANNEL_VAL swizzle value prefix for operand Z channel, with
* optional negation.
* \param w *_CHANNEL_VAL swizzle value prefix for operand W channel, with
* optional negation.
*/
#define i915_fs_operand(reg, x, y, z, w) \
_i915_fs_operand(reg, \
x##_CHANNEL_VAL, y##_CHANNEL_VAL, \
z##_CHANNEL_VAL, w##_CHANNEL_VAL)
/**
* Construct an oeprand description for using a register with no swizzling
*/
#define i915_fs_operand_reg(reg) \
i915_fs_operand(reg, X, Y, Z, W)
static inline struct i915_fs_operand
_i915_fs_operand(int reg, int x, int y, int z, int w)
{
struct i915_fs_operand operand;
operand.reg = reg;
operand.x = x;
operand.y = y;
operand.z = z;
operand.w = w;
return operand;
}
/**
* Returns an operand containing (0.0, 0.0, 0.0, 0.0).
*/
static inline struct i915_fs_operand
i915_fs_operand_zero(void)
{
return i915_fs_operand(FS_R0, ZERO, ZERO, ZERO, ZERO);
}
/**
* Returns an unused operand
*/
#define i915_fs_operand_none() i915_fs_operand_zero()
/**
* Returns an operand containing (1.0, 1.0, 1.0, 1.0).
*/
static inline struct i915_fs_operand
i915_fs_operand_one(void)
{
return i915_fs_operand(FS_R0, ONE, ONE, ONE, ONE);
}
static inline int
i915_get_hardware_channel_val(int channel_val)
{
if (channel_val < 0)
channel_val = -channel_val;
switch (channel_val) {
case X_CHANNEL_VAL:
return SRC_X;
case Y_CHANNEL_VAL:
return SRC_Y;
case Z_CHANNEL_VAL:
return SRC_Z;
case W_CHANNEL_VAL:
return SRC_W;
case ZERO_CHANNEL_VAL:
return SRC_ZERO;
case ONE_CHANNEL_VAL:
return SRC_ONE;
}
FatalError("Bad channel value %d\n", channel_val);
}
/**
* Outputs a fragment shader command to declare a sampler or texture register.
*/
#define i915_fs_dcl(reg) \
do { \
FS_OUT(_i915_fs_dcl(reg)); \
} while (0)
/**
* Constructs a fragment shader command to declare a sampler or texture
* register.
*/
static inline struct i915_fs_op
_i915_fs_dcl(int reg)
{
struct i915_fs_op op;
op.ui[0] = D0_DCL | (REG_TYPE(reg) << D0_TYPE_SHIFT) |
(REG_NR(reg) << D0_NR_SHIFT);
op.ui[1] = 0;
op.ui[2] = 0;
if (REG_TYPE(reg) != REG_TYPE_S)
op.ui[0] |= D0_CHANNEL_ALL;
return op;
}
/**
* Constructs a fragment shader command to load from a texture sampler.
*/
#define i915_fs_texld(dest_reg, sampler_reg, address_reg) \
do { \
FS_OUT(_i915_fs_texld(T0_TEXLD, dest_reg, sampler_reg, address_reg)); \
} while (0)
static inline struct i915_fs_op
_i915_fs_texld(int load_op, int dest_reg, int sampler_reg, int address_reg)
{
struct i915_fs_op op;
op.ui[0] = 0;
op.ui[1] = 0;
op.ui[2] = 0;
if (REG_TYPE(sampler_reg) != REG_TYPE_S)
FatalError("Bad sampler reg type\n");
op.ui[0] |= load_op;
op.ui[0] |= REG_TYPE(dest_reg) << T0_DEST_TYPE_SHIFT;
op.ui[0] |= REG_NR(dest_reg) << T0_DEST_NR_SHIFT;
op.ui[0] |= REG_NR(sampler_reg) << T0_SAMPLER_NR_SHIFT;
op.ui[1] |= REG_TYPE(address_reg) << T1_ADDRESS_REG_TYPE_SHIFT;
op.ui[1] |= REG_NR(address_reg) << T1_ADDRESS_REG_NR_SHIFT;
return op;
}
#define i915_fs_arith(op, dest_reg, operand0, operand1, operand2) \
_i915_fs_arith(A0_##op, dest_reg, operand0, operand1, operand2)
static inline struct i915_fs_op
_i915_fs_arith(int cmd, int dest_reg,
struct i915_fs_operand operand0,
struct i915_fs_operand operand1,
struct i915_fs_operand operand2)
{
struct i915_fs_op op;
op.ui[0] = 0;
op.ui[1] = 0;
op.ui[2] = 0;
/* Set up destination register and write mask */
op.ui[0] |= cmd;
op.ui[0] |= REG_TYPE(dest_reg) << A0_DEST_TYPE_SHIFT;
op.ui[0] |= REG_NR(dest_reg) << A0_DEST_NR_SHIFT;
op.ui[0] |= A0_DEST_CHANNEL_ALL;
/* Set up operand 0 */
op.ui[0] |= REG_TYPE(operand0.reg) << A0_SRC0_TYPE_SHIFT;
op.ui[0] |= REG_NR(operand0.reg) << A0_SRC0_NR_SHIFT;
op.ui[1] |= i915_get_hardware_channel_val(operand0.x) <<
A1_SRC0_CHANNEL_X_SHIFT;
if (operand0.x < 0)
op.ui[1] |= A1_SRC0_CHANNEL_X_NEGATE;
op.ui[1] |= i915_get_hardware_channel_val(operand0.y) <<
A1_SRC0_CHANNEL_Y_SHIFT;
if (operand0.y < 0)
op.ui[1] |= A1_SRC0_CHANNEL_Y_NEGATE;
op.ui[1] |= i915_get_hardware_channel_val(operand0.z) <<
A1_SRC0_CHANNEL_Z_SHIFT;
if (operand0.z < 0)
op.ui[1] |= A1_SRC0_CHANNEL_Z_NEGATE;
op.ui[1] |= i915_get_hardware_channel_val(operand0.w) <<
A1_SRC0_CHANNEL_W_SHIFT;
if (operand0.w < 0)
op.ui[1] |= A1_SRC0_CHANNEL_W_NEGATE;
/* Set up operand 1 */
op.ui[1] |= REG_TYPE(operand1.reg) << A1_SRC1_TYPE_SHIFT;
op.ui[1] |= REG_NR(operand1.reg) << A1_SRC1_NR_SHIFT;
op.ui[1] |= i915_get_hardware_channel_val(operand1.x) <<
A1_SRC1_CHANNEL_X_SHIFT;
if (operand1.x < 0)
op.ui[1] |= A1_SRC1_CHANNEL_X_NEGATE;
op.ui[1] |= i915_get_hardware_channel_val(operand1.y) <<
A1_SRC1_CHANNEL_Y_SHIFT;
if (operand1.y < 0)
op.ui[1] |= A1_SRC1_CHANNEL_Y_NEGATE;
op.ui[2] |= i915_get_hardware_channel_val(operand1.z) <<
A2_SRC1_CHANNEL_Z_SHIFT;
if (operand1.z < 0)
op.ui[2] |= A2_SRC1_CHANNEL_Z_NEGATE;
op.ui[2] |= i915_get_hardware_channel_val(operand1.w) <<
A2_SRC1_CHANNEL_W_SHIFT;
if (operand1.w < 0)
op.ui[2] |= A2_SRC1_CHANNEL_W_NEGATE;
/* Set up operand 2 */
op.ui[2] |= REG_TYPE(operand2.reg) << A2_SRC2_TYPE_SHIFT;
op.ui[2] |= REG_NR(operand2.reg) << A2_SRC2_NR_SHIFT;
op.ui[2] |= i915_get_hardware_channel_val(operand2.x) <<
A2_SRC2_CHANNEL_X_SHIFT;
if (operand2.x < 0)
op.ui[2] |= A2_SRC2_CHANNEL_X_NEGATE;
op.ui[2] |= i915_get_hardware_channel_val(operand2.y) <<
A2_SRC2_CHANNEL_Y_SHIFT;
if (operand2.y < 0)
op.ui[2] |= A2_SRC2_CHANNEL_Y_NEGATE;
op.ui[2] |= i915_get_hardware_channel_val(operand2.z) <<
A2_SRC2_CHANNEL_Z_SHIFT;
if (operand2.z < 0)
op.ui[2] |= A2_SRC2_CHANNEL_Z_NEGATE;
op.ui[2] |= i915_get_hardware_channel_val(operand2.w) <<
A2_SRC2_CHANNEL_W_SHIFT;
if (operand2.w < 0)
op.ui[2] |= A2_SRC2_CHANNEL_W_NEGATE;
return op;
}
/**
* Move the values in operand0 to the dest reg with the masking/saturation
* specified.
*/
#define i915_fs_mov_masked(dest_reg, dest_mask, operand0) \
do { \
struct i915_fs_op op; \
\
op = i915_fs_arith(MOV, dest_reg, operand0, i915_fs_operand_none(), \
i915_fs_operand_none()); \
op.ui[0] &= ~A0_DEST_CHANNEL_ALL; \
op.ui[0] |= ((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT; \
if ((dest_mask) & MASK_SATURATE) \
op.ui[0] |= A0_DEST_SATURATE; \
\
FS_OUT(op); \
} while (0)
/** Add operand0 and operand1 and put the result in dest_reg */
#define i915_fs_add(dest_reg, operand0, operand1) \
do { \
FS_OUT(i915_fs_arith(ADD, dest_reg, operand0, operand1, \
i915_fs_operand_none())); \
} while (0)
/**
* Perform a 3-component dot-product of operand0 and operand1 and put the
* resulting scalar in the channels of dest_reg specified by the dest_mask.
*/
#define i915_fs_dp3_masked(dest_reg, dest_mask, operand0, operand1) \
do { \
struct i915_fs_op op; \
\
op = i915_fs_arith(DP3, dest_reg, operand0, i915_fs_operand_none(), \
i915_fs_operand_none()); \
op.ui[0] &= ~A0_DEST_CHANNEL_ALL; \
op.ui[0] |= ((dest_mask) & ~MASK_SATURATE) << A0_DEST_CHANNEL_SHIFT; \
if ((dest_mask) & MASK_SATURATE) \
op.ui[0] |= A0_DEST_SATURATE; \
\
FS_OUT(op); \
} while (0)
/**
* Sets up local state for accumulating a fragment shader buffer.
*
* \param x maximum number of shader commands that may be used between
* a FS_START and FS_END
*/
#define FS_LOCALS(x) \
CARD32 _shader_buf[(x) * 3]; \
int _max_shader_commands = x; \
int _cur_shader_commands
#define FS_BEGIN() \
do { \
_cur_shader_commands = 0; \
} while (0)
#define FS_OUT(_shaderop) \
do { \
_shader_buf[_cur_shader_commands * 3 + 0] = _shaderop.ui[0]; \
_shader_buf[_cur_shader_commands * 3 + 1] = _shaderop.ui[1]; \
_shader_buf[_cur_shader_commands * 3 + 2] = _shaderop.ui[2]; \
if (++_cur_shader_commands > _max_shader_commands) \
FatalError("fragment shader command buffer exceeded (%d)\n", \
_cur_shader_commands); \
} while (0)
#define FS_END() \
do { \
int _i; \
BEGIN_LP_RING(_cur_shader_commands * 3 + 1); \
OUT_RING(_3DSTATE_PIXEL_SHADER_PROGRAM | \
(_cur_shader_commands * 3 - 1)); \
for (_i = 0; _i < _cur_shader_commands * 3; _i++) \
OUT_RING(_shader_buf[_i]); \
ADVANCE_LP_RING(); \
} while (0);

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/**************************************************************************
*
* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
* All Rights Reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the
* "Software"), to deal in the Software without restriction, including
* without limitation the rights to use, copy, modify, merge, publish,
* distribute, sub license, and/or sell copies of the Software, and to
* permit persons to whom the Software is furnished to do so, subject to
* the following conditions:
*
* The above copyright notice and this permission notice (including the
* next paragraph) shall be included in all copies or substantial portions
* of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
**************************************************************************/
#ifndef _I915_REG_H_
#define _I915_REG_H_
#define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value)
#define CMD_3D (0x3<<29)
#define PRIM3D_INLINE (CMD_3D | (0x1f<<24))
#define PRIM3D_TRILIST (0x0<<18)
#define PRIM3D_TRISTRIP (0x1<<18)
#define PRIM3D_TRISTRIP_RVRSE (0x2<<18)
#define PRIM3D_TRIFAN (0x3<<18)
#define PRIM3D_POLY (0x4<<18)
#define PRIM3D_LINELIST (0x5<<18)
#define PRIM3D_LINESTRIP (0x6<<18)
#define PRIM3D_RECTLIST (0x7<<18)
#define PRIM3D_POINTLIST (0x8<<18)
#define PRIM3D_DIB (0x9<<18)
#define PRIM3D_CLEAR_RECT (0xa<<18)
#define PRIM3D_ZONE_INIT (0xd<<18)
#define PRIM3D_MASK (0x1f<<18)
/* p137 */
#define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24))
#define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16)
#define AA_LINE_ECAAR_WIDTH_0_5 0
#define AA_LINE_ECAAR_WIDTH_1_0 (1<<14)
#define AA_LINE_ECAAR_WIDTH_2_0 (2<<14)
#define AA_LINE_ECAAR_WIDTH_4_0 (3<<14)
#define AA_LINE_REGION_WIDTH_ENABLE (1<<8)
#define AA_LINE_REGION_WIDTH_0_5 0
#define AA_LINE_REGION_WIDTH_1_0 (1<<6)
#define AA_LINE_REGION_WIDTH_2_0 (2<<6)
#define AA_LINE_REGION_WIDTH_4_0 (3<<6)
/* 3DSTATE_BACKFACE_STENCIL_OPS, p138*/
#define _3DSTATE_BACKFACE_STENCIL_OPS (CMD_3D | (0x8<<24))
#define BFO_ENABLE_STENCIL_REF (1<<23)
#define BFO_STENCIL_REF_SHIFT 15
#define BFO_STENCIL_REF_MASK (0xff<<15)
#define BFO_ENABLE_STENCIL_FUNCS (1<<14)
#define BFO_STENCIL_TEST_SHIFT 11
#define BFO_STENCIL_TEST_MASK (0x7<<11)
#define BFO_STENCIL_FAIL_SHIFT 8
#define BFO_STENCIL_FAIL_MASK (0x7<<8)
#define BFO_STENCIL_PASS_Z_FAIL_SHIFT 5
#define BFO_STENCIL_PASS_Z_FAIL_MASK (0x7<<5)
#define BFO_STENCIL_PASS_Z_PASS_SHIFT 2
#define BFO_STENCIL_PASS_Z_PASS_MASK (0x7<<2)
#define BFO_ENABLE_STENCIL_TWO_SIDE (1<<1)
#define BFO_STENCIL_TWO_SIDE (1<<0)
/* 3DSTATE_BACKFACE_STENCIL_MASKS, p140 */
#define _3DSTATE_BACKFACE_STENCIL_MASKS (CMD_3D | (0x9<<24))
#define BFM_ENABLE_STENCIL_TEST_MASK (1<<17)
#define BFM_ENABLE_STENCIL_WRITE_MASK (1<<16)
#define BFM_STENCIL_TEST_MASK_SHIFT 8
#define BFM_STENCIL_TEST_MASK_MASK (0xff<<8)
#define BFM_STENCIL_WRITE_MASK_SHIFT 0
#define BFM_STENCIL_WRITE_MASK_MASK (0xff<<0)
/* 3DSTATE_BIN_CONTROL p141 */
/* p143 */
#define _3DSTATE_BUF_INFO_CMD (CMD_3D | (0x1d<<24) | (0x8e<<16) | 1)
/* Dword 1 */
#define BUF_3D_ID_COLOR_BACK (0x3<<24)
#define BUF_3D_ID_DEPTH (0x7<<24)
#define BUF_3D_USE_FENCE (1<<23)
#define BUF_3D_TILED_SURFACE (1<<22)
#define BUF_3D_TILE_WALK_X 0
#define BUF_3D_TILE_WALK_Y (1<<21)
#define BUF_3D_PITCH(x) (((x)/4)<<2)
/* Dword 2 */
#define BUF_3D_ADDR(x) ((x) & ~0x3)
/* 3DSTATE_CHROMA_KEY */
/* 3DSTATE_CLEAR_PARAMETERS, p150 */
/* 3DSTATE_CONSTANT_BLEND_COLOR, p153 */
#define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16))
/* 3DSTATE_COORD_SET_BINDINGS, p154 */
#define _3DSTATE_COORD_SET_BINDINGS (CMD_3D | (0x16<<24))
#define CSB_TCB(iunit, eunit) ((eunit)<<(iunit*3))
/* p156 */
#define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16))
/* p157 */
#define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16))
/* p158 */
#define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16))
/* 3DSTATE_DEPTH_OFFSET_SCALE, p159 */
#define _3DSTATE_DEPTH_OFFSET_SCALE (CMD_3D | (0x1d<<24) | (0x97<<16))
/* scale in dword 1 */
/* 3DSTATE_DEPTH_SUBRECT_DISABLE, p160 */
#define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<19) | 0x2)
/* p161 */
#define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16))
/* Dword 1 */
#define TEX_DEFAULT_COLOR_OGL (0<<30)
#define TEX_DEFAULT_COLOR_D3D (1<<30)
#define ZR_EARLY_DEPTH (1<<29)
#define LOD_PRECLAMP_OGL (1<<28)
#define LOD_PRECLAMP_D3D (0<<28)
#define DITHER_FULL_ALWAYS (0<<26)
#define DITHER_FULL_ON_FB_BLEND (1<<26)
#define DITHER_CLAMPED_ALWAYS (2<<26)
#define LINEAR_GAMMA_BLEND_32BPP (1<<25)
#define DEBUG_DISABLE_ENH_DITHER (1<<24)
#define DSTORG_HORT_BIAS(x) ((x)<<20)
#define DSTORG_VERT_BIAS(x) ((x)<<16)
#define COLOR_4_2_2_CHNL_WRT_ALL 0
#define COLOR_4_2_2_CHNL_WRT_Y (1<<12)
#define COLOR_4_2_2_CHNL_WRT_CR (2<<12)
#define COLOR_4_2_2_CHNL_WRT_CB (3<<12)
#define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12)
#define COLR_BUF_8BIT 0
#define COLR_BUF_RGB555 (1<<8)
#define COLR_BUF_RGB565 (2<<8)
#define COLR_BUF_ARGB8888 (3<<8)
#define DEPTH_FRMT_16_FIXED 0
#define DEPTH_FRMT_16_FLOAT (1<<2)
#define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2)
#define VERT_LINE_STRIDE_1 (1<<1)
#define VERT_LINE_STRIDE_0 (0<<1)
#define VERT_LINE_STRIDE_OFS_1 1
#define VERT_LINE_STRIDE_OFS_0 0
/* p166 */
#define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3)
/* Dword 1 */
#define DRAW_RECT_DIS_DEPTH_OFS (1<<30)
#define DRAW_DITHER_OFS_X(x) ((x)<<26)
#define DRAW_DITHER_OFS_Y(x) ((x)<<24)
/* Dword 2 */
#define DRAW_YMIN(x) ((x)<<16)
#define DRAW_XMIN(x) (x)
/* Dword 3 */
#define DRAW_YMAX(x) ((x)<<16)
#define DRAW_XMAX(x) (x)
/* Dword 4 */
#define DRAW_YORG(x) ((x)<<16)
#define DRAW_XORG(x) (x)
/* 3DSTATE_FILTER_COEFFICIENTS_4X4, p170 */
/* 3DSTATE_FILTER_COEFFICIENTS_6X5, p172 */
/* _3DSTATE_FOG_COLOR, p173 */
#define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24))
#define FOG_COLOR_RED(x) ((x)<<16)
#define FOG_COLOR_GREEN(x) ((x)<<8)
#define FOG_COLOR_BLUE(x) (x)
/* _3DSTATE_FOG_MODE, p174 */
#define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2)
/* Dword 1 */
#define FMC1_FOGFUNC_MODIFY_ENABLE (1<<31)
#define FMC1_FOGFUNC_VERTEX (0<<28)
#define FMC1_FOGFUNC_PIXEL_EXP (1<<28)
#define FMC1_FOGFUNC_PIXEL_EXP2 (2<<28)
#define FMC1_FOGFUNC_PIXEL_LINEAR (3<<28)
#define FMC1_FOGFUNC_MASK (3<<28)
#define FMC1_FOGINDEX_MODIFY_ENABLE (1<<27)
#define FMC1_FOGINDEX_Z (0<<25)
#define FMC1_FOGINDEX_W (1<<25)
#define FMC1_C1_C2_MODIFY_ENABLE (1<<24)
#define FMC1_DENSITY_MODIFY_ENABLE (1<<23)
#define FMC1_C1_ONE (1<<13)
#define FMC1_C1_MASK (0xffff<<4)
/* Dword 2 */
#define FMC2_C2_ONE (1<<16)
/* Dword 3 */
#define FMC3_D_ONE (1<<16)
/* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p177 */
#define _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24))
#define IAB_MODIFY_ENABLE (1<<23)
#define IAB_ENABLE (1<<22)
#define IAB_MODIFY_FUNC (1<<21)
#define IAB_FUNC_SHIFT 16
#define IAB_MODIFY_SRC_FACTOR (1<<11)
#define IAB_SRC_FACTOR_SHIFT 6
#define IAB_SRC_FACTOR_MASK (BLENDFACT_MASK<<6)
#define IAB_MODIFY_DST_FACTOR (1<<5)
#define IAB_DST_FACTOR_SHIFT 0
#define IAB_DST_FACTOR_MASK (BLENDFACT_MASK<<0)
#define BLENDFACT_ZERO 0x01
#define BLENDFACT_ONE 0x02
#define BLENDFACT_SRC_COLR 0x03
#define BLENDFACT_INV_SRC_COLR 0x04
#define BLENDFACT_SRC_ALPHA 0x05
#define BLENDFACT_INV_SRC_ALPHA 0x06
#define BLENDFACT_DST_ALPHA 0x07
#define BLENDFACT_INV_DST_ALPHA 0x08
#define BLENDFACT_DST_COLR 0x09
#define BLENDFACT_INV_DST_COLR 0x0a
#define BLENDFACT_SRC_ALPHA_SATURATE 0x0b
#define BLENDFACT_CONST_COLOR 0x0c
#define BLENDFACT_INV_CONST_COLOR 0x0d
#define BLENDFACT_CONST_ALPHA 0x0e
#define BLENDFACT_INV_CONST_ALPHA 0x0f
#define BLENDFACT_MASK 0x0f
#define BLENDFUNC_ADD 0x0
#define BLENDFUNC_SUBTRACT 0x1
#define BLENDFUNC_REVERSE_SUBTRACT 0x2
#define BLENDFUNC_MIN 0x3
#define BLENDFUNC_MAX 0x4
#define BLENDFUNC_MASK 0x7
/* 3DSTATE_LOAD_INDIRECT, p180 */
#define _3DSTATE_LOAD_INDIRECT (CMD_3D|(0x1d<<24)|(0x7<<16))
#define LI0_STATE_STATIC_INDIRECT (0x01<<8)
#define LI0_STATE_DYNAMIC_INDIRECT (0x02<<8)
#define LI0_STATE_SAMPLER (0x04<<8)
#define LI0_STATE_MAP (0x08<<8)
#define LI0_STATE_PROGRAM (0x10<<8)
#define LI0_STATE_CONSTANTS (0x20<<8)
#define SIS0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define SIS0_FORCE_LOAD (1<<1)
#define SIS0_BUFFER_VALID (1<<0)
#define SIS1_BUFFER_LENGTH(x) ((x)&0xff)
#define DIS0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define DIS0_BUFFER_RESET (1<<1)
#define DIS0_BUFFER_VALID (1<<0)
#define SSB0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define SSB0_FORCE_LOAD (1<<1)
#define SSB0_BUFFER_VALID (1<<0)
#define SSB1_BUFFER_LENGTH(x) ((x)&0xff)
#define MSB0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define MSB0_FORCE_LOAD (1<<1)
#define MSB0_BUFFER_VALID (1<<0)
#define MSB1_BUFFER_LENGTH(x) ((x)&0xff)
#define PSP0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define PSP0_FORCE_LOAD (1<<1)
#define PSP0_BUFFER_VALID (1<<0)
#define PSP1_BUFFER_LENGTH(x) ((x)&0xff)
#define PSC0_BUFFER_ADDRESS(x) ((x)&~0x3)
#define PSC0_FORCE_LOAD (1<<1)
#define PSC0_BUFFER_VALID (1<<0)
#define PSC1_BUFFER_LENGTH(x) ((x)&0xff)
/* _3DSTATE_RASTERIZATION_RULES */
#define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24))
#define ENABLE_POINT_RASTER_RULE (1<<15)
#define OGL_POINT_RASTER_RULE (1<<13)
#define ENABLE_TEXKILL_3D_4D (1<<10)
#define TEXKILL_3D (0<<9)
#define TEXKILL_4D (1<<9)
#define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8)
#define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5)
#define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6)
#define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3)
/* _3DSTATE_SCISSOR_ENABLE, p256 */
#define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19))
#define ENABLE_SCISSOR_RECT ((1<<1) | 1)
#define DISABLE_SCISSOR_RECT (1<<1)
/* _3DSTATE_SCISSOR_RECTANGLE_0, p257 */
#define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1)
/* Dword 1 */
#define SCISSOR_RECT_0_YMIN(x) ((x)<<16)
#define SCISSOR_RECT_0_XMIN(x) (x)
/* Dword 2 */
#define SCISSOR_RECT_0_YMAX(x) ((x)<<16)
#define SCISSOR_RECT_0_XMAX(x) (x)
/* p189 */
#define _3DSTATE_LOAD_STATE_IMMEDIATE_1 ((0x3<<29)|(0x1d<<24)|(0x04<<16))
#define I1_LOAD_S(n) (1<<(4+n))
#define S0_VB_OFFSET_MASK 0xffffffc
#define S0_AUTO_CACHE_INV_DISABLE (1<<0)
#define S1_VERTEX_WIDTH_SHIFT 24
#define S1_VERTEX_WIDTH_MASK (0x3f<<24)
#define S1_VERTEX_PITCH_SHIFT 16
#define S1_VERTEX_PITCH_MASK (0x3f<<16)
#define TEXCOORDFMT_2D 0x0
#define TEXCOORDFMT_3D 0x1
#define TEXCOORDFMT_4D 0x2
#define TEXCOORDFMT_1D 0x3
#define TEXCOORDFMT_2D_16 0x4
#define TEXCOORDFMT_4D_16 0x5
#define TEXCOORDFMT_NOT_PRESENT 0xf
#define S2_TEXCOORD_FMT0_MASK 0xf
#define S2_TEXCOORD_FMT1_SHIFT 4
#define S2_TEXCOORD_FMT(unit, type) ((type)<<(unit*4))
#define S2_TEXCOORD_NONE (~0)
/* S3 not interesting */
#define S4_POINT_WIDTH_SHIFT 23
#define S4_POINT_WIDTH_MASK (0x1ff<<23)
#define S4_LINE_WIDTH_SHIFT 19
#define S4_LINE_WIDTH_ONE (0x2<<19)
#define S4_LINE_WIDTH_MASK (0xf<<19)
#define S4_FLATSHADE_ALPHA (1<<18)
#define S4_FLATSHADE_FOG (1<<17)
#define S4_FLATSHADE_SPECULAR (1<<16)
#define S4_FLATSHADE_COLOR (1<<15)
#define S4_CULLMODE_BOTH (0<<13)
#define S4_CULLMODE_NONE (1<<13)
#define S4_CULLMODE_CW (2<<13)
#define S4_CULLMODE_CCW (3<<13)
#define S4_CULLMODE_MASK (3<<13)
#define S4_VFMT_POINT_WIDTH (1<<12)
#define S4_VFMT_SPEC_FOG (1<<11)
#define S4_VFMT_COLOR (1<<10)
#define S4_VFMT_DEPTH_OFFSET (1<<9)
#define S4_VFMT_XYZ (1<<6)
#define S4_VFMT_XYZW (2<<6)
#define S4_VFMT_XY (3<<6)
#define S4_VFMT_XYW (4<<6)
#define S4_VFMT_XYZW_MASK (7<<6)
#define S4_FORCE_DEFAULT_DIFFUSE (1<<5)
#define S4_FORCE_DEFAULT_SPECULAR (1<<4)
#define S4_LOCAL_DEPTH_OFFSET_ENABLE (1<<3)
#define S4_VFMT_FOG_PARAM (1<<2)
#define S4_SPRITE_POINT_ENABLE (1<<1)
#define S4_LINE_ANTIALIAS_ENABLE (1<<0)
#define S4_VFMT_MASK (S4_VFMT_POINT_WIDTH | \
S4_VFMT_SPEC_FOG | \
S4_VFMT_COLOR | \
S4_VFMT_DEPTH_OFFSET | \
S4_VFMT_XYZW_MASK | \
S4_VFMT_FOG_PARAM)
#define S5_WRITEDISABLE_ALPHA (1<<31)
#define S5_WRITEDISABLE_RED (1<<30)
#define S5_WRITEDISABLE_GREEN (1<<29)
#define S5_WRITEDISABLE_BLUE (1<<28)
#define S5_WRITEDISABLE_MASK (0xf<<28)
#define S5_FORCE_DEFAULT_POINT_SIZE (1<<27)
#define S5_LAST_PIXEL_ENABLE (1<<26)
#define S5_GLOBAL_DEPTH_OFFSET_ENABLE (1<<25)
#define S5_FOG_ENABLE (1<<24)
#define S5_STENCIL_REF_SHIFT 16
#define S5_STENCIL_REF_MASK (0xff<<16)
#define S5_STENCIL_TEST_FUNC_SHIFT 13
#define S5_STENCIL_TEST_FUNC_MASK (0x7<<13)
#define S5_STENCIL_FAIL_SHIFT 10
#define S5_STENCIL_FAIL_MASK (0x7<<10)
#define S5_STENCIL_PASS_Z_FAIL_SHIFT 7
#define S5_STENCIL_PASS_Z_FAIL_MASK (0x7<<7)
#define S5_STENCIL_PASS_Z_PASS_SHIFT 4
#define S5_STENCIL_PASS_Z_PASS_MASK (0x7<<4)
#define S5_STENCIL_WRITE_ENABLE (1<<3)
#define S5_STENCIL_TEST_ENABLE (1<<2)
#define S5_COLOR_DITHER_ENABLE (1<<1)
#define S5_LOGICOP_ENABLE (1<<0)
#define S6_ALPHA_TEST_ENABLE (1<<31)
#define S6_ALPHA_TEST_FUNC_SHIFT 28
#define S6_ALPHA_TEST_FUNC_MASK (0x7<<28)
#define S6_ALPHA_REF_SHIFT 20
#define S6_ALPHA_REF_MASK (0xff<<20)
#define S6_DEPTH_TEST_ENABLE (1<<19)
#define S6_DEPTH_TEST_FUNC_SHIFT 16
#define S6_DEPTH_TEST_FUNC_MASK (0x7<<16)
#define S6_CBUF_BLEND_ENABLE (1<<15)
#define S6_CBUF_BLEND_FUNC_SHIFT 12
#define S6_CBUF_BLEND_FUNC_MASK (0x7<<12)
#define S6_CBUF_SRC_BLEND_FACT_SHIFT 8
#define S6_CBUF_SRC_BLEND_FACT_MASK (0xf<<8)
#define S6_CBUF_DST_BLEND_FACT_SHIFT 4
#define S6_CBUF_DST_BLEND_FACT_MASK (0xf<<4)
#define S6_DEPTH_WRITE_ENABLE (1<<3)
#define S6_COLOR_WRITE_ENABLE (1<<2)
#define S6_TRISTRIP_PV_SHIFT 0
#define S6_TRISTRIP_PV_MASK (0x3<<0)
#define S7_DEPTH_OFFSET_CONST_MASK ~0
/* 3DSTATE_MAP_DEINTERLACER_PARAMETERS */
/* 3DSTATE_MAP_PALETTE_LOAD_32, p206 */
/* _3DSTATE_MODES_4, p218 */
#define _3DSTATE_MODES_4_CMD (CMD_3D|(0x0d<<24))
#define ENABLE_LOGIC_OP_FUNC (1<<23)
#define LOGIC_OP_FUNC(x) ((x)<<18)
#define LOGICOP_MASK (0xf<<18)
#define LOGICOP_COPY 0xc
#define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00))
#define ENABLE_STENCIL_TEST_MASK (1<<17)
#define STENCIL_TEST_MASK(x) ((x)<<8)
#define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff))
#define ENABLE_STENCIL_WRITE_MASK (1<<16)
#define STENCIL_WRITE_MASK(x) ((x)&0xff)
/* _3DSTATE_MODES_5, p220 */
#define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24))
#define PIPELINE_FLUSH_RENDER_CACHE (1<<18)
#define PIPELINE_FLUSH_TEXTURE_CACHE (1<<16)
/* p221 */
#define _3DSTATE_PIXEL_SHADER_CONSTANTS (CMD_3D|(0x1d<<24)|(0x6<<16))
#define PS1_REG(n) (1<<(n))
#define PS2_CONST_X(n) (n)
#define PS3_CONST_Y(n) (n)
#define PS4_CONST_Z(n) (n)
#define PS5_CONST_W(n) (n)
/* p222 */
#define I915_MAX_TEX_INDIRECT 4
#define I915_MAX_TEX_INSN 32
#define I915_MAX_ALU_INSN 64
#define I915_MAX_DECL_INSN 27
#define I915_MAX_TEMPORARY 16
/* Each instruction is 3 dwords long, though most don't require all
* this space. Maximum of 123 instructions. Smaller maxes per insn
* type.
*/
#define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16))
#define REG_TYPE_R 0 /* temporary regs, no need to
* dcl, must be written before
* read -- Preserved between
* phases.
*/
#define REG_TYPE_T 1 /* Interpolated values, must be
* dcl'ed before use.
*
* 0..7: texture coord,
* 8: diffuse spec,
* 9: specular color,
* 10: fog parameter in w.
*/
#define REG_TYPE_CONST 2 /* Restriction: only one const
* can be referenced per
* instruction, though it may be
* selected for multiple inputs.
* Constants not initialized
* default to zero.
*/
#define REG_TYPE_S 3 /* sampler */
#define REG_TYPE_OC 4 /* output color (rgba) */
#define REG_TYPE_OD 5 /* output depth (w), xyz are
* temporaries. If not written,
* interpolated depth is used?
*/
#define REG_TYPE_U 6 /* unpreserved temporaries */
#define REG_TYPE_MASK 0x7
#define REG_NR_MASK 0xf
/* REG_TYPE_T:
*/
#define T_TEX0 0
#define T_TEX1 1
#define T_TEX2 2
#define T_TEX3 3
#define T_TEX4 4
#define T_TEX5 5
#define T_TEX6 6
#define T_TEX7 7
#define T_DIFFUSE 8
#define T_SPECULAR 9
#define T_FOG_W 10 /* interpolated fog is in W coord */
/* Arithmetic instructions */
/* .replicate_swizzle == selection and replication of a particular
* scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww
*/
#define A0_NOP (0x0<<24) /* no operation */
#define A0_ADD (0x1<<24) /* dst = src0 + src1 */
#define A0_MOV (0x2<<24) /* dst = src0 */
#define A0_MUL (0x3<<24) /* dst = src0 * src1 */
#define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */
#define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */
#define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */
#define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */
#define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */
#define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */
#define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */
#define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */
#define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */
#define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */
#define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */
#define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */
#define A0_FLR (0x10<<24) /* dst = floor(src0) */
#define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */
#define A0_TRC (0x12<<24) /* dst = int(src0) */
#define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */
#define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */
#define A0_DEST_SATURATE (1<<22)
#define A0_DEST_TYPE_SHIFT 19
/* Allow: R, OC, OD, U */
#define A0_DEST_NR_SHIFT 14
/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
#define A0_DEST_CHANNEL_X (1<<10)
#define A0_DEST_CHANNEL_Y (2<<10)
#define A0_DEST_CHANNEL_Z (4<<10)
#define A0_DEST_CHANNEL_W (8<<10)
#define A0_DEST_CHANNEL_ALL (0xf<<10)
#define A0_DEST_CHANNEL_SHIFT 10
#define A0_SRC0_TYPE_SHIFT 7
#define A0_SRC0_NR_SHIFT 2
#define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y)
#define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z)
#define SRC_X 0
#define SRC_Y 1
#define SRC_Z 2
#define SRC_W 3
#define SRC_ZERO 4
#define SRC_ONE 5
#define A1_SRC0_CHANNEL_X_NEGATE (1<<31)
#define A1_SRC0_CHANNEL_X_SHIFT 28
#define A1_SRC0_CHANNEL_Y_NEGATE (1<<27)
#define A1_SRC0_CHANNEL_Y_SHIFT 24
#define A1_SRC0_CHANNEL_Z_NEGATE (1<<23)
#define A1_SRC0_CHANNEL_Z_SHIFT 20
#define A1_SRC0_CHANNEL_W_NEGATE (1<<19)
#define A1_SRC0_CHANNEL_W_SHIFT 16
#define A1_SRC1_TYPE_SHIFT 13
#define A1_SRC1_NR_SHIFT 8
#define A1_SRC1_CHANNEL_X_NEGATE (1<<7)
#define A1_SRC1_CHANNEL_X_SHIFT 4
#define A1_SRC1_CHANNEL_Y_NEGATE (1<<3)
#define A1_SRC1_CHANNEL_Y_SHIFT 0
#define A2_SRC1_CHANNEL_Z_NEGATE (1<<31)
#define A2_SRC1_CHANNEL_Z_SHIFT 28
#define A2_SRC1_CHANNEL_W_NEGATE (1<<27)
#define A2_SRC1_CHANNEL_W_SHIFT 24
#define A2_SRC2_TYPE_SHIFT 21
#define A2_SRC2_NR_SHIFT 16
#define A2_SRC2_CHANNEL_X_NEGATE (1<<15)
#define A2_SRC2_CHANNEL_X_SHIFT 12
#define A2_SRC2_CHANNEL_Y_NEGATE (1<<11)
#define A2_SRC2_CHANNEL_Y_SHIFT 8
#define A2_SRC2_CHANNEL_Z_NEGATE (1<<7)
#define A2_SRC2_CHANNEL_Z_SHIFT 4
#define A2_SRC2_CHANNEL_W_NEGATE (1<<3)
#define A2_SRC2_CHANNEL_W_SHIFT 0
/* Texture instructions */
#define T0_TEXLD (0x15<<24) /* Sample texture using predeclared
* sampler and address, and output
* filtered texel data to destination
* register */
#define T0_TEXLDP (0x16<<24) /* Same as texld but performs a
* perspective divide of the texture
* coordinate .xyz values by .w before
* sampling. */
#define T0_TEXLDB (0x17<<24) /* Same as texld but biases the
* computed LOD by w. Only S4.6 two's
* comp is used. This implies that a
* float to fixed conversion is
* done. */
#define T0_TEXKILL (0x18<<24) /* Does not perform a sampling
* operation. Simply kills the pixel
* if any channel of the address
* register is < 0.0. */
#define T0_DEST_TYPE_SHIFT 19
/* Allow: R, OC, OD, U */
/* Note: U (unpreserved) regs do not retain their values between
* phases (cannot be used for feedback)
*
* Note: oC and OD registers can only be used as the destination of a
* texture instruction once per phase (this is an implementation
* restriction).
*/
#define T0_DEST_NR_SHIFT 14
/* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */
#define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */
#define T0_SAMPLER_NR_MASK (0xf<<0)
#define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */
/* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */
#define T1_ADDRESS_REG_NR_SHIFT 17
#define T2_MBZ 0
/* Declaration instructions */
#define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib)
* register or an s (sampler)
* register. */
#define D0_SAMPLE_TYPE_SHIFT 22
#define D0_SAMPLE_TYPE_2D (0x0<<22)
#define D0_SAMPLE_TYPE_CUBE (0x1<<22)
#define D0_SAMPLE_TYPE_VOLUME (0x2<<22)
#define D0_SAMPLE_TYPE_MASK (0x3<<22)
#define D0_TYPE_SHIFT 19
/* Allow: T, S */
#define D0_NR_SHIFT 14
/* Allow T: 0..10, S: 0..15 */
#define D0_CHANNEL_X (1<<10)
#define D0_CHANNEL_Y (2<<10)
#define D0_CHANNEL_Z (4<<10)
#define D0_CHANNEL_W (8<<10)
#define D0_CHANNEL_ALL (0xf<<10)
#define D0_CHANNEL_NONE (0<<10)
#define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y)
#define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z)
/* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse
* or specular declarations.
*
* For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw)
*
* Must be zero for S (sampler) dcls
*/
#define D1_MBZ 0
#define D2_MBZ 0
/* p207 */
#define _3DSTATE_MAP_STATE (CMD_3D|(0x1d<<24)|(0x0<<16))
#define MS1_MAPMASK_SHIFT 0
#define MS1_MAPMASK_MASK (0x8fff<<0)
#define MS2_UNTRUSTED_SURFACE (1<<31)
#define MS2_ADDRESS_MASK 0xfffffffc
#define MS2_VERTICAL_LINE_STRIDE (1<<1)
#define MS2_VERTICAL_OFFSET (1<<1)
#define MS3_HEIGHT_SHIFT 21
#define MS3_WIDTH_SHIFT 10
#define MS3_PALETTE_SELECT (1<<9)
#define MS3_MAPSURF_FORMAT_SHIFT 7
#define MS3_MAPSURF_FORMAT_MASK (0x7<<7)
#define MAPSURF_8BIT (1<<7)
#define MAPSURF_16BIT (2<<7)
#define MAPSURF_32BIT (3<<7)
#define MAPSURF_422 (5<<7)
#define MAPSURF_COMPRESSED (6<<7)
#define MAPSURF_4BIT_INDEXED (7<<7)
#define MS3_MT_FORMAT_MASK (0x7 << 3)
#define MS3_MT_FORMAT_SHIFT 3
#define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */
#define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */
#define MT_8BIT_L8 (1<<3)
#define MT_8BIT_A8 (4<<3)
#define MT_8BIT_MONO8 (5<<3)
#define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */
#define MT_16BIT_ARGB1555 (1<<3)
#define MT_16BIT_ARGB4444 (2<<3)
#define MT_16BIT_AY88 (3<<3)
#define MT_16BIT_88DVDU (5<<3)
#define MT_16BIT_BUMP_655LDVDU (6<<3)
#define MT_16BIT_I16 (7<<3)
#define MT_16BIT_L16 (8<<3)
#define MT_16BIT_A16 (9<<3)
#define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */
#define MT_32BIT_ABGR8888 (1<<3)
#define MT_32BIT_XRGB8888 (2<<3)
#define MT_32BIT_XBGR8888 (3<<3)
#define MT_32BIT_QWVU8888 (4<<3)
#define MT_32BIT_AXVU8888 (5<<3)
#define MT_32BIT_LXVU8888 (6<<3)
#define MT_32BIT_XLVU8888 (7<<3)
#define MT_32BIT_ARGB2101010 (8<<3)
#define MT_32BIT_ABGR2101010 (9<<3)
#define MT_32BIT_AWVU2101010 (0xA<<3)
#define MT_32BIT_GR1616 (0xB<<3)
#define MT_32BIT_VU1616 (0xC<<3)
#define MT_32BIT_xI824 (0xD<<3)
#define MT_32BIT_xA824 (0xE<<3)
#define MT_32BIT_xL824 (0xF<<3)
#define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */
#define MT_422_YCRCB_NORMAL (1<<3)
#define MT_422_YCRCB_SWAPUV (2<<3)
#define MT_422_YCRCB_SWAPUVY (3<<3)
#define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */
#define MT_COMPRESS_DXT2_3 (1<<3)
#define MT_COMPRESS_DXT4_5 (2<<3)
#define MT_COMPRESS_FXT1 (3<<3)
#define MT_COMPRESS_DXT1_RGB (4<<3)
#define MS3_USE_FENCE_REGS (1<<2)
#define MS3_TILED_SURFACE (1<<1)
#define MS3_TILE_WALK (1<<0)
#define MS4_PITCH_SHIFT 21
#define MS4_CUBE_FACE_ENA_NEGX (1<<20)
#define MS4_CUBE_FACE_ENA_POSX (1<<19)
#define MS4_CUBE_FACE_ENA_NEGY (1<<18)
#define MS4_CUBE_FACE_ENA_POSY (1<<17)
#define MS4_CUBE_FACE_ENA_NEGZ (1<<16)
#define MS4_CUBE_FACE_ENA_POSZ (1<<15)
#define MS4_CUBE_FACE_ENA_MASK (0x3f<<15)
#define MS4_MAX_LOD_SHIFT 9
#define MS4_MAX_LOD_MASK (0x3f<<9)
#define MS4_MIP_LAYOUT_LEGACY (0<<8)
#define MS4_MIP_LAYOUT_BELOW_LPT (0<<8)
#define MS4_MIP_LAYOUT_RIGHT_LPT (1<<8)
#define MS4_VOLUME_DEPTH_SHIFT 0
#define MS4_VOLUME_DEPTH_MASK (0xff<<0)
/* p244 */
#define _3DSTATE_SAMPLER_STATE (CMD_3D|(0x1d<<24)|(0x1<<16))
#define SS1_MAPMASK_SHIFT 0
#define SS1_MAPMASK_MASK (0x8fff<<0)
#define SS2_REVERSE_GAMMA_ENABLE (1<<31)
#define SS2_PACKED_TO_PLANAR_ENABLE (1<<30)
#define SS2_COLORSPACE_CONVERSION (1<<29)
#define SS2_CHROMAKEY_SHIFT 27
#define SS2_BASE_MIP_LEVEL_SHIFT 22
#define SS2_BASE_MIP_LEVEL_MASK (0x1f<<22)
#define SS2_MIP_FILTER_SHIFT 20
#define SS2_MIP_FILTER_MASK (0x3<<20)
#define MIPFILTER_NONE 0
#define MIPFILTER_NEAREST 1
#define MIPFILTER_LINEAR 3
#define SS2_MAG_FILTER_SHIFT 17
#define SS2_MAG_FILTER_MASK (0x7<<17)
#define FILTER_NEAREST 0
#define FILTER_LINEAR 1
#define FILTER_ANISOTROPIC 2
#define FILTER_4X4_1 3
#define FILTER_4X4_2 4
#define FILTER_4X4_FLAT 5
#define FILTER_6X5_MONO 6 /* XXX - check */
#define SS2_MIN_FILTER_SHIFT 14
#define SS2_MIN_FILTER_MASK (0x7<<14)
#define SS2_LOD_BIAS_SHIFT 5
#define SS2_LOD_BIAS_ONE (0x10<<5)
#define SS2_LOD_BIAS_MASK (0x1ff<<5)
/* Shadow requires:
* MT_X8{I,L,A}24 or MT_{I,L,A}16 texture format
* FILTER_4X4_x MIN and MAG filters
*/
#define SS2_SHADOW_ENABLE (1<<4)
#define SS2_MAX_ANISO_MASK (1<<3)
#define SS2_MAX_ANISO_2 (0<<3)
#define SS2_MAX_ANISO_4 (1<<3)
#define SS2_SHADOW_FUNC_SHIFT 0
#define SS2_SHADOW_FUNC_MASK (0x7<<0)
/* SS2_SHADOW_FUNC values: see COMPAREFUNC_* */
#define SS3_MIN_LOD_SHIFT 24
#define SS3_MIN_LOD_ONE (0x10<<24)
#define SS3_MIN_LOD_MASK (0xff<<24)
#define SS3_KILL_PIXEL_ENABLE (1<<17)
#define SS3_TCX_ADDR_MODE_SHIFT 12
#define SS3_TCX_ADDR_MODE_MASK (0x7<<12)
#define TEXCOORDMODE_WRAP 0
#define TEXCOORDMODE_MIRROR 1
#define TEXCOORDMODE_CLAMP_EDGE 2
#define TEXCOORDMODE_CUBE 3
#define TEXCOORDMODE_CLAMP_BORDER 4
#define TEXCOORDMODE_MIRROR_ONCE 5
#define SS3_TCY_ADDR_MODE_SHIFT 9
#define SS3_TCY_ADDR_MODE_MASK (0x7<<9)
#define SS3_TCZ_ADDR_MODE_SHIFT 6
#define SS3_TCZ_ADDR_MODE_MASK (0x7<<6)
#define SS3_NORMALIZED_COORDS (1<<5)
#define SS3_TEXTUREMAP_INDEX_SHIFT 1
#define SS3_TEXTUREMAP_INDEX_MASK (0xf<<1)
#define SS3_DEINTERLACER_ENABLE (1<<0)
#define SS4_BORDER_COLOR_MASK (~0)
/* 3DSTATE_SPAN_STIPPLE, p258
*/
#define _3DSTATE_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16))
#define ST1_ENABLE (1<<16)
#define ST1_MASK (0xffff)
#define FLUSH_MAP_CACHE (1<<0)
#define FLUSH_RENDER_CACHE (1<<1)
#endif

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/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86xv.h"
#include "fourcc.h"
#include "i830.h"
#include "i830_video.h"
#include "i915_reg.h"
#include "i915_3d.h"
union intfloat {
CARD32 ui;
float f;
};
#define OUT_RING_F(x) do { \
union intfloat _tmp; \
_tmp.f = x; \
OUT_RING(_tmp.ui); \
} while (0)
void
I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
RegionPtr dstRegion,
short width, short height, int video_pitch,
int x1, int y1, int x2, int y2,
short src_w, short src_h, short drw_w, short drw_h,
DrawablePtr pDraw)
{
I830Ptr pI830 = I830PTR(pScrn);
CARD32 format, ms3, s2;
BoxPtr pbox;
int nbox, dxo, dyo;
Bool planar;
ErrorF("I915DisplayVideo: %dx%d (pitch %d)\n", width, height,
video_pitch);
switch (id) {
case FOURCC_UYVY:
case FOURCC_YUY2:
planar = FALSE;
break;
case FOURCC_YV12:
case FOURCC_I420:
planar = TRUE;
break;
default:
ErrorF("Unknown format 0x%x\n", id);
planar = FALSE;
break;
}
/* Tell the rotation code that we have stomped its invariant state by
* setting a high bit. We don't use any invariant 3D state for video, so we
* don't have to worry about it ourselves.
*/
*pI830->used3D |= 1 << 30;
BEGIN_LP_RING(44);
/* invarient state */
OUT_RING(MI_NOOP);
OUT_RING(_3DSTATE_AA_CMD |
AA_LINE_ECAAR_WIDTH_ENABLE | AA_LINE_ECAAR_WIDTH_1_0 |
AA_LINE_REGION_WIDTH_ENABLE | AA_LINE_REGION_WIDTH_1_0);
OUT_RING(_3DSTATE_DFLT_DIFFUSE_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DFLT_SPEC_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DFLT_Z_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_COORD_SET_BINDINGS | CSB_TCB(0, 0) | CSB_TCB(1, 1) |
CSB_TCB(2,2) | CSB_TCB(3,3) | CSB_TCB(4,4) | CSB_TCB(5,5) |
CSB_TCB(6,6) | CSB_TCB(7,7));
OUT_RING(_3DSTATE_RASTER_RULES_CMD |
ENABLE_TRI_FAN_PROVOKE_VRTX | TRI_FAN_PROVOKE_VRTX(2) |
ENABLE_LINE_STRIP_PROVOKE_VRTX | LINE_STRIP_PROVOKE_VRTX(1) |
ENABLE_TEXKILL_3D_4D | TEXKILL_4D |
ENABLE_POINT_RASTER_RULE | OGL_POINT_RASTER_RULE);
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(3) | 1);
OUT_RING(0x00000000); /* texture coordinate wrap */
/* flush map & render cache */
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
/* draw rect -- just clipping */
OUT_RING(_3DSTATE_DRAW_RECT_CMD);
OUT_RING(0x00000000); /* flags */
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING((pScrn->virtualX - 1) |
(pScrn->virtualY - 1) << 16); /* ymax, xmax */
OUT_RING(0x00000000); /* yorigin, xorigin */
OUT_RING(MI_NOOP);
/* scissor */
OUT_RING(_3DSTATE_SCISSOR_ENABLE_CMD | DISABLE_SCISSOR_RECT);
OUT_RING(_3DSTATE_SCISSOR_RECT_0_CMD);
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING(0x00000000); /* ymax, xmax */
OUT_RING(0x7c000003); /* unknown command */
OUT_RING(0x7d070000);
OUT_RING(0x00000000);
OUT_RING(0x68000002);
/* context setup */
OUT_RING(_3DSTATE_MODES_4_CMD |
ENABLE_LOGIC_OP_FUNC | LOGIC_OP_FUNC(LOGICOP_COPY) |
ENABLE_STENCIL_WRITE_MASK | STENCIL_WRITE_MASK(0xff) |
ENABLE_STENCIL_TEST_MASK | STENCIL_TEST_MASK(0xff));
OUT_RING(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
I1_LOAD_S(4) | I1_LOAD_S(5) | I1_LOAD_S(6) | 4);
s2 = S2_TEXCOORD_FMT(0, TEXCOORDFMT_2D);
if (planar)
s2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_2D);
else
s2 |= S2_TEXCOORD_FMT(1, TEXCOORDFMT_NOT_PRESENT);
s2 |= S2_TEXCOORD_FMT(2, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(3, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(4, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(5, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(6, TEXCOORDFMT_NOT_PRESENT) |
S2_TEXCOORD_FMT(7, TEXCOORDFMT_NOT_PRESENT);
OUT_RING(s2);
OUT_RING((1 << S4_POINT_WIDTH_SHIFT) | S4_LINE_WIDTH_ONE |
S4_CULLMODE_NONE | S4_VFMT_XY);
OUT_RING(0x00000000); /* S5 - enable bits */
OUT_RING((2 << S6_DEPTH_TEST_FUNC_SHIFT) |
(2 << S6_CBUF_SRC_BLEND_FACT_SHIFT) |
(1 << S6_CBUF_DST_BLEND_FACT_SHIFT) | S6_COLOR_WRITE_ENABLE |
(2 << S6_TRISTRIP_PV_SHIFT));
OUT_RING(_3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD |
IAB_MODIFY_ENABLE |
IAB_MODIFY_FUNC | (BLENDFUNC_ADD << IAB_FUNC_SHIFT) |
IAB_MODIFY_SRC_FACTOR | (BLENDFACT_ONE << IAB_SRC_FACTOR_SHIFT) |
IAB_MODIFY_DST_FACTOR | (BLENDFACT_ZERO << IAB_DST_FACTOR_SHIFT));
OUT_RING(_3DSTATE_CONST_BLEND_COLOR_CMD);
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_DST_BUF_VARS_CMD);
if (pI830->cpp == 2)
format = COLR_BUF_RGB565;
else
format = COLR_BUF_ARGB8888 | DEPTH_FRMT_24_FIXED_8_OTHER;
OUT_RING(LOD_PRECLAMP_OGL |
DSTORG_HORT_BIAS(0x80) | DSTORG_VERT_BIAS(0x80) | format);
OUT_RING(_3DSTATE_STIPPLE);
OUT_RING(0x00000000);
/* front buffer, pitch, offset */
OUT_RING(_3DSTATE_BUF_INFO_CMD);
OUT_RING(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
(((pI830->displayWidth * pI830->cpp) / 4) << 2));
OUT_RING(pI830->bufferOffset);
ADVANCE_LP_RING();
if (!planar) {
FS_LOCALS(3);
BEGIN_LP_RING(10);
OUT_RING(_3DSTATE_SAMPLER_STATE | 3);
OUT_RING(0x00000001);
OUT_RING(SS2_COLORSPACE_CONVERSION |
(FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
OUT_RING(0x00000000);
OUT_RING(_3DSTATE_MAP_STATE | 3);
OUT_RING(0x00000001); /* texture map #1 */
OUT_RING(pPriv->YBuf0offset);
ms3 = MAPSURF_422;
switch (id) {
case FOURCC_YUY2:
ms3 |= MT_422_YCRCB_NORMAL;
break;
case FOURCC_UYVY:
ms3 |= MT_422_YCRCB_SWAPY;
break;
}
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
if (!pI830->disableTiling)
ms3 |= MS3_USE_FENCE_REGS;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
ADVANCE_LP_RING();
FS_BEGIN();
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_T0);
i915_fs_texld(FS_OC, FS_S0, FS_T0);
FS_END();
} else {
FS_LOCALS(16);
BEGIN_LP_RING(1 + 18 + 11 + 11);
OUT_RING(MI_NOOP);
/* For the planar formats, we set up three samplers -- one for each plane,
* in a Y8 format. Because I couldn't get the special PLANAR_TO_PACKED
* shader setup to work, I did the manual pixel shader:
*
* y' = y - .0625
* u' = u - .5
* v' = v - .5;
*
* r = 1.1643 * y' + 0.0 * u' + 1.5958 * v'
* g = 1.1643 * y' - 0.39173 * u' - 0.81290 * v'
* b = 1.1643 * y' + 2.017 * u' + 0.0 * v'
*
* register assignment:
* r0 = (y',u',v',0)
* r1 = (y,y,y,y)
* r2 = (u,u,u,u)
* r3 = (v,v,v,v)
* OC = (r,g,b,1)
*/
OUT_RING(_3DSTATE_PIXEL_SHADER_CONSTANTS | 16);
OUT_RING(0x000000f); /* constants 0-3 */
/* constant 0: normalization offsets */
OUT_RING_F(-0.0625);
OUT_RING_F(-0.5);
OUT_RING_F(-0.5);
OUT_RING_F(0.0);
/* constant 1: r coefficients*/
OUT_RING_F(1.1643);
OUT_RING_F(0.0);
OUT_RING_F(1.5958);
OUT_RING_F(0.0);
/* constant 2: g coefficients */
OUT_RING_F(1.1643);
OUT_RING_F(-0.39173);
OUT_RING_F(-0.81290);
OUT_RING_F(0.0);
/* constant 3: b coefficients */
OUT_RING_F(1.1643);
OUT_RING_F(2.017);
OUT_RING_F(0.0);
OUT_RING_F(0.0);
OUT_RING(_3DSTATE_SAMPLER_STATE | 9);
OUT_RING(0x00000007);
/* sampler 0 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
/* sampler 1 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
/* sampler 2 */
OUT_RING(0x00000000);
OUT_RING((FILTER_LINEAR << SS2_MAG_FILTER_SHIFT) |
(FILTER_LINEAR << SS2_MIN_FILTER_SHIFT));
OUT_RING((TEXCOORDMODE_CLAMP_EDGE << SS3_TCX_ADDR_MODE_SHIFT) |
(TEXCOORDMODE_CLAMP_EDGE << SS3_TCY_ADDR_MODE_SHIFT));
OUT_RING(_3DSTATE_MAP_STATE | 9);
OUT_RING(0x00000007);
OUT_RING(pPriv->YBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch * 2 / 4) - 1) << 21);
OUT_RING(pPriv->UBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
OUT_RING(pPriv->VBuf0offset);
ms3 = MAPSURF_8BIT | MT_8BIT_I8;
ms3 |= (height / 2 - 1) << MS3_HEIGHT_SHIFT;
ms3 |= (width / 2 - 1) << MS3_WIDTH_SHIFT;
OUT_RING(ms3);
OUT_RING(((video_pitch / 4) - 1) << 21);
ADVANCE_LP_RING();
FS_BEGIN();
/* Declare samplers */
i915_fs_dcl(FS_S0);
i915_fs_dcl(FS_S1);
i915_fs_dcl(FS_S2);
i915_fs_dcl(FS_T0);
i915_fs_dcl(FS_T1);
/* Load samplers to temporaries. Y (sampler 0) gets the un-halved coords-
* from t1.
*/
i915_fs_texld(FS_R1, FS_S0, FS_T1);
i915_fs_texld(FS_R2, FS_S1, FS_T0);
i915_fs_texld(FS_R3, FS_S2, FS_T0);
/* Move the sampled YUV data in R[123] to the first 3 channels of R0. */
i915_fs_mov_masked(FS_R0, MASK_X, i915_fs_operand_reg(FS_R1));
i915_fs_mov_masked(FS_R0, MASK_Y, i915_fs_operand_reg(FS_R2));
i915_fs_mov_masked(FS_R0, MASK_Z, i915_fs_operand_reg(FS_R3));
/* Normalize the YUV data */
i915_fs_add(FS_R0, i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C0));
/* dot-product the YUV data in R0 by the vectors of coefficients for
* calculating R, G, and B, storing the results in the R, G, or B channels
* of the output color.
*/
i915_fs_dp3_masked(FS_OC, MASK_X | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C1));
i915_fs_dp3_masked(FS_OC, MASK_Y | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C2));
i915_fs_dp3_masked(FS_OC, MASK_Z | MASK_SATURATE,
i915_fs_operand_reg(FS_R0),
i915_fs_operand_reg(FS_C3));
/* Set alpha of the output to 1.0, by wiring W to 1 and not actually using
* the source.
*/
i915_fs_mov_masked(FS_OC, MASK_W, i915_fs_operand_one());
FS_END();
}
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
OUT_RING(0x00000000);
ADVANCE_LP_RING();
}
dxo = dstRegion->extents.x1;
dyo = dstRegion->extents.y1;
pbox = REGION_RECTS(dstRegion);
nbox = REGION_NUM_RECTS(dstRegion);
while (nbox--)
{
int box_x1 = pbox->x1;
int box_y1 = pbox->y1;
int box_x2 = pbox->x2;
int box_y2 = pbox->y2;
float src_scale_x, src_scale_y;
int vert_data_count;
pbox++;
src_scale_x = (float)src_w / (float)drw_w;
src_scale_y = (float)src_h / (float)drw_h;
if (!planar)
vert_data_count = 12;
else
vert_data_count = 18;
BEGIN_LP_RING(vert_data_count + 8);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
/* vertex data - rect list consists of bottom right, bottom left, and top
* left vertices.
*/
OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST |
(vert_data_count - 1));
/* bottom right */
OUT_RING_F(box_x2);
OUT_RING_F(box_y2);
if (!planar) {
OUT_RING_F((box_x2 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x2 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y2 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x2 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
}
/* bottom left */
OUT_RING_F(box_x1);
OUT_RING_F(box_y2);
if (!planar) {
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x1 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y2 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y2 - dyo) * src_scale_y);
}
/* top left */
OUT_RING_F(box_x1);
OUT_RING_F(box_y1);
if (!planar) {
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y1 - dyo) * src_scale_y);
} else {
OUT_RING_F((box_x1 - dxo) * src_scale_x / 2.0);
OUT_RING_F((box_y1 - dyo) * src_scale_y / 2.0);
OUT_RING_F((box_x1 - dxo) * src_scale_x);
OUT_RING_F((box_y1 - dyo) * src_scale_y);
}
ADVANCE_LP_RING();
}
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
}

17
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send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
mov (8) m1<1>F g7<0,1,0>F { align1 };
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
mov (8) m3<1>F g3<8,8,1>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

161
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/* The initial payload of the thread is always g0.
* WM_URB (incoming URB entries) is g3
* X0_R is g4
* X1_R is g5
* Y0_R is g6
* Y1_R is g7
*/
/* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
* subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
* subspan are given in GRF register 1.2 through 1.5 (which, with the word
* addressing below, are 1.4 through 1.11).
*
* The result is WM_X*_R and WM_Y*R being:
*
* X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
* Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
* X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
* Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
*/
/* Set up ss0.x coordinates*/
mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.4<1>F g1.8<0,1,0>UW 1UB { align1 };
mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.12<1>F g1.8<0,1,0>UW 1UB { align1 };
/* Set up ss0.y coordinates */
mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
add (1) g6.8<1>F g1.10<0,1,0>UW 1UB { align1 };
add (1) g6.12<1>F g1.10<0,1,0>UW 1UB { align1 };
/* set up ss1.x coordinates */
mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.20<1>F g1.12<0,1,0>UW 1UB { align1 };
mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.28<1>F g1.12<0,1,0>UW 1UB { align1 };
/* set up ss1.y coordinates */
mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
add (1) g6.24<1>F g1.14<0,1,0>UW 1UB { align1 };
add (1) g6.28<1>F g1.14<0,1,0>UW 1UB { align1 };
/* Set up ss2.x coordinates */
mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.4<1>F g1.16<0,1,0>UW 1UB { align1 };
mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.12<1>F g1.16<0,1,0>UW 1UB { align1 };
/* Set up ss2.y coordinates */
mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
add (1) g7.8<1>F g1.18<0,1,0>UW 1UB { align1 };
add (1) g7.12<1>F g1.18<0,1,0>UW 1UB { align1 };
/* Set up ss3.x coordinates */
mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.20<1>F g1.20<0,1,0>UW 1UB { align1 };
mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.28<1>F g1.20<0,1,0>UW 1UB { align1 };
/* Set up ss3.y coordinates */
mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
add (1) g7.24<1>F g1.22<0,1,0>UW 1UB { align1 };
add (1) g7.28<1>F g1.22<0,1,0>UW 1UB { align1 };
/* Now, map these screen space coordinates into texture coordinates. */
/* subtract screen-space X origin of vertex 0. */
add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
/* add in texture X offset */
add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
/* subtract screen-space Y origin of vertex 0. */
add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
/* scale by texture Y increment */
mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
/* add in texture Y offset */
add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
/* sampler */
mov (8) m1<1>F g4<8,8,1>F { align1 };
mov (8) m2<1>F g5<8,8,1>F { align1 };
mov (8) m3<1>F g6<8,8,1>F { align1 };
mov (8) m4<1>F g7<8,8,1>F { align1 };
/*
* g0 holds the PS thread payload, which (oddly) contains
* precisely what the sampler wants to see in m0
*/
send (16) 0 g12<1>UW g0<8,8,1>UW sampler (1,0,F) mlen 5 rlen 8 { align1 };
mov (8) g19<1>UW g19<8,8,1>UW { align1 };
/* color space conversion function:
* R = Clamp ( 1.164(Y-16/255) + 1.596(Cr-128/255), 0, 1)
* G = Clamp ( 1.164(Y-16/255) - 0.813(Cr-128/255) - 0.392(Cb-128/255), 0, 1)
* B = Clamp ( 1.164(Y-16/255) + 2.017(Cb-128/255), 0, 1)
*
* Y is g14, g15.
* Cr is g12, g13.
* Cb is g16, g17.
*
* R is g2, g6.
* G is g3, g7.
* B is g4, g8.
*/
/* Y = Y - 16/255 */
add (8) g14<1>F g14<8,8,1>F -0.0627451F { align1 };
/* Cr = Cr - 128/255 */
add (8) g12<1>F g12<8,8,1>F -0.501961F { align1 };
/* Cb = Cb - 128 / 255 */
add (8) g16<1>F g16<8,8,1>F -0.501961F { align1 };
/* Y = Y * 1.164 */
mul (8) g14<1>F g14<8,8,1>F 1.164F { align1 };
/* acc = 1.596 * Cr */
mul (8) null g12<8,8,1>F 1.596F { align1 };
/* R = acc + Y */
mac.sat (8) m2<1>F g14<8,8,1>F 1F { align1 };
/* acc = Cr * -0.813 */
mul (8) null g12<8,8,1>F -0.813F { align1 };
/* acc += Cb * -0.392 */
mac (8) null g16<8,8,1>F -0.392F { align1 };
/* G = acc + Y */
mac.sat (8) m3<1>F g14<8,8,1>F 1F { align1 };
/* acc = Cb * 2.017 */
mul (8) null g16<8,8,1>F 2.017F { align1 };
/* B = acc + Y */
mac.sat (8) m4<1>F g14<8,8,1>F 1F { align1 };
/* and do it again */
add (8) g15<1>F g15<8,8,1>F -0.0627451F { align1 };
add (8) g13<1>F g13<8,8,1>F -0.501961F { align1 };
add (8) g17<1>F g17<8,8,1>F -0.501961F { align1 };
mul (8) g15<1>F g15<8,8,1>F 1.164F { align1 };
mul (8) null g13<8,8,1>F 1.596F { align1 };
mac.sat (8) m6<1>F g15<8,8,1>F 1F { align1 };
mul (8) null g13<8,8,1>F -0.813F { align1 };
mac (8) null g17<8,8,1>F -0.392F { align1 };
mac.sat (8) m7<1>F g15<8,8,1>F 1F { align1 };
mul (8) null g17<8,8,1>F 2.017F { align1 };
mac.sat (8) m8<1>F g15<8,8,1>F 1F { align1 };
/* Pass through control information:
*/
mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
/* Send framebuffer write message: XXX: acc0? */
send (16) 0 null g0<8,8,1>UW write (
0, /* binding table index 0 */
8, /* pixel scoreboard clear */
4, /* render target write */
0 /* no write commit message */
) mlen 10 rlen 0 { align1 EOT };
/* padding */
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

17
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{ 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
{ 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

82
src/wm_prog.h Normal file
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@ -0,0 +1,82 @@
{ 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
{ 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
{ 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
{ 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
{ 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
{ 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
{ 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
{ 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
{ 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
{ 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
{ 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
{ 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
{ 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
{ 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
{ 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
{ 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
{ 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
{ 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
{ 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
{ 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
{ 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
{ 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
{ 0x00600001, 0x22600129, 0x008d0260, 0x00000000 },
{ 0x00600040, 0x21c07fbd, 0x008d01c0, 0xbd808081 },
{ 0x00600040, 0x21807fbd, 0x008d0180, 0xbf008084 },
{ 0x00600040, 0x22007fbd, 0x008d0200, 0xbf008084 },
{ 0x00600041, 0x21c07fbd, 0x008d01c0, 0x3f94fdf4 },
{ 0x00600041, 0x20007fbc, 0x008d0180, 0x3fcc49ba },
{ 0x80600048, 0x20407fbe, 0x008d01c0, 0x3f800000 },
{ 0x00600041, 0x20007fbc, 0x008d0180, 0xbf5020c5 },
{ 0x00600048, 0x20007fbc, 0x008d0200, 0xbec8b439 },
{ 0x80600048, 0x20607fbe, 0x008d01c0, 0x3f800000 },
{ 0x00600041, 0x20007fbc, 0x008d0200, 0x40011687 },
{ 0x80600048, 0x20807fbe, 0x008d01c0, 0x3f800000 },
{ 0x00600040, 0x21e07fbd, 0x008d01e0, 0xbd808081 },
{ 0x00600040, 0x21a07fbd, 0x008d01a0, 0xbf008084 },
{ 0x00600040, 0x22207fbd, 0x008d0220, 0xbf008084 },
{ 0x00600041, 0x21e07fbd, 0x008d01e0, 0x3f94fdf4 },
{ 0x00600041, 0x20007fbc, 0x008d01a0, 0x3fcc49ba },
{ 0x80600048, 0x20c07fbe, 0x008d01e0, 0x3f800000 },
{ 0x00600041, 0x20007fbc, 0x008d01a0, 0xbf5020c5 },
{ 0x00600048, 0x20007fbc, 0x008d0220, 0xbec8b439 },
{ 0x80600048, 0x20e07fbe, 0x008d01e0, 0x3f800000 },
{ 0x00600041, 0x20007fbc, 0x008d0220, 0x40011687 },
{ 0x80600048, 0x21007fbe, 0x008d01e0, 0x3f800000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x20001d3c, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
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