sna/dri2: Consolidate vblank queueing into a couple of helpers
With the rigamorale of assertions, using the vblank is no longer trivial. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
e29dc33e35
commit
6f3e81d430
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@ -1413,15 +1413,53 @@ inline static uint32_t pipe_select(int pipe)
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return 0;
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}
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static inline int sna_wait_vblank(struct sna *sna, union drm_wait_vblank *vbl, int pipe)
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static inline bool sna_next_vblank(struct sna_dri2_event *info)
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{
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DBG(("%s(pipe=%d, waiting until seq=%u%s)\n",
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__FUNCTION__, pipe, vbl->request.sequence,
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vbl->request.type & DRM_VBLANK_RELATIVE ? " [relative]" : ""));
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assert(pipe != -1);
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union drm_wait_vblank vbl;
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vbl->request.type |= pipe_select(pipe);
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return drmIoctl(sna->kgem.fd, DRM_IOCTL_WAIT_VBLANK, vbl);
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DBG(("%s(pipe=%d, waiting until next vblank)\n",
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__FUNCTION__, info->pipe));
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assert(info->pipe != -1);
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT |
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pipe_select(info->pipe);
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (drmIoctl(info->sna->kgem.fd, DRM_IOCTL_WAIT_VBLANK, &vbl))
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return false;
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info->queued = true;
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return true;
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}
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static inline bool sna_wait_vblank(struct sna_dri2_event *info,
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unsigned seq)
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{
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union drm_wait_vblank vbl;
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DBG(("%s(pipe=%d, waiting until vblank %u)\n",
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__FUNCTION__, info->pipe, seq));
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assert(info->pipe != -1);
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_ABSOLUTE |
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DRM_VBLANK_EVENT |
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pipe_select(info->pipe);
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vbl.request.sequence = seq;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (drmIoctl(info->sna->kgem.fd, DRM_IOCTL_WAIT_VBLANK, &vbl))
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return false;
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info->queued = true;
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return true;
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}
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#if DRI2INFOREC_VERSION >= 4
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@ -2376,8 +2414,6 @@ static void sna_dri2_xchg_crtc(struct sna *sna, DrawablePtr draw, xf86CrtcPtr cr
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static void chain_swap(struct sna_dri2_event *chain)
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{
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union drm_wait_vblank vbl;
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DBG(("%s: draw=%ld, queued?=%d, type=%d\n",
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__FUNCTION__, (long)chain->draw->id, chain->queued, chain->type));
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@ -2399,18 +2435,8 @@ static void chain_swap(struct sna_dri2_event *chain)
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!chain->sna->mode.shadow_damage) {
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/* recursed from wait_for_shadow(), simply requeue */
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DBG(("%s -- recursed from wait_for_shadow(), requeuing\n", __FUNCTION__));
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)chain;
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assert(!chain->queued);
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if (!sna_wait_vblank(chain->sna, &vbl, chain->pipe)) {
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chain->queued = true;
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if (sna_next_vblank(chain))
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return;
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}
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DBG(("%s -- requeue failed, errno=%d\n", __FUNCTION__, errno));
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}
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@ -2431,23 +2457,14 @@ static void chain_swap(struct sna_dri2_event *chain)
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return;
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}
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)chain;
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assert(!chain->queued);
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if ((chain->type == SWAP_COMPLETE &&
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!swap_limit(chain->draw, 2 + !chain->sync) &&
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!chain->sync) ||
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sna_wait_vblank(chain->sna, &vbl, chain->pipe)) {
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!sna_next_vblank(chain)) {
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DBG(("%s: vblank wait failed, unblocking client\n", __FUNCTION__));
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frame_swap_complete(chain, DRI2_BLIT_COMPLETE);
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sna_dri2_event_free(chain);
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} else
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chain->queued = true;
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}
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}
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static inline bool rq_is_busy(struct kgem *kgem, struct kgem_bo *bo)
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@ -2468,27 +2485,13 @@ static inline bool rq_is_busy(struct kgem *kgem, struct kgem_bo *bo)
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return __kgem_busy(kgem, bo->handle);
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}
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static bool sna_dri2_blit_complete(struct sna *sna,
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struct sna_dri2_event *info)
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static bool sna_dri2_blit_complete(struct sna_dri2_event *info)
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{
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if (rq_is_busy(&sna->kgem, info->bo)) {
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union drm_wait_vblank vbl;
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if (rq_is_busy(&info->sna->kgem, info->bo)) {
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DBG(("%s: vsync'ed blit is still busy, postponing\n",
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__FUNCTION__));
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (!sna_wait_vblank(sna, &vbl, info->pipe)) {
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info->queued = true;
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if (sna_next_vblank(info))
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return false;
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}
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}
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DBG(("%s: blit finished\n", __FUNCTION__));
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@ -2501,7 +2504,6 @@ void sna_dri2_vblank_handler(struct drm_event_vblank *event)
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struct sna_dri2_event *info = (void *)(uintptr_t)event->user_data;
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struct sna *sna = info->sna;
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DrawablePtr draw;
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union drm_wait_vblank vbl;
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uint64_t msc;
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DBG(("%s(type=%d, sequence=%d, draw=%ld)\n", __FUNCTION__, info->type, event->sequence, info->draw ? info->draw->serialNumber : 0));
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@ -2543,18 +2545,8 @@ void sna_dri2_vblank_handler(struct drm_event_vblank *event)
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info->type = SWAP_COMPLETE;
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}
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (!sna_wait_vblank(sna, &vbl, info->pipe)) {
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info->queued = true;
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if (sna_next_vblank(info))
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return;
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}
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DBG(("%s -- requeue failed, errno=%d\n", __FUNCTION__, errno));
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assert(info->pending.bo == NULL);
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@ -2566,7 +2558,7 @@ void sna_dri2_vblank_handler(struct drm_event_vblank *event)
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event->sequence, event->tv_sec, event->tv_usec));
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if (info->signal) {
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if (!sna_dri2_blit_complete(sna, info))
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if (!sna_dri2_blit_complete(info))
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return;
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DBG(("%s: triple buffer swap complete, unblocking client (frame=%d, tv=%d.%06d)\n", __FUNCTION__,
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@ -2607,18 +2599,8 @@ void sna_dri2_vblank_handler(struct drm_event_vblank *event)
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}
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if (--info->keepalive) {
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (!sna_wait_vblank(sna, &vbl, info->pipe)) {
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info->queued = true;
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if (sna_next_vblank(info))
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return;
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}
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if (info->signal) {
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DBG(("%s: triple buffer swap complete, unblocking client (frame=%d, tv=%d.%06d)\n", __FUNCTION__,
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@ -2672,8 +2654,6 @@ sna_dri2_immediate_blit(struct sna *sna,
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info->keepalive = KEEPALIVE;
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if (chain == info) {
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union drm_wait_vblank vbl;
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DBG(("%s: no pending blit, starting chain\n", __FUNCTION__));
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if (can_xchg(info->sna, info->draw, info->front, info->back)) {
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@ -2687,21 +2667,12 @@ sna_dri2_immediate_blit(struct sna *sna,
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assert(info->signal);
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if ((!swap_limit(draw, 2 + !sync) && !sync) ||
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sna_wait_vblank(sna, &vbl, info->pipe)) {
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!sna_next_vblank(info)) {
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DBG(("%s: fake triple buffering, unblocking client\n", __FUNCTION__));
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frame_swap_complete(info, DRI2_BLIT_COMPLETE);
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sna_dri2_event_free(info);
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}
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info->queued = true;
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return;
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}
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@ -2822,24 +2793,10 @@ static void chain_flip(struct sna *sna)
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__sna_dri2_copy_event(chain, DRI2_SYNC);
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if (xorg_can_triple_buffer()) {
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union drm_wait_vblank vbl;
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VG_CLEAR(vbl);
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chain->type = SWAP_COMPLETE;
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assert(chain->signal);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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vbl.request.signal = (uintptr_t)chain;
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assert(!chain->queued);
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if (!sna_wait_vblank(sna, &vbl, chain->pipe)) {
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chain->queued = true;
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if (sna_next_vblank(chain))
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return;
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}
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}
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DBG(("%s: fake triple buffering (or vblank wait failed), unblocking client\n", __FUNCTION__));
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@ -2913,16 +2870,24 @@ static void sna_dri2_flip_event(struct sna_dri2_event *flip)
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}
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}
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static int
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sna_query_vblank(struct sna *sna, xf86CrtcPtr crtc, union drm_wait_vblank *vbl)
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{
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VG_CLEAR(*vbl);
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vbl->request.type =
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_DRM_VBLANK_RELATIVE | pipe_select(sna_crtc_pipe(crtc));
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vbl->request.sequence = 0;
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return drmIoctl(sna->kgem.fd, DRM_IOCTL_WAIT_VBLANK, vbl);
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}
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static uint64_t
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get_current_msc(struct sna *sna, DrawablePtr draw, xf86CrtcPtr crtc)
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{
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union drm_wait_vblank vbl;
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uint64_t ret;
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VG_CLEAR(vbl);
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vbl.request.type = _DRM_VBLANK_RELATIVE;
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vbl.request.sequence = 0;
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if (sna_wait_vblank(sna, &vbl, sna_crtc_pipe(crtc)) == 0)
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if (sna_query_vblank(sna, crtc, &vbl) == 0)
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ret = sna_crtc_record_vblank(crtc, &vbl);
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else
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ret = sna_crtc_last_swap(crtc)->msc;
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@ -3142,25 +3107,12 @@ queue:
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if (*target_msc <= current_msc + 1 && sna_dri2_flip(info)) {
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*target_msc = current_msc + 1;
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} else {
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union drm_wait_vblank vbl;
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_ABSOLUTE |
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DRM_VBLANK_EVENT;
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/* Account for 1 frame extra pageflip delay */
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vbl.reply.sequence = draw_target_seq(draw, *target_msc - 1);
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vbl.request.signal = (uintptr_t)info;
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assert(!info->queued);
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if (sna_wait_vblank(sna, &vbl, info->pipe)) {
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if (!sna_wait_vblank(info,
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draw_target_seq(draw, *target_msc - 1))) {
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sna_dri2_event_free(info);
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return false;
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}
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info->queued = true;
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}
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DBG(("%s: reported target_msc=%llu\n", __FUNCTION__, *target_msc));
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@ -3202,7 +3154,6 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
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CARD64 remainder, DRI2SwapEventPtr func, void *data)
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{
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struct sna *sna = to_sna_from_drawable(draw);
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union drm_wait_vblank vbl;
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xf86CrtcPtr crtc = NULL;
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struct sna_dri2_event *info = NULL;
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int type = DRI2_EXCHANGE_COMPLETE;
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@ -3296,8 +3247,6 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
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func, data))
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return TRUE;
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VG_CLEAR(vbl);
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info = sna_dri2_add_event(sna, draw, client, crtc);
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if (!info)
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goto blit;
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@ -3319,32 +3268,28 @@ sna_dri2_schedule_swap(ClientPtr client, DrawablePtr draw, DRI2BufferPtr front,
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return TRUE;
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}
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vbl.request.type =
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DRM_VBLANK_ABSOLUTE |
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DRM_VBLANK_EVENT;
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vbl.request.signal = (uintptr_t)info;
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info->type = SWAP;
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vbl.request.sequence = draw_target_seq(draw, *target_msc - 1);
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if (*target_msc <= current_msc + 1) {
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DBG(("%s: performing blit before queueing\n", __FUNCTION__));
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__sna_dri2_copy_event(info, DRI2_SYNC);
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info->type = SWAP_COMPLETE;
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if (!sna_next_vblank(info))
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goto fake;
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.sequence = 1;
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DBG(("%s: reported target_msc=%llu\n",
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__FUNCTION__, *target_msc));
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*target_msc = current_msc + 1;
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swap_limit(draw, 2);
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} else {
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if (!sna_wait_vblank(info,
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draw_target_seq(draw, *target_msc - 1)))
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goto blit;
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DBG(("%s: reported target_msc=%llu (in)\n",
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__FUNCTION__, *target_msc));
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swap_limit(draw, 1);
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}
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assert(!info->queued);
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if (sna_wait_vblank(sna, &vbl, info->pipe))
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goto blit;
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info->queued = true;
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DBG(("%s: reported target_msc=%llu\n", __FUNCTION__, *target_msc));
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swap_limit(draw, 1 + (info->type == SWAP_COMPLETE));
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return TRUE;
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blit:
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@ -3366,7 +3311,7 @@ skip:
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if (info != dri2_chain(draw))
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goto fake;
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assert(info->crtc == crtc);
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assert(info->crtc == crtc);
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info->type = SWAP_COMPLETE;
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info->event_complete = func;
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@ -3376,18 +3321,9 @@ skip:
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info->front = sna_dri2_reference_buffer(front);
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info->back = sna_dri2_reference_buffer(back);
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VG_CLEAR(vbl);
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vbl.request.type =
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DRM_VBLANK_RELATIVE |
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DRM_VBLANK_EVENT;
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vbl.request.signal = (uintptr_t)info;
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vbl.request.sequence = 1;
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assert(!info->queued);
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if (sna_wait_vblank(sna, &vbl, info->pipe))
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if (!sna_next_vblank(info))
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goto fake;
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info->queued = true;
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swap_limit(draw, 2);
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} else {
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fake:
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@ -3412,21 +3348,16 @@ sna_dri2_get_msc(DrawablePtr draw, CARD64 *ust, CARD64 *msc)
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struct sna *sna = to_sna_from_drawable(draw);
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xf86CrtcPtr crtc = sna_dri2_get_crtc(draw);
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const struct ust_msc *swap;
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union drm_wait_vblank vbl;
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DBG(("%s(draw=%ld, pipe=%d)\n", __FUNCTION__, draw->id,
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crtc ? sna_crtc_pipe(crtc) : -1));
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if (crtc != NULL) {
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union drm_wait_vblank vbl;
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|
||||
VG_CLEAR(vbl);
|
||||
vbl.request.type = _DRM_VBLANK_RELATIVE;
|
||||
vbl.request.sequence = 0;
|
||||
if (sna_wait_vblank(sna, &vbl, sna_crtc_pipe(crtc)) == 0)
|
||||
sna_crtc_record_vblank(crtc, &vbl);
|
||||
} else
|
||||
/* Drawable not displayed, make up a *monotonic* value */
|
||||
/* Drawable not displayed, make up a *monotonic* value */
|
||||
if (crtc == NULL)
|
||||
crtc = sna_primary_crtc(sna);
|
||||
if (sna_query_vblank(sna, crtc, &vbl) == 0)
|
||||
sna_crtc_record_vblank(crtc, &vbl);
|
||||
|
||||
swap = sna_crtc_last_swap(crtc);
|
||||
*msc = draw_current_msc(draw, crtc, swap->msc);
|
||||
|
|
@ -3450,7 +3381,6 @@ sna_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc
|
|||
struct sna_dri2_event *info = NULL;
|
||||
xf86CrtcPtr crtc;
|
||||
CARD64 current_msc;
|
||||
union drm_wait_vblank vbl;
|
||||
const struct ust_msc *swap;
|
||||
|
||||
crtc = sna_dri2_get_crtc(draw);
|
||||
|
|
@ -3484,8 +3414,6 @@ sna_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc
|
|||
assert(info->crtc == crtc);
|
||||
info->type = WAITMSC;
|
||||
|
||||
vbl.request.signal = (uintptr_t)info;
|
||||
vbl.request.type = DRM_VBLANK_ABSOLUTE | DRM_VBLANK_EVENT;
|
||||
/*
|
||||
* If divisor is zero, or current_msc is smaller than target_msc,
|
||||
* we just need to make sure target_msc passes before waking up the
|
||||
|
|
@ -3502,13 +3430,10 @@ sna_dri2_schedule_wait_msc(ClientPtr client, DrawablePtr draw, CARD64 target_msc
|
|||
if (target_msc <= current_msc)
|
||||
target_msc += divisor;
|
||||
}
|
||||
vbl.request.sequence = draw_target_seq(draw, target_msc);
|
||||
|
||||
assert(!info->queued);
|
||||
if (sna_wait_vblank(sna, &vbl, info->pipe))
|
||||
if (!sna_wait_vblank(info, draw_target_seq(draw, target_msc)))
|
||||
goto out_free_info;
|
||||
|
||||
info->queued = true;
|
||||
DRI2BlockClient(client, draw);
|
||||
return TRUE;
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue