Add XV support on IGDNG
This brings necessary change for IGDNG for texture video support from 2D render code. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
This commit is contained in:
Zhenyu Wang
parent
f806fe7d67
commit
7770958e42
188
src/i965_video.c
188
src/i965_video.c
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@ -110,6 +110,27 @@ static const uint32_t ps_kernel_planar_static[][4] = {
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#include "exa_wm_write.g4b"
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};
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/* new program for IGDNG */
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static const uint32_t sf_kernel_static_gen5[][4] = {
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#include "exa_sf.g4b.gen5"
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};
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static const uint32_t ps_kernel_packed_static_gen5[][4] = {
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#include "exa_wm_xy.g4b.gen5"
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#include "exa_wm_src_affine.g4b.gen5"
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#include "exa_wm_src_sample_argb.g4b.gen5"
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#include "exa_wm_yuv_rgb.g4b.gen5"
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#include "exa_wm_write.g4b.gen5"
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};
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static const uint32_t ps_kernel_planar_static_gen5[][4] = {
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#include "exa_wm_xy.g4b.gen5"
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#include "exa_wm_src_affine.g4b.gen5"
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#include "exa_wm_src_sample_planar.g4b.gen5"
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#include "exa_wm_yuv_rgb.g4b.gen5"
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#include "exa_wm_write.g4b.gen5"
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};
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#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
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#define MIN(a,b) ((a) < (b) ? (a) : (b))
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@ -498,7 +519,10 @@ i965_create_vs_state(ScrnInfoPtr scrn)
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return NULL;
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/* Set up the vertex shader to be disabled (passthrough) */
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vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
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if (IS_IGDNG(pI830))
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vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES >> 2;
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else
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vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
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vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
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vs_state->vs6.vs_enable = 0;
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vs_state->vs6.vert_cache_disable = 1;
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@ -531,8 +555,12 @@ i965_create_sf_state(ScrnInfoPtr scrn)
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drm_intel_bo *sf_bo, *kernel_bo;
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struct brw_sf_unit_state *sf_state;
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kernel_bo = i965_create_program(scrn, &sf_kernel_static[0][0],
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sizeof(sf_kernel_static));
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if (IS_IGDNG(pI830))
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kernel_bo = i965_create_program(scrn, &sf_kernel_static_gen5[0][0],
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sizeof(sf_kernel_static_gen5));
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else
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kernel_bo = i965_create_program(scrn, &sf_kernel_static[0][0],
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sizeof(sf_kernel_static));
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if (!kernel_bo)
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return NULL;
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@ -591,11 +619,19 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
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struct brw_wm_unit_state *wm_state;
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if (is_packed) {
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kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static[0][0],
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sizeof(ps_kernel_packed_static));
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if (IS_IGDNG(pI830))
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kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static_gen5[0][0],
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sizeof(ps_kernel_packed_static_gen5));
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else
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kernel_bo = i965_create_program(scrn, &ps_kernel_packed_static[0][0],
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sizeof(ps_kernel_packed_static));
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} else {
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kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static[0][0],
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sizeof(ps_kernel_planar_static));
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if (IS_IGDNG(pI830))
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kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static_gen5[0][0],
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sizeof(ps_kernel_planar_static_gen5));
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else
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kernel_bo = i965_create_program(scrn, &ps_kernel_planar_static[0][0],
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sizeof(ps_kernel_planar_static));
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}
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if (!kernel_bo)
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return NULL;
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@ -616,6 +652,13 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
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wm_state->thread1.binding_table_entry_count = 2;
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else
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wm_state->thread1.binding_table_entry_count = 7;
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/* binding table entry count is only used for prefetching, and it has to
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* be set 0 for IGDNG
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*/
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if (IS_IGDNG(pI830))
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wm_state->thread1.binding_table_entry_count = 0;
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/* Though we never use the scratch space in our WM kernel, it has to be
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* set, and the minimum allocation is 1024 bytes.
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*/
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@ -631,7 +674,10 @@ i965_create_wm_state(ScrnInfoPtr scrn, drm_intel_bo *sampler_bo, Bool is_packed)
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intel_emit_reloc(wm_bo, offsetof(struct brw_wm_unit_state, wm4),
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sampler_bo, 0,
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I915_GEM_DOMAIN_INSTRUCTION, 0) >> 5;
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wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
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if (IS_IGDNG(pI830))
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wm_state->wm4.sampler_count = 0;
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else
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wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
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wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
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wm_state->wm5.thread_dispatch_enable = 1;
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wm_state->wm5.enable_16_pix = 1;
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@ -713,6 +759,7 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
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int urb_clip_start, urb_clip_size;
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int urb_sf_start, urb_sf_size;
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int urb_cs_start, urb_cs_size;
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int pipe_ctl;
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IntelEmitInvarientState(pScrn);
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pI830->last_3d = LAST_3D_VIDEO;
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@ -736,9 +783,12 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
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ADVANCE_BATCH();
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/* brw_debug (pScrn, "before base address modify"); */
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BEGIN_BATCH(12);
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if (IS_IGDNG(pI830))
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BEGIN_BATCH(14);
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else
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BEGIN_BATCH(12);
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/* Match Mesa driver setup */
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if (IS_G4X(pI830))
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if (IS_G4X(pI830) || IS_IGDNG(pI830))
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OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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else
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OUT_BATCH(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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@ -751,14 +801,28 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
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/* Zero out the two base address registers so all offsets are
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* absolute
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*/
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
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/* general state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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/* media object state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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if (IS_IGDNG(pI830)) {
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
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/* general state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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/* media object state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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/* Instruction max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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} else {
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
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/* general state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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/* media object state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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}
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/* Set system instruction pointer */
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OUT_BATCH(BRW_STATE_SIP | 0);
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@ -771,14 +835,17 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
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/* brw_debug (pScrn, "after base address modify"); */
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if (IS_IGDNG(pI830))
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pipe_ctl = BRW_PIPE_CONTROL_NOWRITE;
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else
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pipe_ctl = BRW_PIPE_CONTROL_NOWRITE | BRW_PIPE_CONTROL_IS_FLUSH;
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BEGIN_BATCH(38);
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OUT_BATCH(MI_NOOP);
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/* Pipe control */
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OUT_BATCH(BRW_PIPE_CONTROL |
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BRW_PIPE_CONTROL_NOWRITE |
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BRW_PIPE_CONTROL_IS_FLUSH |
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2);
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OUT_BATCH(BRW_PIPE_CONTROL | pipe_ctl | 2);
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OUT_BATCH(0); /* Destination address */
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OUT_BATCH(0); /* Immediate data low DW */
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OUT_BATCH(0); /* Immediate data high DW */
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@ -849,27 +916,50 @@ i965_emit_video_setup(ScrnInfoPtr pScrn, drm_intel_bo *bind_bo, int n_src_surf)
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(URB_CS_ENTRIES << 0));
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/* Set up our vertex elements, sourced from the single vertex buffer. */
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OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
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/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(0 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
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(0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
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/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(8 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
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(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
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if (IS_IGDNG(pI830)) {
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OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
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/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(0 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
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/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(8 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT));
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} else {
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OUT_BATCH(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
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/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(0 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
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(0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
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/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
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OUT_BATCH((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
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VE0_VALID |
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(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
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(8 << VE0_OFFSET_SHIFT));
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OUT_BATCH((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
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(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
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(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
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(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
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}
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OUT_BATCH(MI_NOOP); /* pad to quadword */
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ADVANCE_BATCH();
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@ -1112,7 +1202,8 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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drm_intel_bo_unmap(vb_bo);
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i965_pre_draw_debug(pScrn);
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if (!IS_IGDNG(pI830))
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i965_pre_draw_debug(pScrn);
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/* If this command won't fit in the current batch, flush.
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* Assume that it does after being flushed.
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@ -1134,7 +1225,10 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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VB0_VERTEXDATA |
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((4 * 4) << VB0_BUFFER_PITCH_SHIFT));
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OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
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OUT_BATCH(3); /* four corners to our rectangle */
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if (IS_IGDNG(pI830))
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OUT_RELOC(vb_bo, I915_GEM_DOMAIN_VERTEX, 0, (vb_bo->offset + i) * 4);
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else
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OUT_BATCH(3); /* four corners to our rectangle */
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OUT_BATCH(0); /* reserved */
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OUT_BATCH(BRW_3DPRIMITIVE |
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@ -1154,7 +1248,9 @@ I965DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
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drm_intel_bo_unreference(vb_bo);
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i965_post_draw_debug(pScrn);
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if (!IS_IGDNG(pI830))
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i965_post_draw_debug(pScrn);
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}
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/* release reference once we're finished */
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