Clean up more i830_memory.c madness.
It was cooking up insane alignment values for buffers that new libdrm was justifiably complaining about, but it turns out we don't need the alignment values anywhere because the only case they're needed, they're computed entirely by the kernel. Also, the XVMC code was passing a completely unused flag in.
This commit is contained in:
Eric Anholt
parent
d525a0e993
commit
8b2d2ff0d0
15
src/i830.h
15
src/i830.h
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@ -93,12 +93,6 @@ typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr;
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#define ALWAYS_SYNC 0
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#define ALWAYS_FLUSH 0
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enum tile_format {
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TILE_NONE,
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TILE_XMAJOR,
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TILE_YMAJOR
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};
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#define PITCH_NONE 0
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/** Record of a linear allocation in the aperture. */
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@ -115,7 +109,7 @@ struct _i830_memory {
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*/
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unsigned long size;
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enum tile_format tiling;
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uint32_t tiling_mode;
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/** Pitch value in bytes for tiled surfaces */
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unsigned int pitch;
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@ -130,7 +124,6 @@ struct _i830_memory {
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/** @} */
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dri_bo *bo;
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uint32_t alignment;
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uint32_t gem_name;
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};
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@ -351,8 +344,7 @@ Bool i830_allocator_init(ScrnInfoPtr scrn, unsigned long size);
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void i830_allocator_fini(ScrnInfoPtr scrn);
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i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
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unsigned long size, unsigned long pitch,
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unsigned long alignment, int flags,
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enum tile_format tile_format);
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int flags, uint32_t tile_format);
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void i830_describe_allocations(ScrnInfoPtr scrn, int verbosity,
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const char *prefix);
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void i830_reset_allocations(ScrnInfoPtr scrn);
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@ -376,7 +368,7 @@ int i830_pad_drawable_width(int width, int cpp);
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Bool i830_bind_all_memory(ScrnInfoPtr scrn);
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unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long size);
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unsigned long i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
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int format);
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uint32_t tiling_mode);
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void i830_set_max_gtt_map_size(ScrnInfoPtr scrn);
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i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn);
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@ -486,7 +478,6 @@ extern const int I830CopyROP[16];
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/* Flags for memory allocation function */
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#define NEED_PHYSICAL_ADDR 0x00000001
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#define ALIGN_BOTH_ENDS 0x00000002
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#define ALLOW_SHARING 0x00000010
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#define DISABLE_REUSE 0x00000020
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@ -147,7 +147,7 @@ Bool intel_xvmc_init_batch(ScrnInfoPtr scrn)
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if (!i830_allocate_xvmc_buffer(scrn, "[XvMC] batch buffer",
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&(xvmc_driver->batch), size,
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ALIGN_BOTH_ENDS))
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0))
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return FALSE;
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if (drmAddMap(intel->drmSubFD,
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@ -122,12 +122,13 @@ unsigned long i830_get_fence_size(intel_screen_private *intel, unsigned long siz
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* calculate that here.
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*/
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unsigned long
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i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int format)
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i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch,
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uint32_t tiling_mode)
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{
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unsigned long i;
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unsigned long tile_width = (format == I915_TILING_Y) ? 128 : 512;
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unsigned long tile_width = (tiling_mode == I915_TILING_Y) ? 128 : 512;
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if (format == TILE_NONE)
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if (tiling_mode == I915_TILING_NONE)
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return pitch;
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/* 965 is flexible */
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@ -140,18 +141,6 @@ i830_get_fence_pitch(intel_screen_private *intel, unsigned long pitch, int forma
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return i;
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}
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/**
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* On some chips, pitch width has to be a power of two tile width, so
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* calculate that here.
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*/
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static unsigned long i830_get_fence_alignment(intel_screen_private *intel, unsigned long size)
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{
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if (IS_I965G(intel))
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return 4096;
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else
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return i830_get_fence_size(intel, size);
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}
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static Bool
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i830_check_display_stride(ScrnInfoPtr scrn, int stride, Bool tiling)
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{
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@ -298,85 +287,6 @@ void i830_allocator_fini(ScrnInfoPtr scrn)
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intel->memory_list = NULL;
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}
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static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
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unsigned long size,
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unsigned long pitch,
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unsigned long align, int flags,
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enum tile_format tile_format)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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i830_memory *mem;
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uint32_t bo_tiling_mode = I915_TILING_NONE;
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int ret;
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assert((flags & NEED_PHYSICAL_ADDR) == 0);
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/* Only allocate page-sized increments. */
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size = ALIGN(size, GTT_PAGE_SIZE);
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align = i830_get_fence_alignment(intel, size);
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mem = xcalloc(1, sizeof(*mem));
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if (mem == NULL)
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return NULL;
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mem->name = xstrdup(name);
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if (mem->name == NULL) {
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xfree(mem);
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return NULL;
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}
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mem->bo = dri_bo_alloc(intel->bufmgr, name, size, align);
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if (!mem->bo) {
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xfree(mem->name);
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xfree(mem);
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return NULL;
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}
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/* Give buffer obviously wrong offset/end until it's pinned. */
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mem->offset = -1;
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mem->end = -1;
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mem->size = size;
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mem->alignment = align;
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mem->tiling = tile_format;
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mem->pitch = pitch;
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switch (tile_format) {
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case TILE_XMAJOR:
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bo_tiling_mode = I915_TILING_X;
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break;
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case TILE_YMAJOR:
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bo_tiling_mode = I915_TILING_Y;
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break;
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case TILE_NONE:
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default:
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bo_tiling_mode = I915_TILING_NONE;
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break;
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}
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ret = drm_intel_bo_set_tiling(mem->bo, &bo_tiling_mode, pitch);
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if (ret != 0
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|| (bo_tiling_mode == I915_TILING_NONE
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&& tile_format != TILE_NONE)) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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"Failed to set tiling on %s: %s\n", mem->name,
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ret == 0 ? "rejected by kernel" : strerror(errno));
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mem->tiling = TILE_NONE;
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}
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if (flags & DISABLE_REUSE)
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drm_intel_bo_disable_reuse(mem->bo);
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/* Insert new allocation into the list */
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mem->prev = NULL;
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mem->next = intel->bo_list;
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if (intel->bo_list != NULL)
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intel->bo_list->prev = mem;
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intel->bo_list = mem;
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return mem;
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}
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/* Allocates video memory at the given size, pitch, alignment and tile format.
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*
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* The memory will be bound automatically when the driver is in control of the
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@ -387,8 +297,6 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
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* flags:
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* - NEED_PHYSICAL_ADDR: Allocates the memory physically contiguous, and return
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* the bus address for that memory.
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* - ALIGN_BOTH_ENDS: after choosing the alignment, align the end offset to
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* @alignment as well.
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* - NEED_NON-STOLEN: don't allow any part of the memory allocation to lie
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* within stolen memory
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* - NEED_LIFETIME_FIXED: don't allow the buffer object to move throughout
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@ -397,14 +305,15 @@ static i830_memory *i830_allocate_memory_bo(ScrnInfoPtr scrn, const char *name,
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*/
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i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
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unsigned long size, unsigned long pitch,
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unsigned long alignment, int flags,
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enum tile_format tile_format)
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int flags, uint32_t tiling_mode)
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{
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i830_memory *mem;
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intel_screen_private *intel = intel_get_screen_private(scrn);
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uint32_t requested_tiling_mode = tiling_mode;
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int ret;
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/* Manage tile alignment and size constraints */
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if (tile_format != TILE_NONE) {
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if (tiling_mode != I915_TILING_NONE) {
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/* Only allocate page-sized increments. */
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size = ALIGN(size, GTT_PAGE_SIZE);
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@ -419,11 +328,54 @@ i830_memory *i830_allocate_memory(ScrnInfoPtr scrn, const char *name,
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/* round to size necessary for the fence register to work */
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size = i830_get_fence_size(intel, size);
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alignment = i830_get_fence_alignment(intel, size);
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}
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return i830_allocate_memory_bo(scrn, name, size,
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pitch, alignment, flags, tile_format);
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assert((flags & NEED_PHYSICAL_ADDR) == 0);
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/* Only allocate page-sized increments. */
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size = ALIGN(size, GTT_PAGE_SIZE);
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mem = xcalloc(1, sizeof(*mem));
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if (mem == NULL)
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return NULL;
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mem->name = xstrdup(name);
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if (mem->name == NULL) {
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xfree(mem);
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return NULL;
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}
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mem->bo = dri_bo_alloc(intel->bufmgr, name, size, GTT_PAGE_SIZE);
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if (!mem->bo) {
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xfree(mem->name);
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xfree(mem);
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return NULL;
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}
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/* Give buffer obviously wrong offset/end until it's pinned. */
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mem->offset = -1;
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mem->end = -1;
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mem->size = size;
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mem->pitch = pitch;
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ret = drm_intel_bo_set_tiling(mem->bo, &tiling_mode, pitch);
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if (ret != 0 || tiling_mode != requested_tiling_mode) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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"Failed to set tiling on %s: %s\n", mem->name,
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ret == 0 ? "rejected by kernel" : strerror(errno));
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}
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mem->tiling_mode = tiling_mode;
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if (flags & DISABLE_REUSE)
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drm_intel_bo_disable_reuse(mem->bo);
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/* Insert new allocation into the list */
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mem->prev = NULL;
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mem->next = intel->bo_list;
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if (intel->bo_list != NULL)
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intel->bo_list->prev = mem;
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intel->bo_list = mem;
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return mem;
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}
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@ -453,9 +405,9 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix)
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char phys_suffix[32] = "";
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char *tile_suffix = "";
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if (mem->tiling == TILE_XMAJOR)
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if (mem->tiling_mode == I915_TILING_X)
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tile_suffix = " X tiled";
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else if (mem->tiling == TILE_YMAJOR)
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else if (mem->tiling_mode == I915_TILING_Y)
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tile_suffix = " Y tiled";
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xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity,
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@ -472,9 +424,9 @@ i830_describe_allocations(ScrnInfoPtr scrn, int verbosity, const char *prefix)
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for (mem = intel->bo_list; mem != NULL; mem = mem->next) {
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char *tile_suffix = "";
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if (mem->tiling == TILE_XMAJOR)
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if (mem->tiling_mode == I915_TILING_X)
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tile_suffix = " X tiled";
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else if (mem->tiling == TILE_YMAJOR)
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else if (mem->tiling_mode == I915_TILING_Y)
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tile_suffix = " Y tiled";
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xf86DrvMsgVerb(scrn->scrnIndex, X_INFO, verbosity,
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@ -527,11 +479,10 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn)
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intel_screen_private *intel = intel_get_screen_private(scrn);
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unsigned int pitch = scrn->displayWidth * intel->cpp;
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unsigned long minspace;
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int align;
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long size, fb_height;
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int flags;
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i830_memory *front_buffer = NULL;
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enum tile_format tile_format = TILE_NONE;
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uint32_t tiling_mode;
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flags = ALLOW_SHARING | DISABLE_REUSE;
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@ -548,30 +499,21 @@ i830_memory *i830_allocate_framebuffer(ScrnInfoPtr scrn)
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size = ROUND_TO_PAGE(pitch * fb_height);
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if (intel->tiling)
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tile_format = TILE_XMAJOR;
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if (intel->tiling && IsTileable(scrn, pitch))
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tiling_mode = I915_TILING_X;
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else
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tiling_mode = I915_TILING_NONE;
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if (!IsTileable(scrn, pitch))
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tile_format = TILE_NONE;
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if (!i830_check_display_stride(scrn, pitch, tile_format != TILE_NONE)) {
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if (!i830_check_display_stride(scrn, pitch,
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tiling_mode != I915_TILING_NONE)) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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"Front buffer stride %d kB "
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"exceed display limit\n", pitch / 1024);
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return NULL;
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}
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/* Attempt to allocate it tiled first if we have page flipping on. */
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if (tile_format != TILE_NONE) {
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/* XXX: probably not the case on 965 */
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if (IS_I9XX(intel))
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align = MB(1);
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else
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align = KB(512);
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} else
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align = KB(64);
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front_buffer = i830_allocate_memory(scrn, "front buffer", size,
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pitch, align, flags, tile_format);
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pitch, flags, tiling_mode);
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if (front_buffer == NULL) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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@ -599,8 +541,7 @@ static Bool i830_allocate_cursor_buffers(ScrnInfoPtr scrn)
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intel->cursor_mem_argb[i] =
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i830_allocate_memory(scrn, "ARGB cursor",
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HWCURSOR_SIZE_ARGB, PITCH_NONE,
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GTT_PAGE_SIZE, DISABLE_REUSE,
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TILE_NONE);
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DISABLE_REUSE, I915_TILING_NONE);
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if (!intel->cursor_mem_argb[i])
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return FALSE;
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@ -667,7 +608,7 @@ Bool i830_allocate_xvmc_buffer(ScrnInfoPtr scrn, const char *name,
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int flags)
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{
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*buffer = i830_allocate_memory(scrn, name, size, PITCH_NONE,
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GTT_PAGE_SIZE, flags, TILE_NONE);
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flags, I915_TILING_NONE);
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if (!*buffer) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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@ -316,7 +316,7 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr scrn,
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I915XvMCContextPriv * ctxpriv)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int flags = ALIGN_BOTH_ENDS;
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int flags = 0;
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/* on 915G/GM, load indirect can only use physical address...sigh */
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if (IS_I915G(intel) || IS_I915GM(intel))
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@ -354,7 +354,7 @@ static Bool i915_allocate_xvmc_buffers(ScrnInfoPtr scrn,
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if (!i830_allocate_xvmc_buffer(scrn, "[XvMC]Correction Data Buffer",
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&(ctxpriv->mcCorrdata), 512 * 1024,
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ALIGN_BOTH_ENDS)) {
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0)) {
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return FALSE;
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}
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@ -595,7 +595,7 @@ static int i915_xvmc_create_surface(ScrnInfoPtr scrn, XvMCSurfacePtr pSurf,
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if (!i830_allocate_xvmc_buffer(scrn, "XvMC surface",
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&(sfpriv->surface), bufsize,
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ALIGN_BOTH_ENDS)) {
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0)) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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"[XvMC] i915 : Failed to allocate XvMC surface space!\n");
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xfree(sfpriv);
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@ -687,7 +687,7 @@ static int i915_xvmc_create_subpict(ScrnInfoPtr scrn, XvMCSubpicturePtr pSubp,
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if (!i830_allocate_xvmc_buffer(scrn, "XvMC surface",
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&(sfpriv->surface), bufsize,
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ALIGN_BOTH_ENDS)) {
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0)) {
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xf86DrvMsg(scrn->scrnIndex, X_ERROR,
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"[XvMC] I915XvMCCreateSurface: Failed to allocate XvMC surface space!\n");
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xfree(sfpriv);
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