render: set the surface state base address
It is the same as commit 73d4c7d7
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
This commit is contained in:
Xiang, Haihao
parent
b5ae596a07
commit
8d008ca89d
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@ -619,6 +619,8 @@ typedef struct brw_surface_state_padded {
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char pad[32 - sizeof(struct brw_surface_state)];
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} brw_surface_state_padded;
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#define PS_BINDING_TABLE_OFFSET (3 * sizeof(struct brw_surface_state_padded))
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struct gen4_cc_unit_state {
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/* Index by [src_blend][dst_blend] */
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brw_cc_unit_state_padded cc_state[BRW_BLENDFACTOR_COUNT]
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@ -629,7 +631,7 @@ typedef float gen4_vertex_buffer[VERTEX_BUFFER_SIZE];
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typedef struct gen4_composite_op {
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int op;
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drm_intel_bo *binding_table_bo;
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drm_intel_bo *surface_state_binding_table_bo;
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sampler_state_filter_t src_filter;
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sampler_state_filter_t mask_filter;
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sampler_state_extend_t src_extend;
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@ -1158,7 +1160,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
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int urb_sf_start, urb_sf_size;
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int urb_cs_start, urb_cs_size;
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uint32_t src_blend, dst_blend;
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dri_bo *binding_table_bo = composite_op->binding_table_bo;
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dri_bo *surface_state_binding_table_bo = composite_op->surface_state_binding_table_bo;
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intel->needs_render_state_emit = FALSE;
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@ -1216,7 +1218,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
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if (IS_GEN5(intel)) {
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | 6);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Instruction base address */
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/* general state max addr, disabled */
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@ -1228,7 +1230,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
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} else {
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | 4);
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_RELOC(surface_state_binding_table_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY); /* Surface state base address */
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OUT_BATCH(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
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/* general state max addr, disabled */
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OUT_BATCH(0x10000000 | BASE_ADDRESS_MODIFY);
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@ -1271,7 +1273,7 @@ static void i965_emit_composite_state(ScrnInfoPtr scrn)
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OUT_BATCH(0); /* clip */
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OUT_BATCH(0); /* sf */
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/* Only the PS uses the binding table */
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OUT_RELOC(binding_table_bo, I915_GEM_DOMAIN_SAMPLER, 0, 0);
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OUT_BATCH(PS_BINDING_TABLE_OFFSET);
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/* The drawing rectangle clipping is always on. Set it to values that
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* shouldn't do any clipping.
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@ -1474,7 +1476,7 @@ static Bool i965_composite_check_aperture(ScrnInfoPtr scrn)
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gen4_composite_op *composite_op = &render_state->composite_op;
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drm_intel_bo *bo_table[] = {
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intel->batch_bo,
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composite_op->binding_table_bo,
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composite_op->surface_state_binding_table_bo,
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render_state->vertex_buffer_bo,
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render_state->vs_state_bo,
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render_state->sf_state_bo,
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@ -1502,7 +1504,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
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struct gen4_render_state *render_state = intel->gen4_render_state;
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gen4_composite_op *composite_op = &render_state->composite_op;
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uint32_t *binding_table;
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drm_intel_bo *binding_table_bo, *surface_state_bo;
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drm_intel_bo *surface_state_binding_table_bo;
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composite_op->src_filter =
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sampler_state_filter_from_picture(source_picture->filter);
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@ -1562,65 +1564,36 @@ i965_prepare_composite(int op, PicturePtr source_picture,
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/* Set up the surface states. */
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surface_state_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
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3 * sizeof(brw_surface_state_padded),
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surface_state_binding_table_bo = dri_bo_alloc(intel->bufmgr, "surface_state",
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3 * (sizeof(struct brw_surface_state_padded) + sizeof(uint32_t)),
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4096);
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if (dri_bo_map(surface_state_bo, 1) != 0) {
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dri_bo_unreference(surface_state_bo);
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if (dri_bo_map(surface_state_binding_table_bo, 1) != 0) {
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dri_bo_unreference(surface_state_binding_table_bo);
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return FALSE;
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}
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/* Set up the state buffer for the destination surface */
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i965_set_picture_surface_state(intel, surface_state_bo, 0,
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i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 0,
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dest_picture, dest, TRUE);
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/* Set up the source surface state buffer */
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i965_set_picture_surface_state(intel, surface_state_bo, 1,
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i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 1,
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source_picture, source, FALSE);
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if (mask) {
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/* Set up the mask surface state buffer */
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i965_set_picture_surface_state(intel, surface_state_bo, 2,
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i965_set_picture_surface_state(intel, surface_state_binding_table_bo, 2,
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mask_picture, mask, FALSE);
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}
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dri_bo_unmap(surface_state_bo);
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/* Set up the binding table of surface indices to surface state. */
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binding_table_bo = dri_bo_alloc(intel->bufmgr, "binding_table",
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3 * sizeof(uint32_t), 4096);
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if (dri_bo_map(binding_table_bo, 1) != 0) {
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dri_bo_unreference(binding_table_bo);
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dri_bo_unreference(surface_state_bo);
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return FALSE;
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}
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binding_table = binding_table_bo->virtual;
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binding_table[0] = intel_emit_reloc(binding_table_bo,
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0 * sizeof(uint32_t),
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surface_state_bo,
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0 *
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sizeof(brw_surface_state_padded),
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I915_GEM_DOMAIN_INSTRUCTION, 0);
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binding_table[1] = intel_emit_reloc(binding_table_bo,
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1 * sizeof(uint32_t),
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surface_state_bo,
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1 *
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sizeof(brw_surface_state_padded),
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I915_GEM_DOMAIN_INSTRUCTION, 0);
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binding_table = (uint32_t *)((char *)surface_state_binding_table_bo->virtual + PS_BINDING_TABLE_OFFSET);
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binding_table[0] = 0;
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binding_table[1] = sizeof(struct brw_surface_state_padded);
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if (mask) {
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binding_table[2] = intel_emit_reloc(binding_table_bo,
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2 * sizeof(uint32_t),
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surface_state_bo,
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2 *
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sizeof
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(brw_surface_state_padded),
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I915_GEM_DOMAIN_INSTRUCTION,
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0);
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binding_table[2] = 2 * sizeof(struct brw_surface_state_padded);
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} else {
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binding_table[2] = 0;
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}
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dri_bo_unmap(binding_table_bo);
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/* All refs to surface_state are now contained in binding_table_bo. */
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drm_intel_bo_unreference(surface_state_bo);
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dri_bo_unmap(surface_state_binding_table_bo);
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composite_op->op = op;
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intel->render_source_picture = source_picture;
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@ -1629,8 +1602,8 @@ i965_prepare_composite(int op, PicturePtr source_picture,
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intel->render_source = source;
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intel->render_mask = mask;
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intel->render_dest = dest;
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drm_intel_bo_unreference(composite_op->binding_table_bo);
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composite_op->binding_table_bo = binding_table_bo;
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drm_intel_bo_unreference(composite_op->surface_state_binding_table_bo);
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composite_op->surface_state_binding_table_bo = surface_state_binding_table_bo;
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intel->scale_units[0][0] = source->drawable.width;
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intel->scale_units[0][1] = source->drawable.height;
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@ -2038,7 +2011,7 @@ void gen4_render_state_cleanup(ScrnInfoPtr scrn)
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int i, j, k, l, m;
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gen4_composite_op *composite_op = &render_state->composite_op;
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drm_intel_bo_unreference(composite_op->binding_table_bo);
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drm_intel_bo_unreference(composite_op->surface_state_binding_table_bo);
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drm_intel_bo_unreference(render_state->vertex_buffer_bo);
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drm_intel_bo_unreference(render_state->vs_state_bo);
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