From 95f4da647a4055545b09cae0834df0fa2127a458 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Wed, 30 Nov 2011 11:59:31 +0000 Subject: [PATCH] sna: Align pwrite to transfer whole cachelines Daniel claims that this is will be faster, or will be once he has completed rewriting pwrite! Signed-off-by: Chris Wilson --- src/sna/kgem.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/src/sna/kgem.c b/src/sna/kgem.c index 58b9b67d..959f97ca 100644 --- a/src/sna/kgem.c +++ b/src/sna/kgem.c @@ -164,9 +164,16 @@ static int gem_write(int fd, uint32_t handle, VG_CLEAR(pwrite); pwrite.handle = handle; - pwrite.offset = offset; - pwrite.size = length; - pwrite.data_ptr = (uintptr_t)src; + /* align the transfer to cachelines; fortuitously this is safe! */ + if ((offset | length) & 63) { + pwrite.offset = offset & ~63; + pwrite.size = ALIGN(offset+length, 64) - pwrite.offset; + pwrite.data_ptr = (uintptr_t)src + pwrite.offset - offset; + } else { + pwrite.offset = offset; + pwrite.size = length; + pwrite.data_ptr = (uintptr_t)src; + } return drmIoctl(fd, DRM_IOCTL_I915_GEM_PWRITE, &pwrite); }