From 97fc1d4c5bd268f331aaa9f7144e4fe40837fbb0 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Fri, 12 Apr 2013 10:23:43 +0100 Subject: [PATCH] sna/gen5: Force a MI_FLUSH between using the BLT and RENDER engines There is a workaround that says the first RENDER command following use of the BLT should be a non-pipelined command. To be safe, emit a MI_FLUSH before setting up the invariants. Bugzilla: https://bugs.launchpad.net/ubuntu/+source/xserver-xorg-video-intel/+bug/1168066 Signed-off-by: Chris Wilson --- src/sna/gen5_render.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c index 7038444d..b960ed69 100644 --- a/src/sna/gen5_render.c +++ b/src/sna/gen5_render.c @@ -756,8 +756,13 @@ gen5_emit_invariant(struct sna *sna) * * However, the kernel flushes the pipeline between batches, * so we should be safe.... - * OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + * + * On the other hand, after using BLT we must use a non-pipelined + * operation... */ + if (sna->kgem.nreloc) + OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH); + OUT_BATCH(GEN5_PIPELINE_SELECT | PIPELINE_SELECT_3D); gen5_emit_state_base_address(sna);