Remove flush parameter from intel_batch_flush()

There is only a single caller that wishes to forcibly append a flush
into the batch: intel_sync(). So move the logic there.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>

src/i830_accel.c

@@ -51,20 +51,6 @@ unsigned long intel_get_pixmap_pitch(PixmapPtr pixmap)
 	return (unsigned long)pixmap->devKind;
 }
 
-void intel_sync(ScrnInfoPtr scrn)
-{
-	intel_screen_private *intel = intel_get_screen_private(scrn);
-
-	if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
-		ErrorF("I830Sync\n");
-
-	if (!scrn->vtSema || !intel->batch_bo || !intel->batch_ptr)
-		return;
-
-	intel_batch_flush(scrn, TRUE);
-	intel_batch_wait_last(scrn);
-}
-
 void i830_debug_flush(ScrnInfoPtr scrn)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
@@ -73,7 +59,7 @@ void i830_debug_flush(ScrnInfoPtr scrn)
 		intel_batch_pipelined_flush(scrn);
 
 	if (intel->debug_flush & DEBUG_FLUSH_BATCHES)
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 }
 
 /* The following function sets up the supported acceleration. Call it

src/i830_batchbuffer.c

@@ -124,24 +124,13 @@ void intel_batch_pipelined_flush(ScrnInfoPtr scrn)
 	}
 }
 
-void intel_batch_flush(ScrnInfoPtr scrn, Bool flush)
+void intel_batch_flush(ScrnInfoPtr scrn)
 {
 	intel_screen_private *intel = intel_get_screen_private(scrn);
 	int ret;
 
 	assert (!intel->in_batch_atomic);
 
-	if (flush) {
-		int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
-
-		if (IS_I965G(intel))
-			flags = 0;
-
-		*(uint32_t *) (intel->batch_ptr + intel->batch_used) =
-			MI_FLUSH | flags;
-		intel->batch_used += 4;
-	}
-
 	if (intel->batch_used == 0)
 		return;
 
@@ -228,3 +217,26 @@ void intel_batch_wait_last(ScrnInfoPtr scrn)
 	drm_intel_bo_map(intel->last_batch_bo, TRUE);
 	drm_intel_bo_unmap(intel->last_batch_bo);
 }
+
+void intel_sync(ScrnInfoPtr scrn)
+{
+	intel_screen_private *intel = intel_get_screen_private(scrn);
+	int flags;
+
+	if (I810_DEBUG & (DEBUG_VERBOSE_ACCEL | DEBUG_VERBOSE_SYNC))
+		ErrorF("I830Sync\n");
+
+	if (!scrn->vtSema || !intel->batch_bo || !intel->batch_ptr)
+		return;
+
+	flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
+	if (IS_I965G(intel))
+		flags = 0;
+
+	BEGIN_BATCH(1);
+	OUT_BATCH(flags);
+	ADVANCE_BATCH();
+
+	intel_batch_flush(scrn);
+	intel_batch_wait_last(scrn);
+}

src/i830_batchbuffer.h

@@ -36,7 +36,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 void intel_batch_init(ScrnInfoPtr scrn);
 void intel_batch_teardown(ScrnInfoPtr scrn);
 void intel_batch_pipelined_flush(ScrnInfoPtr scrn);
-void intel_batch_flush(ScrnInfoPtr scrn, Bool flush);
+void intel_batch_flush(ScrnInfoPtr scrn);
 void intel_batch_wait_last(ScrnInfoPtr scrn);
 
 static inline int intel_batch_space(intel_screen_private *intel)
@@ -49,7 +49,7 @@ intel_batch_require_space(ScrnInfoPtr scrn, intel_screen_private *intel, GLuint
 {
 	assert(sz < intel->batch_bo->size - 8);
 	if (intel_batch_space(intel) < sz)
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 }
 
 static inline void intel_batch_start_atomic(ScrnInfoPtr scrn, unsigned int sz)
@@ -193,7 +193,7 @@ do {									\
 	if ((intel->batch_emitting > 8) &&				\
 	    (I810_DEBUG & DEBUG_ALWAYS_SYNC)) {				\
 		/* Note: not actually syncing, just flushing each batch. */ \
-		intel_batch_flush(scrn, FALSE);			\
+		intel_batch_flush(scrn);			\
 	}								\
 	intel->batch_emitting = 0;					\
 } while (0)

src/i830_dri.c

@@ -352,7 +352,7 @@ I830DRI2CopyRegion(DrawablePtr drawable, RegionPtr pRegion,
 	 * We can't rely on getting into the block handler before the DRI
 	 * client gets to run again so flush now. */
 	intel->need_mi_flush = FALSE;
-	intel_batch_flush(scrn, TRUE);
+	intel_batch_flush(scrn);
 #if ALWAYS_SYNC
 	intel_sync(scrn);
 #endif

src/i830_driver.c

@@ -997,7 +997,8 @@ I830BlockHandler(int i, pointer blockData, pointer pTimeout, pointer pReadmask)
 		/* Flush the batch, so that any rendering is executed in a timely
 		 * fashion.
 		 */
-		intel_batch_flush(scrn, flush);
+		if (flush)
+			intel_batch_pipelined_flush(scrn);
 		drmCommandNone(intel->drmSubFD, DRM_I915_GEM_THROTTLE);
 
 		intel->need_mi_flush = FALSE;

src/i830_uxa.c

@@ -93,7 +93,7 @@ i830_get_aperture_space(ScrnInfoPtr scrn, drm_intel_bo ** bo_table,
 
 	bo_table[0] = intel->batch_bo;
 	if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) != 0) {
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 		bo_table[0] = intel->batch_bo;
 		if (drm_intel_bufmgr_check_aperture_space(bo_table, num_bos) !=
 		    0) {
@@ -573,7 +573,7 @@ static Bool i830_uxa_prepare_access(PixmapPtr pixmap, uxa_access_t access)
 
 	if (!list_is_empty(&priv->batch) &&
 	    (access == UXA_ACCESS_RW || priv->batch_write_domain))
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 
 	/* No VT sema or GEM?  No GTT mapping. */
 	if (!scrn->vtSema || bo->size > intel->max_gtt_map_size) {

src/i965_render.c

@@ -1627,7 +1627,7 @@ i965_prepare_composite(int op, PicturePtr source_picture,
 	}
 
 	if (!i965_composite_check_aperture(scrn)) {
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 		if (!i965_composite_check_aperture(scrn)) {
 			intel_debug_fallback(scrn,
 					     "Couldn't fit render operation "
@@ -1805,7 +1805,7 @@ i965_composite(PixmapPtr dest, int srcX, int srcY, int maskX, int maskY,
 	drm_intel_bo_subdata(vb_bo, render_state->vb_offset * 4, i * 4, vb);
 
 	if (!i965_composite_check_aperture(scrn))
-		intel_batch_flush(scrn, FALSE);
+		intel_batch_flush(scrn);
 
 	intel_batch_start_atomic(scrn, 200);
 	if (intel->needs_render_state_emit)

src/i965_video.c

@@ -1213,7 +1213,7 @@ I965DisplayVideoTextured(ScrnInfoPtr scrn,
 		if (drm_intel_bufmgr_check_aperture_space(bo_table,
 							  ARRAY_SIZE(bo_table))
 		    < 0) {
-			intel_batch_flush(scrn, FALSE);
+			intel_batch_flush(scrn);
 		}
 
 		intel_batch_start_atomic(scrn, 100);