Aurelien
/
xf86-video-intel
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'crestline' of git+ssh://zhen@otc-graphics.jf.intel.com/git/xorg/driver/xf86-video-intel into crestline

This commit is contained in:
Wang Zhenyu 2006-12-29 10:10:26 +08:00
parent 84915ac8af fabfccd3d8
commit a1796bfb51
27 changed files with 3221 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

11
src/Makefile.am
View File

@ -91,13 +91,22 @@ i810_drv_la_SOURCES = \
i830_exa.c \
i830_xaa.c \
i830_exa_render.c \
i915_exa_render.c
i915_exa_render.c \
i965_exa_render.c
if HAVE_GEN4ASM
sf_prog.h: packed_yuv_sf.g4a
intel-gen4asm -o sf_prog.h packed_yuv_sf.g4a
wm_prog.h: packed_yuv_wm.g4a
intel-gen4asm -o wm_prog.h packed_yuv_wm.g4a
exa_sf_prog.h: exa_sf.g4a
intel-gen4asm -o exa_sf_prog.h exa_sf.g4a
exa_sf_mask_prog.h: exa_sf_mask.g4a
intel-gen4asm -o exa_sf_mask_prog.h exa_sf_mask.g4a
exa_wm_nomask_prog.h: exa_wm_nomask.g4a
intel-gen4asm -o exa_wm_nomask_prog.h exa_wm_nomask.g4a
exa_wm_masknoca_prog.h: exa_wm_masknoca.g4a
intel-gen4asm -o exa_wm_masknoca_prog.h exa_wm_masknoca.g4a
endif
if DRI

10
src/common.h
View File

@ -302,6 +302,11 @@ extern int I810_DEBUG;
#define PCI_CHIP_I946_GZ_BRIDGE 0x2970
#endif
#ifndef PCI_CHIP_CRESTLINE //XXX: fix with official name
#define PCI_CHIP_CRESTLINE 0x2A02
#define PCI_CHIP_CRESTLINE_BRIDGE 0x2A00
#endif
#define IS_I810(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I810 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_DC100 || \
pI810->PciInfo->chipType == PCI_CHIP_I810_E)
@ -317,10 +322,11 @@ extern int I810_DEBUG;
#define IS_I915GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I915_GM)
#define IS_I945G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_G)
#define IS_I945GM(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I945_GM)
#define IS_I965G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_G || pI810->PciInfo->chipType == PCI_CHIP_I965_G_1 || pI810->PciInfo->chipType == PCI_CHIP_I965_Q || pI810->PciInfo->chipType == PCI_CHIP_I946_GZ)
#define IS_I965G(pI810) (pI810->PciInfo->chipType == PCI_CHIP_I965_G || pI810->PciInfo->chipType == PCI_CHIP_I965_G_1 || pI810->PciInfo->chipType == PCI_CHIP_I965_Q || pI810->PciInfo->chipType == PCI_CHIP_I946_GZ || pI810->PciInfo->chipType == PCI_CHIP_CRESTLINE)
#define IS_I9XX(pI810) (IS_I915G(pI810) || IS_I915GM(pI810) || IS_I945G(pI810) || IS_I945GM(pI810) || IS_I965G(pI810))
#define IS_CRESTLINE(pI810) (pI810->PciInfo->chipType == PCI_CHIP_CRESTLINE) // XXX: IS_965GM ?
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810))
#define IS_MOBILE(pI810) (IS_I830(pI810) || IS_I85X(pI810) || IS_I915GM(pI810) || IS_I945GM(pI810) || IS_CRESTLINE(pI810))
#define GTT_PAGE_SIZE KB(4)
#define ROUND_TO(x, y) (((x) + (y) - 1) / (y) * (y))

17
src/exa_sf.g4a Normal file
View File

@ -0,0 +1,17 @@
send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
mov (8) m1<1>F g7<0,1,0>F { align1 };
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
mov (8) m3<1>F g3<8,8,1>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

53
src/exa_sf_mask.g4a Normal file
View File

@ -0,0 +1,53 @@
/* FIXME how to setup second coeffient for mask tex coord */
/*
g3 (v0) { u0, v0, 1.0, 1.0 } ==> {u0, v0, 1.0, 1.0, mu0, mv0, 1.0, 1.0} Co[0](u0) Co[1](v0) Co[2](mu0) Co[3](mv0)
g4 (v1) { u1, v1, 1.0, 1.0 } ==> {u1, v1, 1.0, 1.0, mu1, mv1, 1.0, 1.0}
g5 (v2) { u2, v2 } ==> (u2, v2, mu2, mv2}
g6 { 1/(x1-x0), 1/(y1-y0) }
g7 { u1-u0, v1-v0, 0, 0} ==>{u1-u0, v1-v0,0, 0, mu1-mu0, mv1-mv0, 0, 0}
-> { (u1-u0)/(x1-x0), (v1-v0)/(y1-y0) } ==>{(u1-u0)/(x1-x0), (v1-v0)/(y1-y0),(mu1-mu0)/(x1-x0), (mv1-mv0)/(y1-y0)
Cx, Cy Cx[0], Cy[0], Cx[1], Cy[1]
*/
/* assign Cx[0], Cx[1] to src, same to Cy, Co
Cx[2], Cx[3] to mask, same to Cy, Co */
send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
/* Cx[0] */
mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
/* Cy[0] */
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
/* Cx[2] */
mul (1) g7.16<1>F g7.16<0,1,0>F g6<0,1,0>F { align1 };
/* Cy[2] */
mul (1) g7.20<1>F g7.20<0,1,0>F g6.4<0,1,0>F { align1 };
/* src Cx[0], Cx[1] */
mov (8) m1<1>F g7<0,1,0>F { align1 };
/* mask Cx[2], Cx[3] */
mov (1) m1.8<1>F g7.16<0,1,0>F { align1 };
mov (1) m1.12<1>F g7.16<0,1,0>F { align1 };
/* src Cy[0], Cy[1] */
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
/* mask Cy[2], Cy[3] */
mov (1) m2.8<1>F g7.20<0,1,0>F { align1 };
mov (1) m2.12<1>F g7.20<0,1,0>F { align1 };
/* src Co[0], Co[1] */
mov (8) m3<1>F g3<8,8,1>F { align1 };
/* mask Co[2], Co[3] */
mov (1) m3.8<1>F g3.16<0,1,0>F { align1 };
mov (1) m3.12<1>F g3.20<0,1,0>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

25
src/exa_sf_mask_prog.h Normal file
View File

@ -0,0 +1,25 @@
{ 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
{ 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00000041, 0x20f077bd, 0x000000f0, 0x000000c0 },
{ 0x00000041, 0x20f477bd, 0x000000f4, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00000001, 0x202803be, 0x000000f0, 0x00000000 },
{ 0x00000001, 0x202c03be, 0x000000f0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00000001, 0x204803be, 0x000000f4, 0x00000000 },
{ 0x00000001, 0x204c03be, 0x000000f4, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00000001, 0x206803be, 0x00000070, 0x00000000 },
{ 0x00000001, 0x206c03be, 0x00000074, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

17
src/exa_sf_prog.h Normal file
View File

@ -0,0 +1,17 @@
{ 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
{ 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

202
src/exa_wm_masknoca.g4a Normal file
View File

@ -0,0 +1,202 @@
/*
* This's for exa composite operation in no mask picture case.
* The simplest case is just sending what src picture has to dst picture.
* XXX: This is still experimental, and should be fixed to support multiple texture
* map, and conditional mul actions.
*/
/* I think this should be same as in g4a program for texture video,
as we also use 16-pixel dispatch. and SF scale in g3 is useful for us. */
/* The initial payload of the thread is always g0.
* WM_URB (incoming URB entries) is g3
As mask texture coeffient needs extra setup urb starting from g4, we should
shift this location.
* X0_R is g4->g6
* X1_R is g5->g7
* Y0_R is g6->g8
* Y1_R is g7->g9
* X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
* Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
* X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
* Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
*/
/* multitexture program with src and mask texture */
/* - load src texture */
/* - load mask texture */
/* - mul src.X with mask's alpha */
/* - write out src.X */
/* Set up ss0.x coordinates*/
mov (1) g6<1>F g1.8<0,1,0>UW { align1 };
add (1) g6.4<1>F g1.8<0,1,0>UW 1UB { align1 };
mov (1) g6.8<1>F g1.8<0,1,0>UW { align1 };
add (1) g6.12<1>F g1.8<0,1,0>UW 1UB { align1 };
/* Set up ss0.y coordinates */
mov (1) g8<1>F g1.10<0,1,0>UW { align1 };
mov (1) g8.4<1>F g1.10<0,1,0>UW { align1 };
add (1) g8.8<1>F g1.10<0,1,0>UW 1UB { align1 };
add (1) g8.12<1>F g1.10<0,1,0>UW 1UB { align1 };
/* set up ss1.x coordinates */
mov (1) g6.16<1>F g1.12<0,1,0>UW { align1 };
add (1) g6.20<1>F g1.12<0,1,0>UW 1UB { align1 };
mov (1) g6.24<1>F g1.12<0,1,0>UW { align1 };
add (1) g6.28<1>F g1.12<0,1,0>UW 1UB { align1 };
/* set up ss1.y coordinates */
mov (1) g8.16<1>F g1.14<0,1,0>UW { align1 };
mov (1) g8.20<1>F g1.14<0,1,0>UW { align1 };
add (1) g8.24<1>F g1.14<0,1,0>UW 1UB { align1 };
add (1) g8.28<1>F g1.14<0,1,0>UW 1UB { align1 };
/* Set up ss2.x coordinates */
mov (1) g7<1>F g1.16<0,1,0>UW { align1 };
add (1) g7.4<1>F g1.16<0,1,0>UW 1UB { align1 };
mov (1) g7.8<1>F g1.16<0,1,0>UW { align1 };
add (1) g7.12<1>F g1.16<0,1,0>UW 1UB { align1 };
/* Set up ss2.y coordinates */
mov (1) g9<1>F g1.18<0,1,0>UW { align1 };
mov (1) g9.4<1>F g1.18<0,1,0>UW { align1 };
add (1) g9.8<1>F g1.18<0,1,0>UW 1UB { align1 };
add (1) g9.12<1>F g1.18<0,1,0>UW 1UB { align1 };
/* Set up ss3.x coordinates */
mov (1) g7.16<1>F g1.20<0,1,0>UW { align1 };
add (1) g7.20<1>F g1.20<0,1,0>UW 1UB { align1 };
mov (1) g7.24<1>F g1.20<0,1,0>UW { align1 };
add (1) g7.28<1>F g1.20<0,1,0>UW 1UB { align1 };
/* Set up ss3.y coordinates */
mov (1) g9.16<1>F g1.22<0,1,0>UW { align1 };
mov (1) g9.20<1>F g1.22<0,1,0>UW { align1 };
add (1) g9.24<1>F g1.22<0,1,0>UW 1UB { align1 };
add (1) g9.28<1>F g1.22<0,1,0>UW 1UB { align1 };
/* Now, map these screen space coordinates into texture coordinates. */
/* This is for src texture */
/* I don't want to change origin ssX coords, as it will be used later in mask */
/* so store tex coords in g10, g11, g12, g13 */
/* subtract screen-space X origin of vertex 0. */
add (8) g10<1>F g6<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g11<1>F g7<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
/* Cx[0] */
mul (8) g10<1>F g10<8,8,1>F g3<0,1,0>F { align1 };
mul (8) g11<1>F g11<8,8,1>F g3<0,1,0>F { align1 };
/* add in texture X offset */
/* Co[0] */
add (8) g10<1>F g10<8,8,1>F g3.12<0,1,0>F { align1 };
add (8) g11<1>F g11<8,8,1>F g3.12<0,1,0>F { align1 };
/* subtract screen-space Y origin of vertex 0. */
add (8) g12<1>F g8<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g13<1>F g9<8,8,1>F -g1.4<0,1,0>F { align1 };
/* scale by texture Y increment */
/* Cy[0] */
mul (8) g12<1>F g12<8,8,1>F g3.4<0,1,0>F { align1 };
mul (8) g13<1>F g13<8,8,1>F g3.4<0,1,0>F { align1 };
/* add in texture Y offset */
/* Co[1] */
add (8) g12<1>F g12<8,8,1>F g3.28<0,1,0>F { align1 };
add (8) g13<1>F g13<8,8,1>F g3.28<0,1,0>F { align1 };
/* prepare sampler read back gX register, which would be written back to output */
/* use simd16 sampler, param 0 is u, param 1 is v. */
/* 'payload' loading, assuming tex coord start from g4 */
mov (8) m1<1>F g10<8,8,1>F { align1 };
mov (8) m2<1>F g11<8,8,1>F { align1 }; /* param 0 u in m1, m2 */
mov (8) m3<1>F g12<8,8,1>F { align1 };
mov (8) m4<1>F g13<8,8,1>F { align1 }; /* param 1 v in m3, m4 */
/* m0 will be copied with g0, as it contains send desc */
/* emit sampler 'send' cmd */
/* src texture readback: g14-g21 */
send (16) 0 /* msg reg index */
g14<1>UW /* readback */
g0<8,8,1>UW /* copy to msg start reg*/
sampler (1,0,F) /* sampler message description,
(binding_table,sampler_index,datatype).
here(src->dst) we should use src_sampler and
src_surface */
mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
mov (8) g21<1>UD g21<8,8,1>UD { align1 }; /* wait sampler return */
/* sampler mask texture, use g10, g11, g12, g13 */
/* subtract screen-space X origin of vertex 0. */
add (8) g10<1>F g6<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g11<1>F g7<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
/* Cx[2] */
mul (8) g10<1>F g10<8,8,1>F g4<0,1,0>F { align1 };
mul (8) g11<1>F g11<8,8,1>F g4<0,1,0>F { align1 };
/* add in texture X offset */
/* Co[2] */
add (8) g10<1>F g10<8,8,1>F g4.12<0,1,0>F { align1 };
add (8) g11<1>F g11<8,8,1>F g4.12<0,1,0>F { align1 };
/* subtract screen-space Y origin of vertex 0. */
add (8) g12<1>F g8<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g13<1>F g9<8,8,1>F -g1.4<0,1,0>F { align1 };
/* scale by texture Y increment */
/* Cy[2] */
mul (8) g12<1>F g12<8,8,1>F g4.4<0,1,0>F { align1 };
mul (8) g13<1>F g13<8,8,1>F g4.4<0,1,0>F { align1 };
/* add in texture Y offset */
/* Co[3] */
add (8) g12<1>F g12<8,8,1>F g4.28<0,1,0>F { align1 };
add (8) g13<1>F g13<8,8,1>F g4.28<0,1,0>F { align1 };
mov (8) m1<1>F g10<8,8,1>F { align1 };
mov (8) m2<1>F g11<8,8,1>F { align1 };
mov (8) m3<1>F g12<8,8,1>F { align1 };
mov (8) m4<1>F g13<8,8,1>F { align1 };
/* mask sampler g22-g29 */
/* binding_table (2), sampler (1) */
send (16) 0 g22<1>UW g0<8,8,1>UW sampler (2,1,F) mlen 5 rlen 8 { align1 };
mov (8) g29<1>UD g29<8,8,1>UD { align1 }; /* wait sampler return */
/* mul mask's alpha channel g28,g29 to src (g14-g21), then write out src */
mul (8) g14<1>F g14<8,8,1>F g28<8,8,1>F { align1 };
mul (8) g15<1>F g15<8,8,1>F g29<8,8,1>F { align1 };
mul (8) g16<1>F g16<8,8,1>F g28<8,8,1>F { align1 };
mul (8) g17<1>F g17<8,8,1>F g29<8,8,1>F { align1 };
mul (8) g18<1>F g18<8,8,1>F g28<8,8,1>F { align1 };
mul (8) g19<1>F g19<8,8,1>F g29<8,8,1>F { align1 };
mul (8) g20<1>F g20<8,8,1>F g28<8,8,1>F { align1 };
mul (8) g21<1>F g21<8,8,1>F g29<8,8,1>F { align1 };
/* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */
mov (8) m2<1>F g14<8,8,1>F { align1 };
mov (8) m3<1>F g16<8,8,1>F { align1 };
mov (8) m4<1>F g18<8,8,1>F { align1 };
mov (8) m5<1>F g20<8,8,1>F { align1 };
mov (8) m6<1>F g15<8,8,1>F { align1 };
mov (8) m7<1>F g17<8,8,1>F { align1 };
mov (8) m8<1>F g19<8,8,1>F { align1 };
mov (8) m9<1>F g21<8,8,1>F { align1 };
/* m0, m1 are all direct passed by PS thread payload */
mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
/* write */
send (16) 0 acc0<1>UW g0<8,8,1>UW write (
0, /* binding_table */
8, /* pixel scordboard clear, msg type simd16 single source */
4, /* render target write */
0 /* no write commit message */
)
mlen 10
rlen 0
{ align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

95
src/exa_wm_masknoca_prog.h Normal file
View File

@ -0,0 +1,95 @@
{ 0x00000001, 0x20c0013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20c40d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x20c8013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20cc0d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x2100013d, 0x0000002a, 0x00000000 },
{ 0x00000001, 0x2104013d, 0x0000002a, 0x00000000 },
{ 0x00000040, 0x21080d3d, 0x0000002a, 0x00000001 },
{ 0x00000040, 0x210c0d3d, 0x0000002a, 0x00000001 },
{ 0x00000001, 0x20d0013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20d40d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x20d8013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20dc0d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x2110013d, 0x0000002e, 0x00000000 },
{ 0x00000001, 0x2114013d, 0x0000002e, 0x00000000 },
{ 0x00000040, 0x21180d3d, 0x0000002e, 0x00000001 },
{ 0x00000040, 0x211c0d3d, 0x0000002e, 0x00000001 },
{ 0x00000001, 0x20e0013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20e40d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20e8013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20ec0d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x2120013d, 0x00000032, 0x00000000 },
{ 0x00000001, 0x2124013d, 0x00000032, 0x00000000 },
{ 0x00000040, 0x21280d3d, 0x00000032, 0x00000001 },
{ 0x00000040, 0x212c0d3d, 0x00000032, 0x00000001 },
{ 0x00000001, 0x20f0013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20f40d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20f8013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20fc0d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x2130013d, 0x00000036, 0x00000000 },
{ 0x00000001, 0x2134013d, 0x00000036, 0x00000000 },
{ 0x00000040, 0x21380d3d, 0x00000036, 0x00000001 },
{ 0x00000040, 0x213c0d3d, 0x00000036, 0x00000001 },
{ 0x00600040, 0x214077bd, 0x008d00c0, 0x00004020 },
{ 0x00600040, 0x216077bd, 0x008d00e0, 0x00004020 },
{ 0x00600041, 0x214077bd, 0x008d0140, 0x00000060 },
{ 0x00600041, 0x216077bd, 0x008d0160, 0x00000060 },
{ 0x00600040, 0x214077bd, 0x008d0140, 0x0000006c },
{ 0x00600040, 0x216077bd, 0x008d0160, 0x0000006c },
{ 0x00600040, 0x218077bd, 0x008d0100, 0x00004024 },
{ 0x00600040, 0x21a077bd, 0x008d0120, 0x00004024 },
{ 0x00600041, 0x218077bd, 0x008d0180, 0x00000064 },
{ 0x00600041, 0x21a077bd, 0x008d01a0, 0x00000064 },
{ 0x00600040, 0x218077bd, 0x008d0180, 0x0000007c },
{ 0x00600040, 0x21a077bd, 0x008d01a0, 0x0000007c },
{ 0x00600001, 0x202003be, 0x008d0140, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d0160, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0180, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d01a0, 0x00000000 },
{ 0x00800031, 0x21c01d29, 0x008d0000, 0x02580001 },
{ 0x00600001, 0x22a00021, 0x008d02a0, 0x00000000 },
{ 0x00600040, 0x214077bd, 0x008d00c0, 0x00004020 },
{ 0x00600040, 0x216077bd, 0x008d00e0, 0x00004020 },
{ 0x00600041, 0x214077bd, 0x008d0140, 0x00000080 },
{ 0x00600041, 0x216077bd, 0x008d0160, 0x00000080 },
{ 0x00600040, 0x214077bd, 0x008d0140, 0x0000008c },
{ 0x00600040, 0x216077bd, 0x008d0160, 0x0000008c },
{ 0x00600040, 0x218077bd, 0x008d0100, 0x00004024 },
{ 0x00600040, 0x21a077bd, 0x008d0120, 0x00004024 },
{ 0x00600041, 0x218077bd, 0x008d0180, 0x00000084 },
{ 0x00600041, 0x21a077bd, 0x008d01a0, 0x00000084 },
{ 0x00600040, 0x218077bd, 0x008d0180, 0x0000009c },
{ 0x00600040, 0x21a077bd, 0x008d01a0, 0x0000009c },
{ 0x00600001, 0x202003be, 0x008d0140, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d0160, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0180, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d01a0, 0x00000000 },
{ 0x00800031, 0x22c01d29, 0x008d0000, 0x02580102 },
{ 0x00600001, 0x23a00021, 0x008d03a0, 0x00000000 },
{ 0x00600041, 0x21c077bd, 0x008d01c0, 0x008d0380 },
{ 0x00600041, 0x21e077bd, 0x008d01e0, 0x008d03a0 },
{ 0x00600041, 0x220077bd, 0x008d0200, 0x008d0380 },
{ 0x00600041, 0x222077bd, 0x008d0220, 0x008d03a0 },
{ 0x00600041, 0x224077bd, 0x008d0240, 0x008d0380 },
{ 0x00600041, 0x226077bd, 0x008d0260, 0x008d03a0 },
{ 0x00600041, 0x228077bd, 0x008d0280, 0x008d0380 },
{ 0x00600041, 0x22a077bd, 0x008d02a0, 0x008d03a0 },
{ 0x00600001, 0x204003be, 0x008d01c0, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0200, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x20a003be, 0x008d0280, 0x00000000 },
{ 0x00600001, 0x20c003be, 0x008d01e0, 0x00000000 },
{ 0x00600001, 0x20e003be, 0x008d0220, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d02a0, 0x00000000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

143
src/exa_wm_nomask.g4a Normal file
View File

@ -0,0 +1,143 @@
/*
* This's for exa composite operation in no mask picture case.
* The simplest case is just sending what src picture has to dst picture.
*/
/* I think this should be same as in g4a program for texture video,
as we also use 16-pixel dispatch. and SF scale in g3 is useful for us. */
/* The initial payload of the thread is always g0.
* WM_URB (incoming URB entries) is g3
* X0_R is g4
* X1_R is g5
* Y0_R is g6
* Y1_R is g7
*/
/* Set up ss0.x coordinates*/
mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.4<1>F g1.8<0,1,0>UW 1UB { align1 };
mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.12<1>F g1.8<0,1,0>UW 1UB { align1 };
/* Set up ss0.y coordinates */
mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
add (1) g6.8<1>F g1.10<0,1,0>UW 1UB { align1 };
add (1) g6.12<1>F g1.10<0,1,0>UW 1UB { align1 };
/* set up ss1.x coordinates */
mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.20<1>F g1.12<0,1,0>UW 1UB { align1 };
mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.28<1>F g1.12<0,1,0>UW 1UB { align1 };
/* set up ss1.y coordinates */
mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
add (1) g6.24<1>F g1.14<0,1,0>UW 1UB { align1 };
add (1) g6.28<1>F g1.14<0,1,0>UW 1UB { align1 };
/* Set up ss2.x coordinates */
mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.4<1>F g1.16<0,1,0>UW 1UB { align1 };
mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.12<1>F g1.16<0,1,0>UW 1UB { align1 };
/* Set up ss2.y coordinates */
mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
add (1) g7.8<1>F g1.18<0,1,0>UW 1UB { align1 };
add (1) g7.12<1>F g1.18<0,1,0>UW 1UB { align1 };
/* Set up ss3.x coordinates */
mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.20<1>F g1.20<0,1,0>UW 1UB { align1 };
mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.28<1>F g1.20<0,1,0>UW 1UB { align1 };
/* Set up ss3.y coordinates */
mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
add (1) g7.24<1>F g1.22<0,1,0>UW 1UB { align1 };
add (1) g7.28<1>F g1.22<0,1,0>UW 1UB { align1 };
/* Now, map these screen space coordinates into texture coordinates. */
/* subtract screen-space X origin of vertex 0. */
add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
/* add in texture X offset */
add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
/* subtract screen-space Y origin of vertex 0. */
add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
/* scale by texture Y increment */
mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
/* add in texture Y offset */
add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
/* prepare sampler read back gX register, which would be written back to output */
/* use simd16 sampler, param 0 is u, param 1 is v. */
/* 'payload' loading, assuming tex coord start from g4 */
mov (8) m1<1>F g4<8,8,1>F { align1 };
mov (8) m2<1>F g5<8,8,1>F { align1 }; /* param 0 u in m1, m2 */
mov (8) m3<1>F g6<8,8,1>F { align1 };
mov (8) m4<1>F g7<8,8,1>F { align1 }; /* param 1 v in m3, m4 */
/* m0 will be copied with g0, as it contains send desc */
/* emit sampler 'send' cmd */
send (16) 0 /* msg reg index */
g12<1>UW /* readback */
g0<8,8,1>UW /* copy to msg start reg*/
sampler (1,0,F) /* sampler message description, (binding_table,sampler_index,datatype)
/* here(src->dst) we should use src_sampler and src_surface */
mlen 5 rlen 8 { align1 }; /* required message len 5, readback len 8 */
mov (8) g19<1>UD g19<8,8,1>UD { align1 }; /* wait sampler return */
/* if we set up read-back reg correctly, emit dataport write 'send' cmd with EOT */
/* m0, m1 are all direct passed by PS thread payload */
mov (8) m1<1>F g1<8,8,1>F { align1 };
/* prepare data in m2-m5 for subspan(1,0), m6-m9 for subspan(3,2), then it's ready to write */
/* g12 -> m2
g13 -> m6
g14 -> m3
g15 -> m7
g16 -> m4
g17 -> m8
g18 -> m5
g19 -> m9
*/
mov (8) m2<1>F g12<8,8,1>F { align1 };
mov (8) m3<1>F g14<8,8,1>F { align1 };
mov (8) m4<1>F g16<8,8,1>F { align1 };
mov (8) m5<1>F g18<8,8,1>F { align1 };
mov (8) m6<1>F g13<8,8,1>F { align1 };
mov (8) m7<1>F g15<8,8,1>F { align1 };
mov (8) m8<1>F g17<8,8,1>F { align1 };
mov (8) m9<1>F g19<8,8,1>F { align1 };
/* m0, m1 are all direct passed by PS thread payload */
mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
/* write */
send (16) 0 acc0<1>UW g0<8,8,1>UW write (
0, /* binding_table */
8, /* pixel scordboard clear, msg type simd16 single source */
4, /* render target write */
0 /* no write commit message */
)
mlen 10
rlen 0
{ align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

70
src/exa_wm_nomask_prog.h Normal file
View File

@ -0,0 +1,70 @@
{ 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
{ 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
{ 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
{ 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
{ 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
{ 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
{ 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
{ 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
{ 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
{ 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
{ 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
{ 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
{ 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
{ 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
{ 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
{ 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
{ 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
{ 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
{ 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
{ 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
{ 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
{ 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
{ 0x00600001, 0x22600021, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x202003be, 0x008d0020, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d0180, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d01c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
{ 0x00600001, 0x20a003be, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x20c003be, 0x008d01a0, 0x00000000 },
{ 0x00600001, 0x20e003be, 0x008d01e0, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0220, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d0260, 0x00000000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

3
src/i810_driver.c
View File

@ -144,6 +144,7 @@ static SymTabRec I810Chipsets[] = {
{PCI_CHIP_I965_G_1, "965G"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_CRESTLINE, "Crestline"},
{-1, NULL}
};
@ -167,6 +168,7 @@ static PciChipsets I810PciChipsets[] = {
{PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_CRESTLINE, PCI_CHIP_CRESTLINE, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED }
};
@ -603,6 +605,7 @@ I810Probe(DriverPtr drv, int flags)
case PCI_CHIP_I965_G_1:
case PCI_CHIP_I965_Q:
case PCI_CHIP_I946_GZ:
case PCI_CHIP_CRESTLINE:
xf86SetEntitySharable(usedChips[i]);
/* Allocate an entity private if necessary */

3
src/i830.h
View File

@ -73,6 +73,7 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#ifdef I830_USE_EXA
#include "exa.h"
Bool I830EXAInit(ScreenPtr pScreen);
#define EXA_LINEAR_EXTRA (64*1024)
#endif
#ifdef I830_USE_XAA
@ -267,6 +268,7 @@ typedef struct _I830Rec {
I830MemRange Scratch2;
#ifdef I830_USE_EXA
I830MemRange Offscreen;
I830MemRange EXAStateMem; /* specific exa state for G965 */
#endif
/* Regions allocated either from the above pools, or from agpgart. */
I830MemRange *CursorMem;
@ -286,6 +288,7 @@ typedef struct _I830Rec {
XF86ModReqInfo shadowReq; /* to test for later libshadow */
I830MemRange RotatedMem;
I830MemRange RotatedMem2;
I830MemRange RotateStateMem; /* for G965 state buffer */
Rotation rotation;
int InitialRotation;
int displayWidth;

26
src/i830_driver.c
View File

@ -232,6 +232,7 @@ static SymTabRec I830Chipsets[] = {
{PCI_CHIP_I965_G_1, "965G"},
{PCI_CHIP_I965_Q, "965Q"},
{PCI_CHIP_I946_GZ, "946GZ"},
{PCI_CHIP_CRESTLINE, "Crestline"},
{-1, NULL}
};
@ -249,6 +250,7 @@ static PciChipsets I830PciChipsets[] = {
{PCI_CHIP_I965_G_1, PCI_CHIP_I965_G_1, RES_SHARED_VGA},
{PCI_CHIP_I965_Q, PCI_CHIP_I965_Q, RES_SHARED_VGA},
{PCI_CHIP_I946_GZ, PCI_CHIP_I946_GZ, RES_SHARED_VGA},
{PCI_CHIP_CRESTLINE, PCI_CHIP_CRESTLINE, RES_SHARED_VGA},
{-1, -1, RES_UNDEFINED}
};
@ -1103,6 +1105,9 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_I946_GZ:
chipname = "946GZ";
break;
case PCI_CHIP_CRESTLINE:
chipname = "Crestline";
break;
default:
chipname = "unknown chipset";
break;
@ -1222,16 +1227,12 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
}
} else {
if (IS_I9XX(pI830)) {
if (pI830->PciInfo->memBase[2] & 0x08000000)
pI830->FbMapSize = 0x8000000; /* 128MB aperture */
else
pI830->FbMapSize = 0x10000000; /* 256MB aperture */
if (pI830->PciInfo->chipType == PCI_CHIP_E7221_G)
pI830->FbMapSize = 0x8000000; /* 128MB aperture */
} else
/* 128MB aperture for later chips */
pI830->FbMapSize = 1UL << pciGetBaseSize(pI830->PciTag, 2, TRUE,
NULL);
} else {
/* 128MB aperture for later i8xx series. */
pI830->FbMapSize = 0x8000000;
}
}
if (pI830->PciInfo->chipType == PCI_CHIP_E7221_G)
@ -2585,6 +2586,10 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
/* Rotated2 Buffer */
memset(&(pI830->RotatedMem2), 0, sizeof(pI830->RotatedMem2));
pI830->RotatedMem2.Key = -1;
if (IS_I965G(pI830)) {
memset(&(pI830->RotateStateMem), 0, sizeof(pI830->RotateStateMem));
pI830->RotateStateMem.Key = -1;
}
}
#ifdef HAS_MTRR_SUPPORT
@ -3289,8 +3294,7 @@ I830SwitchMode(int scrnIndex, DisplayModePtr mode, int flags)
* The extra WindowTable check detects a rotation at startup.
*/
if ( (!WindowTable[pScrn->scrnIndex] || pspix->devPrivate.ptr == NULL) &&
!pI830->DGAactive && (pScrn->PointerMoved == I830PointerMoved) &&
!IS_I965G(pI830)) {
!pI830->DGAactive && (pScrn->PointerMoved == I830PointerMoved)) {
if (!I830Rotate(pScrn, mode))
ret = FALSE;
}

11
src/i830_exa.c
View File

@ -120,6 +120,11 @@ extern Bool I915EXACheckComposite(int, PicturePtr, PicturePtr, PicturePtr);
extern Bool I915EXAPrepareComposite(int, PicturePtr, PicturePtr, PicturePtr,
PixmapPtr, PixmapPtr, PixmapPtr);
extern Bool I965EXACheckComposite(int, PicturePtr, PicturePtr, PicturePtr);
extern Bool I965EXAPrepareComposite(int, PicturePtr, PicturePtr, PicturePtr,
PixmapPtr, PixmapPtr, PixmapPtr);
extern void I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX,
int maskY, int dstX, int dstY, int width, int height);
/**
* I830EXASync - wait for a command to finish
* @pScreen: current screen
@ -418,6 +423,7 @@ IntelEXADoneComposite(PixmapPtr pDst)
I830Sync(pScrn);
#endif
}
/*
* TODO:
* - Dual head?
@ -491,6 +497,11 @@ I830EXAInit(ScreenPtr pScreen)
pI830->EXADriverPtr->PrepareComposite = I830EXAPrepareComposite;
pI830->EXADriverPtr->Composite = IntelEXAComposite;
pI830->EXADriverPtr->DoneComposite = IntelEXADoneComposite;
} else if (IS_I965G(pI830)) {
pI830->EXADriverPtr->CheckComposite = I965EXACheckComposite;
pI830->EXADriverPtr->PrepareComposite = I965EXAPrepareComposite;
pI830->EXADriverPtr->Composite = I965EXAComposite;
pI830->EXADriverPtr->DoneComposite = IntelEXADoneComposite;
}
if(!exaDriverInit(pScreen, pI830->EXADriverPtr)) {

72
src/i830_memory.c
View File

@ -518,6 +518,28 @@ I830AllocateRotatedBuffer(ScrnInfoPtr pScrn, int flags)
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sAllocated %ld kB for the rotated buffer at 0x%lx.\n", s,
alloced / 1024, pI830->RotatedMem.Start);
#define BRW_LINEAR_EXTRA (32*1024)
if (IS_I965G(pI830)) {
memset(&(pI830->RotateStateMem), 0, sizeof(I830MemRange));
pI830->RotateStateMem.Key = -1;
size = ROUND_TO_PAGE(BRW_LINEAR_EXTRA);
align = GTT_PAGE_SIZE;
alloced = I830AllocVidMem(pScrn, &(pI830->RotateStateMem),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP);
if (alloced < size) {
if (!dryrun) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"G965: Failed to allocate rotate state buffer space.\n");
}
return FALSE;
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sAllocated %ld kB for the G965 rotate state buffer at 0x%lx - 0x%lx.\n", s,
alloced / 1024, pI830->RotateStateMem.Start, pI830->RotateStateMem.End);
}
return TRUE;
}
@ -897,6 +919,25 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
"offscreen memory at 0x%lx, size %ld KB\n",
pI830->Offscreen.Start, pI830->Offscreen.Size/1024);
}
if (IS_I965G(pI830)) {
memset(&(pI830->EXAStateMem), 0, sizeof(I830MemRange));
pI830->EXAStateMem.Key = -1;
size = ROUND_TO_PAGE(EXA_LINEAR_EXTRA);
align = GTT_PAGE_SIZE;
alloced = I830AllocVidMem(pScrn, &(pI830->EXAStateMem),
&(pI830->StolenPool), size, align,
flags | FROM_ANYWHERE | ALLOCATE_AT_TOP);
if (alloced < size) {
if (!dryrun) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"G965: Failed to allocate exa state buffer space.\n");
}
return FALSE;
}
xf86DrvMsgVerb(pScrn->scrnIndex, X_INFO, verbosity,
"%sAllocated %ld kB for the G965 exa state buffer at 0x%lx - 0x%lx.\n", s,
alloced / 1024, pI830->EXAStateMem.Start, pI830->EXAStateMem.End);
}
#endif
} else {
long lineSize;
@ -1541,6 +1582,11 @@ I830FixupOffsets(ScrnInfoPtr pScrn)
I830FixOffset(pScrn, &(pI830->TexMem));
}
}
#endif
#ifdef I830_USE_EXA
I830FixOffset(pScrn, &(pI830->Offscreen));
if (IS_I965G(pI830))
I830FixOffset(pScrn, &(pI830->EXAStateMem));
#endif
return TRUE;
}
@ -1766,8 +1812,13 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
int i;
/* Clear out */
for (i = 0; i < 8; i++)
pI830->ModeReg.Fence[i] = 0;
if (IS_I965G(pI830)) {
for (i = 0; i < FENCE_NEW_NR*2; i++)
pI830->ModeReg.Fence[i] = 0;
} else {
for (i = 0; i < 8; i++)
pI830->ModeReg.Fence[i] = 0;
}
nextTile = 0;
tileGeneration = -1;
@ -1837,6 +1888,9 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
}
}
/* XXX tiled rotate mem not ready on G965*/
if(!IS_I965G(pI830)) {
if (pI830->RotatedMem.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem), FENCE_XMAJOR)) {
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
@ -1847,7 +1901,7 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
"MakeTiles failed for the rotated buffer.\n");
}
}
}
#if 0
if (pI830->RotatedMem2.Alignment >= KB(512)) {
if (MakeTiles(pScrn, &(pI830->RotatedMem2), FENCE_XMAJOR)) {
@ -1942,6 +1996,12 @@ I830BindAGPMemory(ScrnInfoPtr pScrn)
!BindMemRange(pScrn, &(pI830->TexMem)))
return FALSE;
}
#endif
#ifdef I830_USE_EXA
if (!BindMemRange(pScrn, &(pI830->Offscreen)))
return FALSE;
if (IS_I965G(pI830) && !BindMemRange(pScrn, &(pI830->EXAStateMem)))
return FALSE;
#endif
pI830->GttBound = 1;
}
@ -2027,6 +2087,12 @@ I830UnbindAGPMemory(ScrnInfoPtr pScrn)
!UnbindMemRange(pScrn, &(pI830->TexMem)))
return FALSE;
}
#endif
#ifdef I830_USE_EXA
if (!UnbindMemRange(pScrn, &(pI830->Offscreen)))
return FALSE;
if (IS_I965G(pI830) && !UnbindMemRange(pScrn, &(pI830->EXAStateMem)))
return FALSE;
#endif
if (!xf86ReleaseGART(pScrn->scrnIndex))
return FALSE;

753
src/i830_rotate.c
View File

@ -60,6 +60,8 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830.h"
#include "i915_reg.h"
#include "i915_3d.h"
#include "brw_defines.h"
#include "brw_structs.h"
#ifdef XF86DRI
#include "dri.h"
@ -194,6 +196,718 @@ static void draw_poly(CARD32 *vb,
}
}
/* Our PS kernel uses less than 32 GRF registers (about 20) */
#define PS_KERNEL_NUM_GRF 32
#define PS_MAX_THREADS 32
#define BRW_GRF_BLOCKS(nreg) ((nreg + 15) / 16 - 1)
static const CARD32 ps_kernel_static0[][4] = {
#include "rotation_wm_prog0.h"
};
static const CARD32 ps_kernel_static90[][4] = {
#include "rotation_wm_prog90.h"
};
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define BRW_LINEAR_EXTRA (32*1024)
#define WM_BINDING_TABLE_ENTRIES 2
static const CARD32 sip_kernel_static[][4] = {
/* wait (1) a0<1>UW a145<0,1,0>UW { align1 + } */
{ 0x00000030, 0x20000108, 0x00001220, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
/* nop (4) g0<1>UD { align1 + } */
{ 0x0040007e, 0x20000c21, 0x00690000, 0x00000000 },
};
#define SF_KERNEL_NUM_GRF 16
#define SF_MAX_THREADS 1
static const CARD32 sf_kernel_static0[][4] = {
#include "rotation_sf_prog0.h"
};
static const CARD32 sf_kernel_static90[][4] = {
#include "rotation_sf_prog90.h"
};
static void
I965UpdateRotate (ScreenPtr pScreen,
shadowBufPtr pBuf)
{
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
ScrnInfoPtr pScrn1 = pScrn;
I830Ptr pI8301 = NULL;
RegionPtr damage = shadowDamage(pBuf);
int nbox = REGION_NUM_RECTS (damage);
BoxPtr pbox = REGION_RECTS (damage);
int box_x1, box_x2, box_y1, box_y2;
float verts[4][2];
struct matrix23 rotMatrix;
Bool updateInvarient = FALSE;
#ifdef XF86DRI
drmI830Sarea *sarea = NULL;
drm_context_t myContext = 0;
#endif
Bool didLock = FALSE;
/* Gen4 states */
int urb_vs_start, urb_vs_size;
int urb_gs_start, urb_gs_size;
int urb_clip_start, urb_clip_size;
int urb_sf_start, urb_sf_size;
int urb_cs_start, urb_cs_size;
struct brw_surface_state *dest_surf_state;
struct brw_surface_state *src_surf_state;
struct brw_sampler_state *src_sampler_state;
struct brw_vs_unit_state *vs_state;
struct brw_sf_unit_state *sf_state;
struct brw_wm_unit_state *wm_state;
struct brw_cc_unit_state *cc_state;
struct brw_cc_viewport *cc_viewport;
struct brw_instruction *sf_kernel;
struct brw_instruction *ps_kernel;
struct brw_instruction *sip_kernel;
float *vb;
BOOL first_output = TRUE;
CARD32 *binding_table;
int dest_surf_offset, src_surf_offset, src_sampler_offset, vs_offset;
int sf_offset, wm_offset, cc_offset, vb_offset, cc_viewport_offset;
int wm_scratch_offset;
int sf_kernel_offset, ps_kernel_offset, sip_kernel_offset;
int binding_table_offset;
int next_offset, total_state_size;
int vb_size = (4 * 4) * 4; /* 4 DWORDS per vertex */
char *state_base;
int state_base_offset;
DPRINTF(PFX, "I965UpdateRotate: from (%d x %d) -> (%d x %d)\n",
pScrn->virtualX, pScrn->virtualY, pScreen->width, pScreen->height);
if (I830IsPrimary(pScrn)) {
pI8301 = pI830;
} else {
pI8301 = I830PTR(pI830->entityPrivate->pScrn_1);
pScrn1 = pI830->entityPrivate->pScrn_1;
}
switch (pI830->rotation) {
case RR_Rotate_90:
matrix23Rotate(&rotMatrix,
pScreen->width, pScreen->height,
90);
break;
case RR_Rotate_180:
matrix23Rotate(&rotMatrix,
pScreen->width, pScreen->height,
180);
break;
case RR_Rotate_270:
matrix23Rotate(&rotMatrix,
pScreen->width, pScreen->height,
270);
break;
default:
break;
}
#ifdef XF86DRI
if (pI8301->directRenderingEnabled) {
sarea = DRIGetSAREAPrivate(pScrn1->pScreen);
myContext = DRIGetContext(pScrn1->pScreen);
didLock = I830DRILock(pScrn1);
}
#endif
if (pScrn->scrnIndex != *pI830->used3D)
updateInvarient = TRUE;
#ifdef XF86DRI
if (sarea && sarea->ctxOwner != myContext)
updateInvarient = TRUE;
#endif
/*XXX we'll always update state */
*pI830->used3D = pScrn->scrnIndex;
#ifdef XF86DRI
if (sarea)
sarea->ctxOwner = myContext;
#endif
/* this starts initialize 3D engine for rotation mapping*/
next_offset = 0;
/* Set up our layout of state in framebuffer. First the general state: */
vs_offset = ALIGN(next_offset, 64);
next_offset = vs_offset + sizeof(*vs_state);
sf_offset = ALIGN(next_offset, 32);
next_offset = sf_offset + sizeof(*sf_state);
wm_offset = ALIGN(next_offset, 32);
next_offset = wm_offset + sizeof(*wm_state);
wm_scratch_offset = ALIGN(next_offset, 1024);
next_offset = wm_scratch_offset + 1024 * PS_MAX_THREADS;
cc_offset = ALIGN(next_offset, 32);
next_offset = cc_offset + sizeof(*cc_state);
sf_kernel_offset = ALIGN(next_offset, 64);
switch (pI830->rotation) {
case RR_Rotate_90:
case RR_Rotate_270:
next_offset = sf_kernel_offset + sizeof (sf_kernel_static90);
ps_kernel_offset = ALIGN(next_offset, 64);
next_offset = ps_kernel_offset + sizeof (ps_kernel_static90);
break;
case RR_Rotate_180:
default:
next_offset = sf_kernel_offset + sizeof (sf_kernel_static0);
ps_kernel_offset = ALIGN(next_offset, 64);
next_offset = ps_kernel_offset + sizeof (ps_kernel_static0);
break;
}
sip_kernel_offset = ALIGN(next_offset, 64);
next_offset = sip_kernel_offset + sizeof (sip_kernel_static);
cc_viewport_offset = ALIGN(next_offset, 32);
next_offset = cc_viewport_offset + sizeof(*cc_viewport);
src_sampler_offset = ALIGN(next_offset, 32);
next_offset = src_sampler_offset + sizeof(*src_sampler_state);
/* Align VB to native size of elements, for safety */
vb_offset = ALIGN(next_offset, 8);
next_offset = vb_offset + vb_size;
dest_surf_offset = ALIGN(next_offset, 32);
next_offset = dest_surf_offset + sizeof(*dest_surf_state);
src_surf_offset = ALIGN(next_offset, 32);
next_offset = src_surf_offset + sizeof(*src_surf_state);
binding_table_offset = ALIGN(next_offset, 32);
next_offset = binding_table_offset + (WM_BINDING_TABLE_ENTRIES * 4);
total_state_size = next_offset;
assert (total_state_size < BRW_LINEAR_EXTRA);
state_base_offset = pI830->RotateStateMem.Start;
state_base_offset = ALIGN(state_base_offset, 64);
state_base = (char *)(pI830->FbBase + state_base_offset);
DPRINTF(PFX, "rotate state buffer start 0x%x, addr 0x%x, base 0x%x\n",
pI830->RotateStateMem.Start, state_base, pI830->FbBase);
vs_state = (void *)(state_base + vs_offset);
sf_state = (void *)(state_base + sf_offset);
wm_state = (void *)(state_base + wm_offset);
cc_state = (void *)(state_base + cc_offset);
sf_kernel = (void *)(state_base + sf_kernel_offset);
ps_kernel = (void *)(state_base + ps_kernel_offset);
sip_kernel = (void *)(state_base + sip_kernel_offset);
cc_viewport = (void *)(state_base + cc_viewport_offset);
dest_surf_state = (void *)(state_base + dest_surf_offset);
src_surf_state = (void *)(state_base + src_surf_offset);
src_sampler_state = (void *)(state_base + src_sampler_offset);
binding_table = (void *)(state_base + binding_table_offset);
vb = (void *)(state_base + vb_offset);
/* For 3D, the VS must have 8, 12, 16, 24, or 32 VUEs allocated to it.
* A VUE consists of a 256-bit vertex header followed by the vertex data,
* which in our case is 4 floats (128 bits), thus a single 512-bit URB
* entry.
*/
#define URB_VS_ENTRIES 8
#define URB_VS_ENTRY_SIZE 1
#define URB_GS_ENTRIES 0
#define URB_GS_ENTRY_SIZE 0
#define URB_CLIP_ENTRIES 0
#define URB_CLIP_ENTRY_SIZE 0
/* The SF kernel we use outputs only 4 256-bit registers, leading to an
* entry size of 2 512-bit URBs. We don't need to have many entries to
* output as we're generally working on large rectangles and don't care
* about having WM threads running on different rectangles simultaneously.
*/
#define URB_SF_ENTRIES 1
#define URB_SF_ENTRY_SIZE 2
#define URB_CS_ENTRIES 0
#define URB_CS_ENTRY_SIZE 0
urb_vs_start = 0;
urb_vs_size = URB_VS_ENTRIES * URB_VS_ENTRY_SIZE;
urb_gs_start = urb_vs_start + urb_vs_size;
urb_gs_size = URB_GS_ENTRIES * URB_GS_ENTRY_SIZE;
urb_clip_start = urb_gs_start + urb_gs_size;
urb_clip_size = URB_CLIP_ENTRIES * URB_CLIP_ENTRY_SIZE;
urb_sf_start = urb_clip_start + urb_clip_size;
urb_sf_size = URB_SF_ENTRIES * URB_SF_ENTRY_SIZE;
urb_cs_start = urb_sf_start + urb_sf_size;
urb_cs_size = URB_CS_ENTRIES * URB_CS_ENTRY_SIZE;
memset (cc_viewport, 0, sizeof (*cc_viewport));
cc_viewport->min_depth = -1.e35;
cc_viewport->max_depth = 1.e35;
memset(cc_state, 0, sizeof(*cc_state));
cc_state->cc0.stencil_enable = 0; /* disable stencil */
cc_state->cc2.depth_test = 0; /* disable depth test */
cc_state->cc2.logicop_enable = 1; /* enable logic op */
cc_state->cc3.ia_blend_enable = 1; /* blend alpha just like colors */
cc_state->cc3.blend_enable = 0; /* disable color blend */
cc_state->cc3.alpha_test = 0; /* disable alpha test */
cc_state->cc4.cc_viewport_state_offset = (state_base_offset + cc_viewport_offset) >> 5;
cc_state->cc5.dither_enable = 0; /* disable dither */
cc_state->cc5.logicop_func = 0xc; /* COPY S*/
cc_state->cc5.statistics_enable = 1;
cc_state->cc5.ia_blend_function = BRW_BLENDFUNCTION_ADD;
cc_state->cc5.ia_src_blend_factor = BRW_BLENDFACTOR_ONE;
cc_state->cc5.ia_dest_blend_factor = BRW_BLENDFACTOR_ZERO;
/* Upload system kernel */
memcpy (sip_kernel, sip_kernel_static, sizeof (sip_kernel_static));
memset(dest_surf_state, 0, sizeof(*dest_surf_state));
dest_surf_state->ss0.surface_type = BRW_SURFACE_2D;
dest_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;
if (pI8301->cpp == 2)
dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
else
dest_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
dest_surf_state->ss0.writedisable_alpha = 0;
dest_surf_state->ss0.writedisable_red = 0;
dest_surf_state->ss0.writedisable_green = 0;
dest_surf_state->ss0.writedisable_blue = 0;
dest_surf_state->ss0.color_blend = 0;
dest_surf_state->ss0.vert_line_stride = 0;
dest_surf_state->ss0.vert_line_stride_ofs = 0;
dest_surf_state->ss0.mipmap_layout_mode = 0;
dest_surf_state->ss0.render_cache_read_mode = 0;
if (I830IsPrimary(pScrn))
dest_surf_state->ss1.base_addr = pI830->FrontBuffer.Start;
else
dest_surf_state->ss1.base_addr = pI8301->FrontBuffer2.Start;
dest_surf_state->ss2.width = pScrn->virtualX - 1;
dest_surf_state->ss2.height = pScrn->virtualY - 1;
dest_surf_state->ss2.mip_count = 0;
dest_surf_state->ss2.render_target_rotation = 0; /*XXX how to use? */
dest_surf_state->ss3.pitch = (pI830->displayWidth * pI830->cpp) - 1;
if (pI830->front_tiled) {
dest_surf_state->ss3.tiled_surface = 1;
dest_surf_state->ss3.tile_walk = 0; /* X major */
}
memset(src_surf_state, 0, sizeof(*src_surf_state));
src_surf_state->ss0.surface_type = BRW_SURFACE_2D;
/* src_surf_state->ss0.data_return_format = BRW_SURFACERETURNFORMAT_FLOAT32;*/
if (pI8301->cpp == 2)
src_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B5G6R5_UNORM;
else
src_surf_state->ss0.surface_format = BRW_SURFACEFORMAT_B8G8R8A8_UNORM;
src_surf_state->ss0.writedisable_alpha = 0;
src_surf_state->ss0.writedisable_red = 0;
src_surf_state->ss0.writedisable_green = 0;
src_surf_state->ss0.writedisable_blue = 0;
src_surf_state->ss0.color_blend = 0;
src_surf_state->ss0.vert_line_stride = 0;
src_surf_state->ss0.vert_line_stride_ofs = 0;
src_surf_state->ss0.mipmap_layout_mode = 0;
src_surf_state->ss0.render_cache_read_mode = 0;
if (I830IsPrimary(pScrn))
src_surf_state->ss1.base_addr = pI830->RotatedMem.Start;
else
src_surf_state->ss1.base_addr = pI8301->RotatedMem2.Start;
src_surf_state->ss2.width = pScreen->width - 1;
src_surf_state->ss2.height = pScreen->height - 1;
src_surf_state->ss2.mip_count = 0;
src_surf_state->ss2.render_target_rotation = 0;
src_surf_state->ss3.pitch = (pScrn->displayWidth * pI830->cpp) - 1;
if (pI830->rotated_tiled) {
src_surf_state->ss3.tiled_surface = 1;
src_surf_state->ss3.tile_walk = 0; /* X major */
}
binding_table[0] = state_base_offset + dest_surf_offset;
binding_table[1] = state_base_offset + src_surf_offset;
memset(src_sampler_state, 0, sizeof(*src_sampler_state));
src_sampler_state->ss0.min_filter = BRW_MAPFILTER_LINEAR;
src_sampler_state->ss0.mag_filter = BRW_MAPFILTER_LINEAR;
src_sampler_state->ss1.r_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
src_sampler_state->ss1.s_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
src_sampler_state->ss1.t_wrap_mode = BRW_TEXCOORDMODE_CLAMP;
/* Set up the vertex shader to be disabled (passthrough) */
memset(vs_state, 0, sizeof(*vs_state));
vs_state->thread4.nr_urb_entries = URB_VS_ENTRIES;
vs_state->thread4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
vs_state->vs6.vs_enable = 0;
vs_state->vs6.vert_cache_disable = 1;
/* Set up the SF kernel to do coord interp: for each attribute,
* calculate dA/dx and dA/dy. Hand these interpolation coefficients
* back to SF which then hands pixels off to WM.
*/
switch (pI830->rotation) {
case RR_Rotate_90:
case RR_Rotate_270:
memcpy (sf_kernel, sf_kernel_static90, sizeof (sf_kernel_static90));
memcpy (ps_kernel, ps_kernel_static90, sizeof (ps_kernel_static90));
break;
case RR_Rotate_180:
default:
memcpy (sf_kernel, sf_kernel_static0, sizeof (sf_kernel_static0));
memcpy (ps_kernel, ps_kernel_static0, sizeof (ps_kernel_static0));
break;
}
memset(sf_state, 0, sizeof(*sf_state));
sf_state->thread0.kernel_start_pointer =
(state_base_offset + sf_kernel_offset) >> 6;
sf_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
sf_state->sf1.single_program_flow = 1; /* XXX */
sf_state->sf1.binding_table_entry_count = 0;
sf_state->sf1.thread_priority = 0;
sf_state->sf1.floating_point_mode = 0;
sf_state->sf1.illegal_op_exception_enable = 1;
sf_state->sf1.mask_stack_exception_enable = 1;
sf_state->sf1.sw_exception_enable = 1;
sf_state->thread2.per_thread_scratch_space = 0;
sf_state->thread2.scratch_space_base_pointer = 0; /* not used in our kernel */
sf_state->thread3.const_urb_entry_read_length = 0; /* no const URBs */
sf_state->thread3.const_urb_entry_read_offset = 0; /* no const URBs */
sf_state->thread3.urb_entry_read_length = 1; /* 1 URB per vertex */
sf_state->thread3.urb_entry_read_offset = 0;
sf_state->thread3.dispatch_grf_start_reg = 3;
sf_state->thread4.max_threads = SF_MAX_THREADS - 1;
sf_state->thread4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
sf_state->thread4.nr_urb_entries = URB_SF_ENTRIES;
sf_state->thread4.stats_enable = 1;
sf_state->sf5.viewport_transform = FALSE; /* skip viewport */
sf_state->sf6.cull_mode = BRW_CULLMODE_NONE;
sf_state->sf6.scissor = 0;
sf_state->sf7.trifan_pv = 2;
sf_state->sf6.dest_org_vbias = 0x8;
sf_state->sf6.dest_org_hbias = 0x8;
memset (wm_state, 0, sizeof (*wm_state));
wm_state->thread0.kernel_start_pointer =
(state_base_offset + ps_kernel_offset) >> 6;
wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
wm_state->thread1.single_program_flow = 1; /* XXX */
wm_state->thread1.binding_table_entry_count = 2;
/* Though we never use the scratch space in our WM kernel, it has to be
* set, and the minimum allocation is 1024 bytes.
*/
wm_state->thread2.scratch_space_base_pointer = (state_base_offset +
wm_scratch_offset) >> 10;
wm_state->thread2.per_thread_scratch_space = 0; /* 1024 bytes */
wm_state->thread3.dispatch_grf_start_reg = 3;
wm_state->thread3.const_urb_entry_read_length = 0;
wm_state->thread3.const_urb_entry_read_offset = 0;
wm_state->thread3.urb_entry_read_length = 1;
wm_state->thread3.urb_entry_read_offset = 0;
wm_state->wm4.stats_enable = 1;
wm_state->wm4.sampler_state_pointer = (state_base_offset + src_sampler_offset) >> 5;
wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
wm_state->wm5.thread_dispatch_enable = 1;
wm_state->wm5.enable_16_pix = 1;
wm_state->wm5.enable_8_pix = 0;
wm_state->wm5.early_depth_test = 1;
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH |
MI_STATE_INSTRUCTION_CACHE_FLUSH |
BRW_MI_GLOBAL_SNAPSHOT_RESET);
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
}
{
BEGIN_LP_RING(12);
OUT_RING(BRW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
/* Mesa does this. Who knows... */
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING((0 << 4) | /* URB Entry Allocation Size */
(0 << 0)); /* Number of URB Entries */
/* Zero out the two base address registers so all offsets are absolute */
OUT_RING(BRW_STATE_BASE_ADDRESS | 4);
OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Generate state base address */
OUT_RING(0 | BASE_ADDRESS_MODIFY); /* Surface state base address */
OUT_RING(0 | BASE_ADDRESS_MODIFY); /* media base addr, don't care */
OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY); /* general state max addr, disabled */
OUT_RING(0x10000000 | BASE_ADDRESS_MODIFY); /* media object state max addr, disabled */
/* Set system instruction pointer */
OUT_RING(BRW_STATE_SIP | 0);
OUT_RING(state_base_offset + sip_kernel_offset); /* system instruction pointer */
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
}
{
BEGIN_LP_RING(36);
/* Enable VF statistics */
OUT_RING(BRW_3DSTATE_VF_STATISTICS | 1);
/* Pipe control */
OUT_RING(BRW_PIPE_CONTROL |
BRW_PIPE_CONTROL_NOWRITE |
BRW_PIPE_CONTROL_IS_FLUSH |
2);
OUT_RING(0); /* Destination address */
OUT_RING(0); /* Immediate data low DW */
OUT_RING(0); /* Immediate data high DW */
/* Binding table pointers */
OUT_RING(BRW_3DSTATE_BINDING_TABLE_POINTERS | 4);
OUT_RING(0); /* vs */
OUT_RING(0); /* gs */
OUT_RING(0); /* clip */
OUT_RING(0); /* sf */
/* Only the PS uses the binding table */
OUT_RING(state_base_offset + binding_table_offset); /* ps */
/* XXX: Blend constant color (magenta is fun) */
//OUT_RING(BRW_3DSTATE_CONSTANT_COLOR | 3);
//OUT_RING(float_to_uint (1.0));
//OUT_RING(float_to_uint (0.0));
//OUT_RING(float_to_uint (1.0));
//OUT_RING(float_to_uint (1.0));
/* The drawing rectangle clipping is always on. Set it to values that
* shouldn't do any clipping.
*/
OUT_RING(BRW_3DSTATE_DRAWING_RECTANGLE | 2); /* XXX 3 for BLC or CTG */
OUT_RING(0x00000000); /* ymin, xmin */
OUT_RING((pScrn->virtualX - 1) |
(pScrn->virtualY - 1) << 16); /* ymax, xmax */
OUT_RING(0x00000000); /* yorigin, xorigin */
/* skip the depth buffer */
/* skip the polygon stipple */
/* skip the polygon stipple offset */
/* skip the line stipple */
/* Set the pointers to the 3d pipeline state */
OUT_RING(BRW_3DSTATE_PIPELINED_POINTERS | 5);
OUT_RING(state_base_offset + vs_offset); /* 32 byte aligned */
OUT_RING(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
OUT_RING(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
OUT_RING(state_base_offset + sf_offset); /* 32 byte aligned */
OUT_RING(state_base_offset + wm_offset); /* 32 byte aligned */
OUT_RING(state_base_offset + cc_offset); /* 64 byte aligned */
/* URB fence */
OUT_RING(BRW_URB_FENCE |
UF0_CS_REALLOC |
UF0_SF_REALLOC |
UF0_CLIP_REALLOC |
UF0_GS_REALLOC |
UF0_VS_REALLOC |
1);
OUT_RING(((urb_clip_start + urb_clip_size) << UF1_CLIP_FENCE_SHIFT) |
((urb_gs_start + urb_gs_size) << UF1_GS_FENCE_SHIFT) |
((urb_vs_start + urb_vs_size) << UF1_VS_FENCE_SHIFT));
OUT_RING(((urb_cs_start + urb_cs_size) << UF2_CS_FENCE_SHIFT) |
((urb_sf_start + urb_sf_size) << UF2_SF_FENCE_SHIFT));
/* Constant buffer state */
OUT_RING(BRW_CS_URB_STATE | 0);
OUT_RING(((URB_CS_ENTRY_SIZE - 1) << 4) | /* URB Entry Allocation Size */
(URB_CS_ENTRIES << 0)); /* Number of URB Entries */
/* Set up the pointer to our vertex buffer */
OUT_RING(BRW_3DSTATE_VERTEX_BUFFERS | 2);
OUT_RING((0 << VB0_BUFFER_INDEX_SHIFT) |
VB0_VERTEXDATA |
((4 * 4) << VB0_BUFFER_PITCH_SHIFT)); /* four 32-bit floats per vertex */
OUT_RING(state_base_offset + vb_offset);
OUT_RING(3); /* four corners to our rectangle */
/* Set up our vertex elements, sourced from the single vertex buffer. */
OUT_RING(BRW_3DSTATE_VERTEX_ELEMENTS | 3);
/* offset 0: X,Y -> {X, Y, 1.0, 1.0} */
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(0 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(0 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
/* offset 8: S0, T0 -> {S0, T0, 1.0, 1.0} */
OUT_RING((0 << VE0_VERTEX_BUFFER_INDEX_SHIFT) |
VE0_VALID |
(BRW_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT) |
(8 << VE0_OFFSET_SHIFT));
OUT_RING((BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT) |
(BRW_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT) |
(BRW_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT) |
(4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT));
//OUT_RING(MI_NOOP); /* pad to quadword */
ADVANCE_LP_RING();
}
{
BEGIN_LP_RING(2);
OUT_RING(MI_FLUSH |
MI_STATE_INSTRUCTION_CACHE_FLUSH |
BRW_MI_GLOBAL_SNAPSHOT_RESET);
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
}
while (nbox--)
{
float src_scale_x, src_scale_y;
int i;
box_x1 = pbox->x1;
box_y1 = pbox->y1;
box_x2 = pbox->x2;
box_y2 = pbox->y2;
if (!first_output) {
/* Since we use the same little vertex buffer over and over, sync for
* subsequent rectangles.
*/
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
}
pbox++;
verts[0][0] = box_x1; verts[0][1] = box_y1;
verts[1][0] = box_x2; verts[1][1] = box_y1;
verts[2][0] = box_x2; verts[2][1] = box_y2;
verts[3][0] = box_x1; verts[3][1] = box_y2;
/* transform coordinates to rotated versions, but leave texcoords unchanged */
for (i = 0; i < 4; i++)
matrix23TransformCoordf(&rotMatrix, &verts[i][0], &verts[i][1]);
src_scale_x = (float)1.0 / (float)pScreen->width;
src_scale_y = (float)1.0 / (float)pScreen->height;
i = 0;
DPRINTF(PFX, "box size (%d, %d) -> (%d, %d)\n",
box_x1, box_y1, box_x2, box_y2);
switch (pI830->rotation) {
case RR_Rotate_90:
vb[i++] = (float)box_x1 * src_scale_x;
vb[i++] = (float)box_y2 * src_scale_y;
vb[i++] = verts[3][0];
vb[i++] = verts[3][1];
vb[i++] = (float)box_x1 * src_scale_x;
vb[i++] = (float)box_y1 * src_scale_y;
vb[i++] = verts[0][0];
vb[i++] = verts[0][1];
vb[i++] = (float)box_x2 * src_scale_x;
vb[i++] = (float)box_y1 * src_scale_y;
vb[i++] = verts[1][0];
vb[i++] = verts[1][1];
break;
case RR_Rotate_270:
vb[i++] = (float)box_x2 * src_scale_x;
vb[i++] = (float)box_y1 * src_scale_y;
vb[i++] = verts[1][0];
vb[i++] = verts[1][1];
vb[i++] = (float)box_x2 * src_scale_x;
vb[i++] = (float)box_y2 * src_scale_y;
vb[i++] = verts[2][0];
vb[i++] = verts[2][1];
vb[i++] = (float)box_x1 * src_scale_x;
vb[i++] = (float)box_y2 * src_scale_y;
vb[i++] = verts[3][0];
vb[i++] = verts[3][1];
break;
case RR_Rotate_180:
default:
vb[i++] = (float)box_x1 * src_scale_x;
vb[i++] = (float)box_y1 * src_scale_y;
vb[i++] = verts[0][0];
vb[i++] = verts[0][1];
vb[i++] = (float)box_x2 * src_scale_x;
vb[i++] = (float)box_y1 * src_scale_y;
vb[i++] = verts[1][0];
vb[i++] = verts[1][1];
vb[i++] = (float)box_x2 * src_scale_x;
vb[i++] = (float)box_y2 * src_scale_y;
vb[i++] = verts[2][0];
vb[i++] = verts[2][1];
break;
}
BEGIN_LP_RING(6);
OUT_RING(BRW_3DPRIMITIVE |
BRW_3DPRIMITIVE_VERTEX_SEQUENTIAL |
(_3DPRIM_RECTLIST << BRW_3DPRIMITIVE_TOPOLOGY_SHIFT) |
(0 << 9) | /* CTG - indirect vertex count */
4);
OUT_RING(3); /* vertex count per instance */
OUT_RING(0); /* start vertex offset */
OUT_RING(1); /* single instance */
OUT_RING(0); /* start instance location */
OUT_RING(0); /* index buffer offset, ignored */
ADVANCE_LP_RING();
first_output = FALSE;
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
}
if (pI830->AccelInfoRec)
(*pI830->AccelInfoRec->Sync)(pScrn);
#ifdef XF86DRI
if (didLock)
I830DRIUnlock(pScrn1);
#endif
}
static void
I915UpdateRotate (ScreenPtr pScreen,
shadowBufPtr pBuf)
@ -657,11 +1371,15 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
if (pI830->noAccel)
func = LoaderSymbol("shadowUpdateRotatePacked");
else
if (IS_I9XX(pI830))
func = I915UpdateRotate;
else
else {
if (IS_I9XX(pI830)) {
if (IS_I965G(pI830))
func = I965UpdateRotate;
else
func = I915UpdateRotate;
} else
func = I830UpdateRotate;
}
if (I830IsPrimary(pScrn)) {
pI8301 = pI830;
@ -738,6 +1456,15 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
memset(&(pI8301->RotatedMem), 0, sizeof(pI8301->RotatedMem));
pI8301->RotatedMem.Key = -1;
if (IS_I965G(pI8301)) {
if (pI8301->RotateStateMem.Key != -1)
xf86UnbindGARTMemory(pScrn1->scrnIndex, pI8301->RotateStateMem.Key);
I830FreeVidMem(pScrn1, &(pI8301->RotateStateMem));
memset(&(pI8301->RotateStateMem), 0, sizeof(pI8301->RotateStateMem));
pI8301->RotateStateMem.Key = -1;
}
if (pI830->entityPrivate) {
if (pI8301->RotatedMem2.Key != -1)
xf86UnbindGARTMemory(pScrn1->scrnIndex, pI8301->RotatedMem2.Key);
@ -820,6 +1547,12 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
I830FixOffset(pScrn1, &(pI8301->RotatedMem));
if (pI8301->RotatedMem.Key != -1)
xf86BindGARTMemory(pScrn1->scrnIndex, pI8301->RotatedMem.Key, pI8301->RotatedMem.Offset);
if (IS_I965G(pI8301)) {
I830FixOffset(pScrn1, &(pI8301->RotateStateMem));
if (pI8301->RotateStateMem.Key != -1)
xf86BindGARTMemory(pScrn1->scrnIndex, pI8301->RotateStateMem.Key,
pI8301->RotateStateMem.Offset);
}
}
}
@ -887,8 +1620,16 @@ I830Rotate(ScrnInfoPtr pScrn, DisplayModePtr mode)
}
I830SetupMemoryTiling(pScrn1);
/* update fence registers */
for (i = 0; i < 8; i++)
OUTREG(FENCE + i * 4, pI8301->ModeReg.Fence[i]);
if (IS_I965G(pI830)) {
for (i = 0; i < FENCE_NEW_NR; i++) {
OUTREG(FENCE_NEW + i * 8, pI830->ModeReg.Fence[i]);
OUTREG(FENCE_NEW + 4 + i * 8, pI830->ModeReg.Fence[i+FENCE_NEW_NR]);
}
} else {
for (i = 0; i < 8; i++)
OUTREG(FENCE + i * 4, pI8301->ModeReg.Fence[i]);
}
{
drmI830Sarea *sarea = DRIGetSAREAPrivate(pScrn1->pScreen);
I830UpdateDRIBuffers(pScrn1, sarea );

3
src/i830_sdvo.c
View File

@ -1093,7 +1093,6 @@ i830_sdvo_init(ScrnInfoPtr pScrn, int output_device)
output->driver_private = intel_output;
dev_priv = (struct i830_sdvo_priv *) (intel_output + 1);
intel_output->type = I830_OUTPUT_SDVO;
/* While it's the same bus, we just initialize a new copy to avoid trouble
* with tracking refcounting ourselves, since the XFree86 DDX bits don't.
@ -1212,7 +1211,7 @@ i830_sdvo_init(ScrnInfoPtr pScrn, int output_device)
i830_sdvo_get_input_pixel_clock_range(output, &dev_priv->pixel_clock_min,
&dev_priv->pixel_clock_max);
intel_output->type = I830_OUTPUT_SDVO;
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"%s device VID/DID: %02X:%02X.%02X, "
"clock range %.1fMHz - %.1fMHz, "

192
src/i830_tv.c
View File

@ -249,6 +249,53 @@ const tv_mode_t tv_modes[] = {
.ru =-0.0957, .gu =-0.1879, .bu = 0.2836, .au = 1.0000,
.rv = 0.3992, .gv =-0.3343, .bv =-0.0649, .av = 1.0000,
},
},
{
/* 625 Lines, 50 Fields, 15.625KHz line, Sub-Carrier 4.434MHz */
.name = "PAL 576i",
.oversample = TV_OVERSAMPLE_8X,
.hsync_end = 64, .hblank_end = 128,
.hblank_start = 844, .htotal = 863,
.progressive = FALSE,
.vsync_start_f1 = 6, .vsync_start_f2 = 7,
.vsync_len = 6,
.veq_ena = TRUE, .veq_start_f1 = 0,
.veq_start_f2 = 1, .veq_len = 18,
.vi_end_f1 = 24, .vi_end_f2 = 25,
.nbr_end = 286,
.burst_ena = TRUE,
.hburst_start = 73, .hburst_len = 34,
.vburst_start_f1 = 8, .vburst_end_f1 = 285,
.vburst_start_f2 = 8, .vburst_end_f2 = 286,
.vburst_start_f3 = 9, .vburst_end_f3 = 286,
.vburst_start_f4 = 9, .vburst_end_f4 = 285,
/* desired 4.4336180 actual 4.4336180 clock 107.52 */
.dda1_inc = 168,
.dda2_inc = 18557, .dda2_size = 20625,
.dda3_inc = 0, .dda3_size = 0,
.sc_reset = TV_SC_RESET_EVERY_8,
.pal_burst = TRUE,
.composite_levels = { .blank = 237, .black = 237, .burst = 118 },
.composite_color = {
.ry = 0.2990, .gy = 0.5870, .by = 0.1140, .ay = 0.5379,
.ru =-0.0793, .gu =-0.1557, .bu = 0.2350, .au = 1.0000,
.rv = 0.3307, .gv =-0.2769, .bv =-0.0538, .av = 1.0000,
},
.svideo_levels = { .blank = 280, .black = 280, .burst = 139 },
.svideo_color = {
.ry = 0.2990, .gy = 0.5870, .by = 0.1140, .ay = 0.6357,
.ru =-0.0937, .gu =-0.1840, .bu = 0.2777, .au = 1.0000,
.rv = 0.3908, .gv =-0.3273, .bv =-0.0636, .av = 1.0000,
},
}
#if 0
{
@ -374,13 +421,15 @@ i830_tv_dpms(xf86OutputPtr output, int mode)
switch(mode) {
case DPMSModeOn:
OUTREG(TV_CTL, INREG(TV_CTL) | TV_ENC_ENABLE);
break;
/* Wait for a Vblank when reenable TV encoder */
i830WaitForVblank(pScrn);
OUTREG(TV_CTL, INREG(TV_CTL) | TV_ENC_ENABLE);
break;
case DPMSModeStandby:
case DPMSModeSuspend:
case DPMSModeOff:
OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
break;
/*OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);*/
break;
}
}
@ -639,10 +688,10 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
* mode. For now, just set the first one in the list, with
* NTSC format.
*/
OUTREG(TV_CTL, INREG(TV_CTL) & ~TV_ENC_ENABLE);
tv_mode = &tv_modes[0];
tv_ctl = 0;
switch (dev_priv->type) {
default:
case TV_TYPE_UNKNOWN:
@ -733,8 +782,8 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
tv_mode->dda3_inc << TV_SCDDA3_INC_SHIFT;
/* Enable two fixes for the chips that need them. */
if (pI830->PciInfo->chipType < PCI_CHIP_I945_G)
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
if (pI830->PciInfo->chipType < PCI_CHIP_I945_G)
tv_ctl |= TV_ENC_C0_FIX | TV_ENC_SDP_FIX;
tv_filter_ctl = TV_AUTO_SCALE;
if (mode->HDisplay > 1024)
@ -801,22 +850,122 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
}
static const DisplayModeRec reported_modes[] = {
{
.name = "NTSC 480i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 1024,
.HSyncStart = 1048,
.HSyncEnd = 1184,
.HTotal = 1344,
{
.name = "NTSC 480i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 1280,
.HSyncStart = 1368,
.HSyncEnd = 1496,
.HTotal = 1712,
.VDisplay = 768,
.VSyncStart = 771,
.VSyncEnd = 777,
.VTotal = 806,
.VDisplay = 1024,
.VSyncStart = 1027,
.VSyncEnd = 1034,
.VTotal = 1104,
.type = M_T_DRIVER
},
{
.name = "NTSC 480i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 1024,
.HSyncStart = 1080,
.HSyncEnd = 1184,
.HTotal = 1344,
.type = M_T_DRIVER
}
.VDisplay = 768,
.VSyncStart = 771,
.VSyncEnd = 777,
.VTotal = 806,
.type = M_T_DRIVER
},
{
.name = "NTSC 480i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 800,
.HSyncStart = 832,
.HSyncEnd = 912,
.HTotal = 1024,
.VDisplay = 600,
.VSyncStart = 603,
.VSyncEnd = 607,
.VTotal = 650,
.type = M_T_DRIVER
},
{
.name = "NTSC 480i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 640,
.HSyncStart = 664,
.HSyncEnd = 720,
.HTotal = 800,
.VDisplay = 480,
.VSyncStart = 483,
.VSyncEnd = 487,
.VTotal = 552,
.type = M_T_DRIVER
},
{
.name = "PAL 576i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 1280,
.HSyncStart = 1352,
.HSyncEnd = 1480,
.HTotal = 1680,
.VDisplay = 1024,
.VSyncStart = 1027,
.VSyncEnd = 1034,
.VTotal = 1092,
.type = M_T_DRIVER
},
{
.name = "PAL 576i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 1024,
.HSyncStart = 1072,
.HSyncEnd = 1168,
.HTotal = 1312,
.VDisplay = 768,
.VSyncStart = 771,
.VSyncEnd = 775,
.VTotal = 820,
.VRefresh = 50.0f,
.type = M_T_DRIVER
},
{
.name = "PAL 576i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 800,
.HSyncStart = 832,
.HSyncEnd = 904,
.HTotal = 1008,
.VDisplay = 600,
.VSyncStart = 603,
.VSyncEnd = 607,
.VTotal = 642,
.VRefresh = 50.0f,
.type = M_T_DRIVER
},
{
.name = "PAL 576i",
.Clock = TV_PLL_CLOCK,
.HDisplay = 640,
.HSyncStart = 664,
.HSyncEnd = 720,
.HTotal = 800,
.VDisplay = 480,
.VSyncStart = 483,
.VSyncEnd = 487,
.VTotal = 516,
.VRefresh = 50.0f,
.type = M_T_DRIVER
},
};
/**
@ -917,7 +1066,6 @@ i830_tv_detect(xf86OutputPtr output)
/* we only need the pixel clock set correctly here */
mode = reported_modes[0];
xf86SetModeCrtc (&mode, INTERLACE_HALVE_V);
i830PipeSetMode (crtc, &mode, FALSE);
}
i830_tv_detect_type (crtc, output);
i830ReleaseLoadDetectPipe (output);

1108
src/i965_exa_render.c Normal file
View File

File diff suppressed because it is too large Load Diff

17
src/rotation_sf0.g4a Normal file
View File

@ -0,0 +1,17 @@
send (1) 0 g6<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
send (1) 0 g6.4<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
mov (8) m1<1>F g7<0,1,0>F { align1 };
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
mov (8) m3<1>F g3<8,8,1>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

17
src/rotation_sf90.g4a Normal file
View File

@ -0,0 +1,17 @@
send (1) 0 g6<1>F g1.20<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
send (1) 0 g6.4<1>F g1.12<0,1,0>F math inv scalar mlen 1 rlen 1 { align1 };
add (8) g7<1>F g4<8,8,1>F -g3<8,8,1>F { align1 };
mul (1) g7<1>F g7<0,1,0>F g6<0,1,0>F { align1 };
mul (1) g7.4<1>F g7.4<0,1,0>F g6.4<0,1,0>F { align1 };
mov (8) m1<1>F g7<0,1,0>F { align1 };
mov (8) m2<1>F g7.4<0,1,0>F { align1 };
mov (8) m3<1>F g3<8,8,1>F { align1 };
send (8) 0 null g0<8,8,1>F urb 0 transpose used complete mlen 4 rlen 0 { align1 EOT };
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

17
src/rotation_sf_prog0.h Normal file
View File

@ -0,0 +1,17 @@
{ 0x00000031, 0x20c01fbd, 0x0000002c, 0x01110081 },
{ 0x00000031, 0x20c41fbd, 0x00000034, 0x01110081 },
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

17
src/rotation_sf_prog90.h Normal file
View File

@ -0,0 +1,17 @@
{ 0x00000031, 0x20c01fbd, 0x00000034, 0x01110081 },
{ 0x00000031, 0x20c41fbd, 0x0000002c, 0x01110081 },
{ 0x00600040, 0x20e077bd, 0x008d0080, 0x008d4060 },
{ 0x00000041, 0x20e077bd, 0x000000e0, 0x000000c0 },
{ 0x00000041, 0x20e477bd, 0x000000e4, 0x000000c4 },
{ 0x00600001, 0x202003be, 0x000000e0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x000000e4, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0060, 0x00000000 },
{ 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

123
src/rotation_wm0.g4a Normal file
View File

@ -0,0 +1,123 @@
/* The initial payload of the thread is always g0.
* WM_URB (incoming URB entries) is g3
* X0_R is g4
* X1_R is g5
* Y0_R is g6
* Y1_R is g7
*/
/* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
* subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
* subspan are given in GRF register 1.2 through 1.5 (which, with the word
* addressing below, are 1.4 through 1.11).
*
* The result is WM_X*_R and WM_Y*R being:
*
* X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
* Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
* X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
* Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
*/
/* Set up ss0.x coordinates*/
mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.4<1>F g1.8<0,1,0>UW 1UB { align1 };
mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.12<1>F g1.8<0,1,0>UW 1UB { align1 };
/* Set up ss0.y coordinates */
mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
add (1) g6.8<1>F g1.10<0,1,0>UW 1UB { align1 };
add (1) g6.12<1>F g1.10<0,1,0>UW 1UB { align1 };
/* set up ss1.x coordinates */
mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.20<1>F g1.12<0,1,0>UW 1UB { align1 };
mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.28<1>F g1.12<0,1,0>UW 1UB { align1 };
/* set up ss1.y coordinates */
mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
add (1) g6.24<1>F g1.14<0,1,0>UW 1UB { align1 };
add (1) g6.28<1>F g1.14<0,1,0>UW 1UB { align1 };
/* Set up ss2.x coordinates */
mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.4<1>F g1.16<0,1,0>UW 1UB { align1 };
mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.12<1>F g1.16<0,1,0>UW 1UB { align1 };
/* Set up ss2.y coordinates */
mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
add (1) g7.8<1>F g1.18<0,1,0>UW 1UB { align1 };
add (1) g7.12<1>F g1.18<0,1,0>UW 1UB { align1 };
/* Set up ss3.x coordinates */
mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.20<1>F g1.20<0,1,0>UW 1UB { align1 };
mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.28<1>F g1.20<0,1,0>UW 1UB { align1 };
/* Set up ss3.y coordinates */
mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
add (1) g7.24<1>F g1.22<0,1,0>UW 1UB { align1 };
add (1) g7.28<1>F g1.22<0,1,0>UW 1UB { align1 };
/* Now, map these screen space coordinates into texture coordinates. */
/* subtract screen-space X origin of vertex 0. */
add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
mul (8) g4<1>F g4<8,8,1>F g3<0,1,0>F { align1 };
mul (8) g5<1>F g5<8,8,1>F g3<0,1,0>F { align1 };
/* add in texture X offset */
add (8) g4<1>F g4<8,8,1>F g3.12<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F g3.12<0,1,0>F { align1 };
/* subtract screen-space Y origin of vertex 0. */
add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
/* scale by texture Y increment */
/* XXX: double check the fields in Cx,Cy,Co and attributes*/
mul (8) g6<1>F g6<8,8,1>F g3.20<0,1,0>F { align1 };
mul (8) g7<1>F g7<8,8,1>F g3.20<0,1,0>F { align1 };
/* add in texture Y offset */
add (8) g6<1>F g6<8,8,1>F g3.28<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F g3.28<0,1,0>F { align1 };
/* sampler */
mov (8) m1<1>F g4<8,8,1>F { align1 };
mov (8) m2<1>F g5<8,8,1>F { align1 };
mov (8) m3<1>F g6<8,8,1>F { align1 };
mov (8) m4<1>F g7<8,8,1>F { align1 };
/*
* g0 holds the PS thread payload, which (oddly) contains
* precisely what the sampler wants to see in m0
*/
send (16) 0 g12<1>UW g0<8,8,1>UW sampler (1,0,F) mlen 5 rlen 8 { align1 };
mov (8) g19<1>UD g19<8,8,1>UD { align1 };
mov (8) m2<1>F g12<8,8,1>F { align1 };
mov (8) m3<1>F g14<8,8,1>F { align1 };
mov (8) m4<1>F g16<8,8,1>F { align1 };
mov (8) m5<1>F g18<8,8,1>F { align1 };
mov (8) m6<1>F g13<8,8,1>F { align1 };
mov (8) m7<1>F g15<8,8,1>F { align1 };
mov (8) m8<1>F g17<8,8,1>F { align1 };
mov (8) m9<1>F g19<8,8,1>F { align1 };
/* Pass through control information:
*/
mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
/* Send framebuffer write message: XXX: acc0? */
send (16) 0 acc0<1>UW g0<8,8,1>UW write (
0, /* binding table index 0 */
8, /* pixel scoreboard clear */
4, /* render target write */
0 /* no write commit message */
) mlen 10 rlen 0 { align1 EOT };
/* padding */
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

127
src/rotation_wm90.g4a Normal file
View File

@ -0,0 +1,127 @@
/* The initial payload of the thread is always g0.
* WM_URB (incoming URB entries) is g3
* X0_R is g4
* X1_R is g5
* Y0_R is g6
* Y1_R is g7
*/
/* Set up the X/Y screen coordinates of the pixels in our 4 subspans. Each
* subspan is a 2x2 rectangle, and the screen x/y of the upper left of each
* subspan are given in GRF register 1.2 through 1.5 (which, with the word
* addressing below, are 1.4 through 1.11).
*
* The result is WM_X*_R and WM_Y*R being:
*
* X0: {ss0.x, ss0.x+1, ss0.x, ss0.x+1, ss1.x, ss1.x+1, ss1.x, ss1.x+y}
* Y0: {ss0.y, ss0.y, ss0.y+1, ss0.y+1, ss1.y, ss1.y, ss1.y+1, ss1.y+1}
* X1: {ss2.x, ss2.x+1, ss2.x, ss2.x+1, ss3.x, ss3.x+1, ss3.x, ss3.x+y}
* Y1: {ss2.y, ss2.y, ss2.y+1, ss2.y+1, ss3.y, ss3.y, ss3.y+1, ss3.y+1}
*/
/* Set up ss0.x coordinates*/
mov (1) g4<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.4<1>F g1.8<0,1,0>UW 1UB { align1 };
mov (1) g4.8<1>F g1.8<0,1,0>UW { align1 };
add (1) g4.12<1>F g1.8<0,1,0>UW 1UB { align1 };
/* Set up ss0.y coordinates */
mov (1) g6<1>F g1.10<0,1,0>UW { align1 };
mov (1) g6.4<1>F g1.10<0,1,0>UW { align1 };
add (1) g6.8<1>F g1.10<0,1,0>UW 1UB { align1 };
add (1) g6.12<1>F g1.10<0,1,0>UW 1UB { align1 };
/* set up ss1.x coordinates */
mov (1) g4.16<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.20<1>F g1.12<0,1,0>UW 1UB { align1 };
mov (1) g4.24<1>F g1.12<0,1,0>UW { align1 };
add (1) g4.28<1>F g1.12<0,1,0>UW 1UB { align1 };
/* set up ss1.y coordinates */
mov (1) g6.16<1>F g1.14<0,1,0>UW { align1 };
mov (1) g6.20<1>F g1.14<0,1,0>UW { align1 };
add (1) g6.24<1>F g1.14<0,1,0>UW 1UB { align1 };
add (1) g6.28<1>F g1.14<0,1,0>UW 1UB { align1 };
/* Set up ss2.x coordinates */
mov (1) g5<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.4<1>F g1.16<0,1,0>UW 1UB { align1 };
mov (1) g5.8<1>F g1.16<0,1,0>UW { align1 };
add (1) g5.12<1>F g1.16<0,1,0>UW 1UB { align1 };
/* Set up ss2.y coordinates */
mov (1) g7<1>F g1.18<0,1,0>UW { align1 };
mov (1) g7.4<1>F g1.18<0,1,0>UW { align1 };
add (1) g7.8<1>F g1.18<0,1,0>UW 1UB { align1 };
add (1) g7.12<1>F g1.18<0,1,0>UW 1UB { align1 };
/* Set up ss3.x coordinates */
mov (1) g5.16<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.20<1>F g1.20<0,1,0>UW 1UB { align1 };
mov (1) g5.24<1>F g1.20<0,1,0>UW { align1 };
add (1) g5.28<1>F g1.20<0,1,0>UW 1UB { align1 };
/* Set up ss3.y coordinates */
mov (1) g7.16<1>F g1.22<0,1,0>UW { align1 };
mov (1) g7.20<1>F g1.22<0,1,0>UW { align1 };
add (1) g7.24<1>F g1.22<0,1,0>UW 1UB { align1 };
add (1) g7.28<1>F g1.22<0,1,0>UW 1UB { align1 };
/* Now, map these screen space coordinates into texture coordinates. */
/* XXX: convert it to calculate (u,v) in 90 and 270 case */
/* subtract screen-space Y origin of vertex 0. */
add (8) g6<1>F g6<8,8,1>F -g1.4<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F -g1.4<0,1,0>F { align1 };
/* (Yp - Ystart) * Cx */
mul (8) g6<1>F g6<8,8,1>F g3<0,1,0>F { align1 };
mul (8) g7<1>F g7<8,8,1>F g3<0,1,0>F { align1 };
/* scale by texture Y increment */
add (8) g6<1>F g6<8,8,1>F g3.12<0,1,0>F { align1 };
add (8) g7<1>F g7<8,8,1>F g3.12<0,1,0>F { align1 };
/* subtract screen-space X origin of vertex 0. */
add (8) g4<1>F g4<8,8,1>F -g1<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F -g1<0,1,0>F { align1 };
/* scale by texture X increment */
mul (8) g4<1>F g4<8,8,1>F g3.20<0,1,0>F { align1 };
mul (8) g5<1>F g5<8,8,1>F g3.20<0,1,0>F { align1 };
/* add in texture X offset */
add (8) g4<1>F g4<8,8,1>F g3.28<0,1,0>F { align1 };
add (8) g5<1>F g5<8,8,1>F g3.28<0,1,0>F { align1 };
/* sampler */
mov (8) m1<1>F g6<8,8,1>F { align1 };
mov (8) m2<1>F g7<8,8,1>F { align1 };
mov (8) m3<1>F g4<8,8,1>F { align1 };
mov (8) m4<1>F g5<8,8,1>F { align1 };
/*
* g0 holds the PS thread payload, which (oddly) contains
* precisely what the sampler wants to see in m0
*/
send (16) 0 g12<1>UW g0<8,8,1>UW sampler (1,0,F) mlen 5 rlen 8 { align1 };
mov (8) g19<1>UD g19<8,8,1>UD { align1 };
mov (8) m2<1>F g12<8,8,1>F { align1 };
mov (8) m3<1>F g14<8,8,1>F { align1 };
mov (8) m4<1>F g16<8,8,1>F { align1 };
mov (8) m5<1>F g18<8,8,1>F { align1 };
mov (8) m6<1>F g13<8,8,1>F { align1 };
mov (8) m7<1>F g15<8,8,1>F { align1 };
mov (8) m8<1>F g17<8,8,1>F { align1 };
mov (8) m9<1>F g19<8,8,1>F { align1 };
/* Pass through control information:
*/
mov (8) m1<1>UD g1<8,8,1>UD { align1 mask_disable };
/* Send framebuffer write message: XXX: acc0? */
send (16) 0 acc0<1>UW g0<8,8,1>UW write (
0, /* binding table index 0 */
8, /* pixel scoreboard clear */
4, /* render target write */
0 /* no write commit message */
) mlen 10 rlen 0 { align1 EOT };
/* padding */
nop;
nop;
nop;
nop;
nop;
nop;
nop;
nop;

68
src/rotation_wm_prog0.h Normal file
View File

@ -0,0 +1,68 @@
{ 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
{ 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
{ 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
{ 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
{ 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
{ 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
{ 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
{ 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
{ 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
{ 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
{ 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
{ 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
{ 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
{ 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
{ 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
{ 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
{ 0x00600041, 0x208077bd, 0x008d0080, 0x00000060 },
{ 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000060 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x0000006c },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000006c },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
{ 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000074 },
{ 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000074 },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000007c },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000007c },
{ 0x00600001, 0x202003be, 0x008d0080, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d00a0, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d00c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d00e0, 0x00000000 },
{ 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
{ 0x00600001, 0x22600021, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d0180, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d01c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
{ 0x00600001, 0x20a003be, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x20c003be, 0x008d01a0, 0x00000000 },
{ 0x00600001, 0x20e003be, 0x008d01e0, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0220, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d0260, 0x00000000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },

68
src/rotation_wm_prog90.h Normal file
View File

@ -0,0 +1,68 @@
{ 0x00000001, 0x2080013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x20840d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x2088013d, 0x00000028, 0x00000000 },
{ 0x00000040, 0x208c0d3d, 0x00000028, 0x00000001 },
{ 0x00000001, 0x20c0013d, 0x0000002a, 0x00000000 },
{ 0x00000001, 0x20c4013d, 0x0000002a, 0x00000000 },
{ 0x00000040, 0x20c80d3d, 0x0000002a, 0x00000001 },
{ 0x00000040, 0x20cc0d3d, 0x0000002a, 0x00000001 },
{ 0x00000001, 0x2090013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x20940d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x2098013d, 0x0000002c, 0x00000000 },
{ 0x00000040, 0x209c0d3d, 0x0000002c, 0x00000001 },
{ 0x00000001, 0x20d0013d, 0x0000002e, 0x00000000 },
{ 0x00000001, 0x20d4013d, 0x0000002e, 0x00000000 },
{ 0x00000040, 0x20d80d3d, 0x0000002e, 0x00000001 },
{ 0x00000040, 0x20dc0d3d, 0x0000002e, 0x00000001 },
{ 0x00000001, 0x20a0013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20a40d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20a8013d, 0x00000030, 0x00000000 },
{ 0x00000040, 0x20ac0d3d, 0x00000030, 0x00000001 },
{ 0x00000001, 0x20e0013d, 0x00000032, 0x00000000 },
{ 0x00000001, 0x20e4013d, 0x00000032, 0x00000000 },
{ 0x00000040, 0x20e80d3d, 0x00000032, 0x00000001 },
{ 0x00000040, 0x20ec0d3d, 0x00000032, 0x00000001 },
{ 0x00000001, 0x20b0013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20b40d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20b8013d, 0x00000034, 0x00000000 },
{ 0x00000040, 0x20bc0d3d, 0x00000034, 0x00000001 },
{ 0x00000001, 0x20f0013d, 0x00000036, 0x00000000 },
{ 0x00000001, 0x20f4013d, 0x00000036, 0x00000000 },
{ 0x00000040, 0x20f80d3d, 0x00000036, 0x00000001 },
{ 0x00000040, 0x20fc0d3d, 0x00000036, 0x00000001 },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x00004024 },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x00004024 },
{ 0x00600041, 0x20c077bd, 0x008d00c0, 0x00000060 },
{ 0x00600041, 0x20e077bd, 0x008d00e0, 0x00000060 },
{ 0x00600040, 0x20c077bd, 0x008d00c0, 0x0000006c },
{ 0x00600040, 0x20e077bd, 0x008d00e0, 0x0000006c },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x00004020 },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x00004020 },
{ 0x00600041, 0x208077bd, 0x008d0080, 0x00000074 },
{ 0x00600041, 0x20a077bd, 0x008d00a0, 0x00000074 },
{ 0x00600040, 0x208077bd, 0x008d0080, 0x0000007c },
{ 0x00600040, 0x20a077bd, 0x008d00a0, 0x0000007c },
{ 0x00600001, 0x202003be, 0x008d00c0, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d00e0, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d0080, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d00a0, 0x00000000 },
{ 0x00800031, 0x21801d29, 0x008d0000, 0x02580001 },
{ 0x00600001, 0x22600021, 0x008d0260, 0x00000000 },
{ 0x00600001, 0x204003be, 0x008d0180, 0x00000000 },
{ 0x00600001, 0x206003be, 0x008d01c0, 0x00000000 },
{ 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
{ 0x00600001, 0x20a003be, 0x008d0240, 0x00000000 },
{ 0x00600001, 0x20c003be, 0x008d01a0, 0x00000000 },
{ 0x00600001, 0x20e003be, 0x008d01e0, 0x00000000 },
{ 0x00600001, 0x210003be, 0x008d0220, 0x00000000 },
{ 0x00600001, 0x212003be, 0x008d0260, 0x00000000 },
{ 0x00600201, 0x20200022, 0x008d0020, 0x00000000 },
{ 0x00800031, 0x24001d28, 0x008d0000, 0x85a04800 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },
{ 0x0000007e, 0x00000000, 0x00000000, 0x00000000 },