Use batch_start_atomic to fix batchbuffer wrapping problems with 8xx render.
Bug #22483.
This commit is contained in:
Eric Anholt
parent
e386e7b14b
commit
a1e6abb5ca
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@ -468,6 +468,14 @@ typedef struct _I830Rec {
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/** Transform pointers for src/mask, or NULL if identity */
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PictTransform *transform[2];
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float coord_adjust;
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/* i830 render accel state */
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PixmapPtr render_src, render_mask, render_dst;
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PicturePtr render_src_picture, render_mask_picture, render_dst_picture;
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uint32_t render_dst_format;
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Bool needs_render_state_emit;
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uint32_t cblend, ablend, s8_blendctl;
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/* i915 render accel state */
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uint32_t mapstate[6];
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uint32_t samplerstate[6];
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@ -790,6 +798,7 @@ Bool i915_prepare_composite(int op, PicturePtr pSrc, PicturePtr pMask,
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void i915_composite(PixmapPtr pDst, int srcX, int srcY,
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int maskX, int maskY, int dstX, int dstY, int w, int h);
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void i915_batch_flush_notify(ScrnInfoPtr pScrn);
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void i830_batch_flush_notify(ScrnInfoPtr scrn);
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/* i965_render.c */
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unsigned int gen4_render_state_size(ScrnInfoPtr pScrn);
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void gen4_render_state_init(ScrnInfoPtr pScrn);
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@ -2757,7 +2757,7 @@ I830ScreenInit(int scrnIndex, ScreenPtr pScreen, int argc, char **argv)
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else if (IS_I9XX(pI830))
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pI830->batch_flush_notify = i915_batch_flush_notify;
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else
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pI830->batch_flush_notify = NULL;
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pI830->batch_flush_notify = i830_batch_flush_notify;
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miInitializeBackingStore(pScreen);
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xf86SetBackingStore(pScreen);
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@ -255,7 +255,7 @@ i8xx_get_card_format(PicturePtr pPict)
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FatalError("Unsupported format type %d\n", pPict->format);
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}
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static Bool
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static void
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i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
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{
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@ -299,7 +299,7 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
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break;
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default:
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filter = 0;
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I830FALLBACK("Bad filter 0x%x\n", pPict->filter);
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FatalError("Bad filter 0x%x\n", pPict->filter);
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}
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filter |= (MIPFILTER_NONE << TM0S3_MIP_FILTER_SHIFT);
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@ -344,10 +344,6 @@ i830_texture_setup(PicturePtr pPict, PixmapPtr pPix, int unit)
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TEX_STREAM_MAP_IDX(unit));
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ADVANCE_BATCH();
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}
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i830_debug_sync(pScrn);
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return TRUE;
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}
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Bool
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@ -391,29 +387,27 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
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{
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ScrnInfoPtr pScrn = xf86Screens[pSrcPicture->pDrawable->pScreen->myNum];
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I830Ptr pI830 = I830PTR(pScrn);
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uint32_t dst_format, dst_pitch;
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Bool is_affine_src, is_affine_mask;
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Bool is_nearest = FALSE;
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pI830->render_src_picture = pSrcPicture;
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pI830->render_src = pSrc;
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pI830->render_mask_picture = pMaskPicture;
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pI830->render_mask = pMask;
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pI830->render_dst_picture = pDstPicture;
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pI830->render_dst = pDst;
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i830_exa_check_pitch_3d(pSrc);
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if (pMask)
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i830_exa_check_pitch_3d(pMask);
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i830_exa_check_pitch_3d(pDst);
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IntelEmitInvarientState(pScrn);
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pI830->last_3d = LAST_3D_RENDER;
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if (!i830_get_dest_format(pDstPicture, &dst_format))
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if (!i830_get_dest_format(pDstPicture, &pI830->render_dst_format))
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return FALSE;
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dst_pitch = intel_get_pixmap_pitch(pDst);
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if (!i830_texture_setup(pSrcPicture, pSrc, 0))
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I830FALLBACK("fail to setup src texture\n");
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if (pSrcPicture->filter == PictFilterNearest)
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is_nearest = TRUE;
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if (pMask != NULL) {
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if (!i830_texture_setup(pMaskPicture, pMask, 1))
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I830FALLBACK("fail to setup mask texture\n");
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if (pMaskPicture->filter == PictFilterNearest)
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is_nearest = TRUE;
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} else {
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@ -434,45 +428,7 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
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I830FALLBACK("non-affine transform unsupported on 8xx hardware\n");
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{
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uint32_t cblend, ablend, blendctl, vf2;
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BEGIN_BATCH(30);
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/* color buffer */
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OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
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OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
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BUF_3D_PITCH(dst_pitch));
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OUT_RELOC_PIXMAP(pDst, I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP);
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OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
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OUT_BATCH(dst_format);
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/* defaults */
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OUT_BATCH(_3DSTATE_DFLT_Z_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_DFLT_DIFFUSE_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_DFLT_SPEC_CMD);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
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OUT_BATCH(0);
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OUT_BATCH(0); /* ymin, xmin */
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OUT_BATCH(DRAW_YMAX(pDst->drawable.height - 1) |
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DRAW_XMAX(pDst->drawable.width - 1));
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OUT_BATCH(0); /* yorig, xorig */
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(2) |
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I1_LOAD_S(3) | 1);
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if (pMask)
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vf2 = 2 << 12; /* 2 texture coord sets */
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else
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vf2 = 1 << 12;
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OUT_BATCH(vf2); /* TEXCOORDFMT_2D */
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OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
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uint32_t cblend, ablend, blendctl;
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/* If component alpha is active in the mask and the blend operation
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* uses the source alpha, then we know we don't need the source
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@ -541,36 +497,90 @@ i830_prepare_composite(int op, PicturePtr pSrcPicture,
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ablend |= TB0A_ARG2_SEL_ONE;
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}
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
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LOAD_TEXTURE_BLEND_STAGE(0)|1);
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OUT_BATCH(cblend);
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OUT_BATCH(ablend);
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OUT_BATCH(0);
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blendctl = i830_get_blend_cntl(op, pMaskPicture, pDstPicture->format);
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OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
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OUT_BATCH(MI_NOOP);
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
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OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | blendctl |
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S8_ENABLE_COLOR_BUFFER_WRITE);
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OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
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DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
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DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
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ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
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/* We have to explicitly say we don't want write disabled */
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OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
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DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
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DISABLE_DITHER | ENABLE_COLOR_WRITE |
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DISABLE_DEPTH_WRITE);
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ADVANCE_BATCH();
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pI830->cblend = cblend;
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pI830->ablend = ablend;
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pI830->s8_blendctl = blendctl;
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}
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i830_debug_sync(pScrn);
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pI830->needs_render_state_emit = TRUE;
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return TRUE;
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}
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static void
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i830_emit_composite_state(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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uint32_t vf2;
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pI830->needs_render_state_emit = FALSE;
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IntelEmitInvarientState(pScrn);
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pI830->last_3d = LAST_3D_RENDER;
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BEGIN_BATCH(24);
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OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
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OUT_BATCH(BUF_3D_ID_COLOR_BACK| BUF_3D_USE_FENCE |
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BUF_3D_PITCH(intel_get_pixmap_pitch(pI830->render_dst)));
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OUT_RELOC_PIXMAP(pI830->render_dst,
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I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, 0);
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OUT_BATCH(MI_NOOP);
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OUT_BATCH(_3DSTATE_DST_BUF_VARS_CMD);
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OUT_BATCH(pI830->render_dst_format);
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OUT_BATCH(_3DSTATE_DRAW_RECT_CMD);
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OUT_BATCH(0);
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OUT_BATCH(0); /* ymin, xmin */
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OUT_BATCH(DRAW_YMAX(pI830->render_dst->drawable.height - 1) |
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DRAW_XMAX(pI830->render_dst->drawable.width - 1));
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OUT_BATCH(0); /* yorig, xorig */
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 |
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I1_LOAD_S(2) |
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I1_LOAD_S(3) | 1);
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if (pI830->render_mask)
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vf2 = 2 << 12; /* 2 texture coord sets */
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else
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vf2 = 1 << 12;
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OUT_BATCH(vf2); /* TEXCOORDFMT_2D */
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OUT_BATCH(S3_CULLMODE_NONE | S3_VERTEXHAS_XY);
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OUT_BATCH(_3DSTATE_INDPT_ALPHA_BLEND_CMD | DISABLE_INDPT_ALPHA_BLEND);
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OUT_BATCH(MI_NOOP);
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_1 | I1_LOAD_S(8) | 0);
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OUT_BATCH(S8_ENABLE_COLOR_BLEND | S8_BLENDFUNC_ADD | pI830->s8_blendctl |
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S8_ENABLE_COLOR_BUFFER_WRITE);
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OUT_BATCH(_3DSTATE_LOAD_STATE_IMMEDIATE_2 |
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LOAD_TEXTURE_BLEND_STAGE(0)|1);
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OUT_BATCH(pI830->cblend);
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OUT_BATCH(pI830->ablend);
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OUT_BATCH(0);
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OUT_BATCH(_3DSTATE_ENABLES_1_CMD | DISABLE_LOGIC_OP |
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DISABLE_STENCIL_TEST | DISABLE_DEPTH_BIAS |
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DISABLE_SPEC_ADD | DISABLE_FOG | DISABLE_ALPHA_TEST |
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ENABLE_COLOR_BLEND | DISABLE_DEPTH_TEST);
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/* We have to explicitly say we don't want write disabled */
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OUT_BATCH(_3DSTATE_ENABLES_2_CMD | ENABLE_COLOR_MASK |
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DISABLE_STENCIL_WRITE | ENABLE_TEX_CACHE |
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DISABLE_DITHER | ENABLE_COLOR_WRITE |
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DISABLE_DEPTH_WRITE);
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ADVANCE_BATCH();
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i830_texture_setup(pI830->render_src_picture, pI830->render_src, 0);
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if (pI830->render_mask) {
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i830_texture_setup(pI830->render_mask_picture,
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pI830->render_mask, 1);
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}
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}
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/**
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* Do a single rectangle composite operation.
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*
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@ -582,7 +592,6 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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{
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ScrnInfoPtr pScrn = xf86Screens[pDst->drawable.pScreen->myNum];
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I830Ptr pI830 = I830PTR(pScrn);
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Bool has_mask;
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Bool is_affine_src, is_affine_mask;
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int per_vertex, num_floats;
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float src_x[3], src_y[3], src_w[3], mask_x[3], mask_y[3], mask_w[3];
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@ -590,12 +599,6 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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is_affine_src = i830_transform_is_affine (pI830->transform[0]);
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is_affine_mask = i830_transform_is_affine (pI830->transform[1]);
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if (pI830->scale_units[1][0] == -1 || pI830->scale_units[1][1] == -1) {
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has_mask = FALSE;
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} else {
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has_mask = TRUE;
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}
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per_vertex = 2; /* dest x/y */
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if (is_affine_src)
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{
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@ -630,7 +633,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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return;
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per_vertex += 4; /* src x/y/z/w */
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}
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if (has_mask) {
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if (pI830->render_mask) {
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if (is_affine_mask) {
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if (!i830_get_transformed_coordinates(maskX, maskY,
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pI830->transform[1],
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@ -666,6 +669,16 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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}
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num_floats = 3 * per_vertex;
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intel_batch_start_atomic(pScrn,
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58 + /* invarient */
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24 + /* setup */
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20 + /* 2 * setup_texture */
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6 + num_floats /* verts */);
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if (pI830->needs_render_state_emit)
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i830_emit_composite_state(pScrn);
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BEGIN_BATCH(6 + num_floats);
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OUT_BATCH(MI_NOOP);
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@ -683,7 +696,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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OUT_BATCH_F(0.0);
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OUT_BATCH_F(src_w[2]);
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}
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if (has_mask) {
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if (pI830->render_mask) {
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OUT_BATCH_F(mask_x[2] / pI830->scale_units[1][0]);
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OUT_BATCH_F(mask_y[2] / pI830->scale_units[1][1]);
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if (!is_affine_mask) {
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@ -700,7 +713,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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OUT_BATCH_F(0.0);
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OUT_BATCH_F(src_w[1]);
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}
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if (has_mask) {
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if (pI830->render_mask) {
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OUT_BATCH_F(mask_x[1] / pI830->scale_units[1][0]);
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OUT_BATCH_F(mask_y[1] / pI830->scale_units[1][1]);
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if (!is_affine_mask) {
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@ -717,7 +730,7 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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OUT_BATCH_F(0.0);
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OUT_BATCH_F(src_w[0]);
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}
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if (has_mask) {
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if (pI830->render_mask) {
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OUT_BATCH_F(mask_x[0] / pI830->scale_units[1][0]);
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OUT_BATCH_F(mask_y[0] / pI830->scale_units[1][1]);
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if (!is_affine_mask) {
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@ -727,4 +740,16 @@ i830_composite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
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}
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ADVANCE_BATCH();
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intel_batch_end_atomic(pScrn);
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i830_debug_sync(pScrn);
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}
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void
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i830_batch_flush_notify(ScrnInfoPtr scrn)
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{
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I830Ptr i830 = I830PTR(scrn);
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i830->needs_render_state_emit = TRUE;
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}
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