From a47ba68996f117fabcb601d35bcc5f99cbcd6122 Mon Sep 17 00:00:00 2001 From: Gwenole Beauchesne Date: Fri, 4 May 2012 17:17:22 +0200 Subject: [PATCH] uxa: fix max PS threads shift value for Haswell The maximum number of threads is now a 9-bit value. Thus, one more bit towards LSB was re-used. i.e. bit position is now 23 instead of 24 on Ivy Bridge. Signed-off-by: Gwenole Beauchesne Reviewed-by: Kenneth Graunke --- src/i965_reg.h | 3 ++- src/i965_render.c | 7 ++++++- src/i965_video.c | 7 ++++++- 3 files changed, 14 insertions(+), 3 deletions(-) diff --git a/src/i965_reg.h b/src/i965_reg.h index e7b0d15d..45b6d082 100644 --- a/src/i965_reg.h +++ b/src/i965_reg.h @@ -219,7 +219,8 @@ # define GEN7_PS_FLOATING_POINT_MODE_ALT (1 << 16) /* DW3: scratch space */ /* DW4 */ -# define GEN7_PS_MAX_THREADS_SHIFT 24 +# define GEN7_PS_MAX_THREADS_SHIFT_IVB 24 +# define GEN7_PS_MAX_THREADS_SHIFT_HSW 23 # define GEN7_PS_PUSH_CONSTANT_ENABLE (1 << 11) # define GEN7_PS_ATTRIBUTE_ENABLE (1 << 10) # define GEN7_PS_OMASK_TO_RENDER_TARGET (1 << 9) diff --git a/src/i965_render.c b/src/i965_render.c index 2182df81..30fef572 100644 --- a/src/i965_render.c +++ b/src/i965_render.c @@ -2687,6 +2687,11 @@ gen7_composite_wm_state(intel_screen_private *intel, drm_intel_bo *bo) { int num_surfaces = has_mask ? 3 : 2; + unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB; + + if (IS_HSW(intel)) { + max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW; + } if (intel->gen6_render_state.kernel == bo) return; @@ -2703,7 +2708,7 @@ gen7_composite_wm_state(intel_screen_private *intel, OUT_BATCH((1 << GEN7_PS_SAMPLER_COUNT_SHIFT) | (num_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT)); OUT_BATCH(0); /* scratch space base offset */ - OUT_BATCH(((48 - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + OUT_BATCH(((48 - 1) << max_threads_shift) | GEN7_PS_ATTRIBUTE_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); OUT_BATCH((6 << GEN7_PS_DISPATCH_START_GRF_SHIFT_0)); diff --git a/src/i965_video.c b/src/i965_video.c index bcd60636..bba282dd 100644 --- a/src/i965_video.c +++ b/src/i965_video.c @@ -1625,6 +1625,11 @@ static void gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed) { intel_screen_private *intel = intel_get_screen_private(scrn); + unsigned int max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_IVB; + + if (IS_HSW(intel)) { + max_threads_shift = GEN7_PS_MAX_THREADS_SHIFT_HSW; + } /* disable WM constant buffer */ OUT_BATCH(GEN6_3DSTATE_CONSTANT_PS | (7 - 2)); @@ -1658,7 +1663,7 @@ gen7_upload_wm_state(ScrnInfoPtr scrn, Bool is_packed) OUT_BATCH(0); /* scratch space base offset */ OUT_BATCH( - ((48 - 1) << GEN7_PS_MAX_THREADS_SHIFT) | + ((48 - 1) << max_threads_shift) | GEN7_PS_ATTRIBUTE_ENABLE | GEN7_PS_16_DISPATCH_ENABLE); OUT_BATCH(