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Merge branch 'modesetting' into modesetting-rotation 

Conflicts:

	src/i830_driver.c
	src/i830_randr.c

Just a few sync changes.
This commit is contained in:
Keith Packard 2007-01-16 12:20:26 +11:00
parent 37946c9c8a 45696aa291
commit a52df90ffc
10 changed files with 125 additions and 93 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

7
man/i810.man
View File

@ -84,9 +84,12 @@ This allows the user to change the amount of graphics memory used for
2D acceleration and video. Decreasing this amount leaves more for 3D
textures. Increasing it can improve 2D performance at the expense of
3D performance.
.TP
This option only takes effect when XAA acceleration is enabled.
.TP
Default: depends on the resolution, depth, and available video memory. The
driver attempts to allocate at least enough to hold two DVD-sized YUV buffers
by default. The default used for a specific configuration can be found
driver attempts to allocate space for at 3 screenfuls of pixmaps plus an
HD-sized XV video. The default used for a specific configuration can be found
by examining the __xservername__ log file.
.TP
.BI "Option \*qDRI\*q \*q" boolean \*q

4
src/common.h
View File

@ -339,10 +339,6 @@ extern int I810_DEBUG;
#define I810_CURSOR_X 64
#define I810_CURSOR_Y I810_CURSOR_X
/* XXX Need to check if these are reasonable. */
#define MAX_DISPLAY_PITCH 2048
#define MAX_DISPLAY_HEIGHT 2048
#define PIPE_NAME(n) ('A' + (n))
#endif /* _INTEL_COMMON_H_ */

21
src/i830_driver.c
View File

@ -1139,14 +1139,13 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
/* Allocate an xf86CrtcConfig */
xf86CrtcConfigInit (pScrn);
xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
if (IS_I965G(pI830))
{
max_width = 16384;
max_height = 4096;
}
else
{
/* See i830_exa.c comments for why we limit the framebuffer size like this.
*/
if (IS_I965G(pI830)) {
max_width = 8192;
max_height = 8192;
} else {
max_width = 2048;
max_height = 2048;
}
@ -3016,11 +3015,7 @@ i830AdjustFrame(int scrnIndex, int x, int y, int flags)
if (crtc && crtc->enabled)
{
/* Sync the engine before adjust frame */
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
/* XXX should have xf86-based frame adjuster */
i830WaitSync(pScrn);
i830PipeSetBase(crtc, output->initial_x + x, output->initial_y + y);
crtc->x = output->initial_x + x;
crtc->y = output->initial_y + y;

69
src/i830_exa.c
View File

@ -345,9 +345,9 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
int vertex_count;
if (pMask)
vertex_count = 4*6;
vertex_count = 3*6;
else
vertex_count = 4*4;
vertex_count = 3*4;
BEGIN_LP_RING(6+vertex_count);
@ -357,7 +357,7 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
OUT_RING(PRIM3D_INLINE | PRIM3D_TRIFAN | (vertex_count-1));
OUT_RING(PRIM3D_INLINE | PRIM3D_RECTLIST | (vertex_count-1));
OUT_RING_F(dstX);
OUT_RING_F(dstY);
@ -385,15 +385,6 @@ IntelEXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING_F(maskXend / pI830->scale_units[1][0]);
OUT_RING_F(maskYend / pI830->scale_units[1][1]);
}
OUT_RING_F(dstX + w);
OUT_RING_F(dstY);
OUT_RING_F(srcXend / pI830->scale_units[0][0]);
OUT_RING_F(srcY / pI830->scale_units[0][1]);
if (pMask) {
OUT_RING_F(maskXend / pI830->scale_units[1][0]);
OUT_RING_F(maskY / pI830->scale_units[1][1]);
}
ADVANCE_LP_RING();
}
}
@ -447,13 +438,53 @@ I830EXAInit(ScreenPtr pScreen)
/* disable Xv here... */
}
/* i915 3D requires 16 byte alignment (4k if tiled) */
pI830->EXADriverPtr->pixmapOffsetAlign = 256;
pI830->EXADriverPtr->pixmapPitchAlign = 64;
/* i845 and i945 2D limits rendering to 65536 lines and pitch of 32768. */
pI830->EXADriverPtr->maxX = 4095;
pI830->EXADriverPtr->maxY = 4095;
/* Limits are described in the BLT engine chapter under Graphics Data Size
* Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,
* 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.
*
* i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.
*
* i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.
* i965 limits 3D surface to 4kB-aligned offset if tiled.
* i965 limits 3D surfaces to w,h of ?,8192.
* i965 limits 3D surface to pitch of 1B - 128kB.
* i965 limits 3D surface pitch alignment to 512B, only if tiled.
* i965 limits 3D destination drawing rect to w,h of 8192,8192.
*
* i915 limits 3D textures to 4B-aligned offset if un-tiled.
* i915 limits 3D textures to ~4kB-aligned offset if tiled.
* i915 limits 3D textures to width,height of 2048,2048.
* i915 limits 3D textures to pitch of 16B - 8kB, in dwords.
* i915 limits 3D destination to ~4kB-aligned offset if tiled.
* i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.
* i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.
* i915 limits 3D destination to POT aligned pitch if tiled.
* i915 limits 3D destination drawing rect to w,h of 2048,2048.
*
* i845 limits 3D textures to 4B-aligned offset if un-tiled.
* i845 limits 3D textures to ~4kB-aligned offset if tiled.
* i845 limits 3D textures to width,height of 2048,2048.
* i845 limits 3D textures to pitch of 4B - 8kB, in dwords.
* i845 limits 3D destination to 4B-aligned offset if un-tiled.
* i845 limits 3D destination to ~4kB-aligned offset if tiled.
* i845 limits 3D destination to pitch of 8B - 8kB, in dwords.
* i845 limits 3D destination drawing rect to w,h of 2048,2048.
*
* For the tiled issues, the only tiled buffer we draw to should be
* the front, which will have an appropriate pitch/offset already set up,
* so EXA doesn't need to worry.
*/
if (IS_I965G(pI830)) {
pI830->EXADriverPtr->pixmapOffsetAlign = 4 * 2;
pI830->EXADriverPtr->pixmapPitchAlign = 1;
pI830->EXADriverPtr->maxX = 8192;
pI830->EXADriverPtr->maxY = 8192;
} else {
pI830->EXADriverPtr->pixmapOffsetAlign = 4;
pI830->EXADriverPtr->pixmapPitchAlign = 16;
pI830->EXADriverPtr->maxX = 2048;
pI830->EXADriverPtr->maxY = 2048;
}
/* Sync */
pI830->EXADriverPtr->WaitMarker = I830EXASync;

35
src/i830_memory.c
View File

@ -637,6 +637,13 @@ GetFreeSpace(ScrnInfoPtr pScrn)
return extra;
}
/* This is the 2D rendering vertical coordinate limit. We can ignore
* the 3D rendering limits in our 2d pixmap cache allocation, because XAA
* doesn't do any 3D rendering to/from the cache lines when using an offset
* at the start of framebuffer.
*/
#define MAX_2D_HEIGHT 65536
/**
* Allocates a framebuffer for a screen.
*
@ -698,25 +705,19 @@ I830AllocateFramebuffer(ScrnInfoPtr pScrn, I830Ptr pI830, BoxPtr FbMemBox,
"maxCacheLines < 0 in I830Allocate2DMemory()\n");
maxCacheLines = 0;
}
if (maxCacheLines > (MAX_DISPLAY_HEIGHT - pScrn->virtualY))
maxCacheLines = MAX_DISPLAY_HEIGHT - pScrn->virtualY;
if (maxCacheLines > (MAX_2D_HEIGHT - pScrn->virtualY))
maxCacheLines = MAX_2D_HEIGHT - pScrn->virtualY;
if (pI830->CacheLines >= 0) {
cacheLines = pI830->CacheLines;
} else {
#if 1
/* Make sure there is enough for two DVD sized YUV buffers */
cacheLines = (pScrn->depth == 24) ? 256 : 384;
if (pScrn->displayWidth <= 1024)
cacheLines *= 2;
#else
/*
* Make sure there is enough for two DVD sized YUV buffers.
* Make that 1.5MB, which is around what was allocated with
* the old algorithm
*/
cacheLines = (MB(1) + KB(512)) / pI830->cpp / pScrn->displayWidth;
#endif
int size;
size = 3 * lineSize * pScrn->virtualY;
size += 1920 * 1088 * 2 * 2;
size = ROUND_TO_PAGE(size);
cacheLines = (size + lineSize - 1) / lineSize;
}
if (cacheLines > maxCacheLines)
cacheLines = maxCacheLines;
@ -902,8 +903,8 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
maxFb = pI830->FrontBuffer.Size + extra;
lineSize = pScrn->displayWidth * pI830->cpp;
maxFb = ROUND_DOWN_TO(maxFb, lineSize);
if (maxFb > lineSize * MAX_DISPLAY_HEIGHT)
maxFb = lineSize * MAX_DISPLAY_HEIGHT;
if (maxFb > lineSize * MAX_2D_HEIGHT)
maxFb = lineSize * MAX_2D_HEIGHT;
if (0/*maxFb > pI830->FrontBuffer.Size*/) {
unsigned long oldsize;
/*

11
src/i830_rotate.c
View File

@ -805,10 +805,7 @@ I965UpdateRotate (ScreenPtr pScreen,
/* Since we use the same little vertex buffer over and over, sync for
* subsequent rectangles.
*/
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
}
pbox++;
@ -895,12 +892,10 @@ I965UpdateRotate (ScreenPtr pScreen,
ADVANCE_LP_RING();
first_output = FALSE;
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
i830MarkSync(pScrn);
}
if (pI830->AccelInfoRec)
(*pI830->AccelInfoRec->Sync)(pScrn);
i830WaitSync(pScrn);
#ifdef XF86DRI
if (didLock)
I830DRIUnlock(pScrn1);

53
src/i830_video.c
View File

@ -128,6 +128,19 @@ I830FreeMemory(ScrnInfoPtr pScrn, struct linear_alloc *linear);
static Atom xvBrightness, xvContrast, xvSaturation, xvColorKey, xvPipe, xvDoubleBuffer;
static Atom xvGamma0, xvGamma1, xvGamma2, xvGamma3, xvGamma4, xvGamma5;
/* Limits for the overlay/textured video source sizes. The documented hardware
* limits are 2048x2048 or better for overlay and both of our textured video
* implementations. However, we run into the bigrequests limit of (currently)
* 4MB, which even the planar format's 2048*2048*1.5 bytes is larger than.
* Conveniently, the HD resolution, even in packed format, takes
* (1920*1088*2) bytes, which is just shy of 4MB. Additionally, on the 830
* and 845, larger sizes resulted in the card hanging, so we keep the limits
* lower there.
*
* While the HD resolution is actually 1920x1080, we increase our advertised
* size to 1088 because some software wants to send an image aligned to
* 16-pixel boundaries.
*/
#define IMAGE_MAX_WIDTH 1920
#define IMAGE_MAX_HEIGHT 1088
#define IMAGE_MAX_WIDTH_LEGACY 1024
@ -777,7 +790,6 @@ static XF86VideoAdaptorPtr
I830SetupImageVideoTextured(ScreenPtr pScreen)
{
XF86VideoAdaptorPtr adapt;
XF86VideoEncodingPtr encoding;
XF86AttributePtr attrs;
I830PortPrivPtr portPrivs;
DevUnion *devUnions;
@ -791,15 +803,13 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
adapt = xcalloc(1, sizeof(XF86VideoAdaptorRec));
portPrivs = xcalloc(nports, sizeof(I830PortPrivRec));
devUnions = xcalloc(nports, sizeof(DevUnion));
encoding = xcalloc(1, sizeof(XF86VideoEncodingRec));
attrs = xcalloc(nAttributes, sizeof(XF86AttributeRec));
if (adapt == NULL || portPrivs == NULL || devUnions == NULL ||
encoding == NULL || attrs == NULL)
attrs == NULL)
{
xfree(adapt);
xfree(portPrivs);
xfree(devUnions);
xfree(encoding);
xfree(attrs);
return NULL;
}
@ -808,13 +818,7 @@ I830SetupImageVideoTextured(ScreenPtr pScreen)
adapt->flags = 0;
adapt->name = "Intel(R) Textured Video";
adapt->nEncodings = 1;
adapt->pEncodings = encoding;
adapt->pEncodings[0].id = 0;
adapt->pEncodings[0].name = "XV_IMAGE";
adapt->pEncodings[0].width = 2048;
adapt->pEncodings[0].height = 2048;
adapt->pEncodings[0].rate.numerator = 1;
adapt->pEncodings[0].rate.denominator = 1;
adapt->pEncodings = DummyEncoding;
adapt->nFormats = NUM_FORMATS;
adapt->pFormats = Formats;
adapt->nPorts = nports;
@ -2358,10 +2362,7 @@ I830PutImage(ScrnInfoPtr pScrn,
* acceleration to finish before writing the new video data into
* framebuffer.
*/
if (pI830->AccelInfoRec && pI830->AccelInfoRec->NeedToSync) {
(*pI830->AccelInfoRec->Sync)(pScrn);
pI830->AccelInfoRec->NeedToSync = FALSE;
}
i830WaitSync(pScrn);
}
switch (id) {
@ -2449,18 +2450,16 @@ I830QueryImageAttributes(ScrnInfoPtr pScrn,
ErrorF("I830QueryImageAttributes: w is %d, h is %d\n", *w, *h);
#endif
if (!textured) {
if (IS_845G(pI830) || IS_I830(pI830)) {
if (*w > IMAGE_MAX_WIDTH_LEGACY)
*w = IMAGE_MAX_WIDTH_LEGACY;
if (*h > IMAGE_MAX_HEIGHT_LEGACY)
*h = IMAGE_MAX_HEIGHT_LEGACY;
} else {
if (*w > IMAGE_MAX_WIDTH)
*w = IMAGE_MAX_WIDTH;
if (*h > IMAGE_MAX_HEIGHT)
*h = IMAGE_MAX_HEIGHT;
}
if (IS_845G(pI830) || IS_I830(pI830)) {
if (*w > IMAGE_MAX_WIDTH_LEGACY)
*w = IMAGE_MAX_WIDTH_LEGACY;
if (*h > IMAGE_MAX_HEIGHT_LEGACY)
*h = IMAGE_MAX_HEIGHT_LEGACY;
} else {
if (*w > IMAGE_MAX_WIDTH)
*w = IMAGE_MAX_WIDTH;
if (*h > IMAGE_MAX_HEIGHT)
*h = IMAGE_MAX_HEIGHT;
}
*w = (*w + 1) & ~1;

3
src/i915_video.c
View File

@ -433,7 +433,6 @@ I915DisplayVideoTextured(ScrnInfoPtr pScrn, I830PortPrivPtr pPriv, int id,
ADVANCE_LP_RING();
}
if (pI830->AccelInfoRec)
pI830->AccelInfoRec->NeedToSync = TRUE;
i830MarkSync(pScrn);
}

13
src/i965_exa_render.c
View File

@ -404,6 +404,9 @@ I965EXAPrepareComposite(int op, PicturePtr pSrcPicture,
binding_table_entries = 2; /* default no mask */
/* Wait for sync before we start setting up our new state */
i830WaitSync(pScrn);
/* Set up our layout of state in framebuffer. First the general state: */
next_offset = 0;
vs_offset = ALIGN(next_offset, 64);
@ -1024,6 +1027,11 @@ I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
"dstX %d, dstY %d\n", srcX, srcY, srcXend, srcYend,
maskX, maskY, maskXend, maskYend, dstX, dstY);
/* Wait for any existing composite rectangles to land before we overwrite
* the VB with the next one.
*/
i830WaitSync(pScrn);
i = 0;
/* rect (x2,y2) */
vb[i++] = (float)(srcXend) / pI830->scale_units[0][0];
@ -1088,4 +1096,9 @@ I965EXAComposite(PixmapPtr pDst, int srcX, int srcY, int maskX, int maskY,
OUT_RING(0); /* Immediate data high DW */
ADVANCE_LP_RING();
}
/* Mark sync so we can wait for it before setting up the VB on the next
* rectangle.
*/
i830MarkSync(pScrn);
}

2
src/ivch/ivch.c
View File

@ -92,7 +92,7 @@ ivch_init(I2CBusPtr b, I2CSlaveAddr addr)
xf86DrvMsg(b->scrnIndex, X_INFO, "detecting ivch\n");
priv = xcalloc(1, sizeof(struct ivch_priv));
if (priv = NULL)
if (priv == NULL)
return NULL;
priv->d.DevName = "i82807aa \"ivch\" LVDS/CMOS panel controller";