snb: Emit more invariants only once
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
e8f41c3710
commit
a58e5a1bdf
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@ -2175,10 +2175,8 @@ gen6_composite_create_depth_stencil_state(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_invarient_states(ScrnInfoPtr scrn)
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gen6_composite_invariant_states(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(NEW_PIPELINE_SELECT | PIPELINE_SELECT_3D);
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OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
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@ -2195,10 +2193,8 @@ gen6_composite_invarient_states(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_state_base_address(ScrnInfoPtr scrn)
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gen6_composite_state_base_address(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(BRW_STATE_BASE_ADDRESS | (10 - 2));
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OUT_BATCH(BASE_ADDRESS_MODIFY); /* General state base address */
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intel->surface_reloc = intel->batch_used;
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@ -2214,9 +2210,9 @@ gen6_composite_state_base_address(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_viewport_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *cc_vp_bo)
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gen6_composite_viewport_state_pointers(intel_screen_private *intel,
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drm_intel_bo *cc_vp_bo)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(GEN6_3DSTATE_VIEWPORT_STATE_POINTERS |
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GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC |
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@ -2227,10 +2223,8 @@ gen6_composite_viewport_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *cc_vp_bo)
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}
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static void
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gen6_composite_urb(ScrnInfoPtr scrn)
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gen6_composite_urb(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(GEN6_3DSTATE_URB | (3 - 2));
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OUT_BATCH(((1 - 1) << GEN6_3DSTATE_URB_VS_SIZE_SHIFT) |
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(24 << GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT)); /* at least 24 on GEN6 */
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@ -2239,16 +2233,14 @@ gen6_composite_urb(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_cc_state_pointers(ScrnInfoPtr scrn,
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drm_intel_bo *blend_state_bo,
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uint32_t blend_state_offset,
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drm_intel_bo *depth_stencil_state_bo,
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uint32_t depth_stencil_state_offset,
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drm_intel_bo *cc_state_bo,
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uint32_t cc_state_offset)
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gen6_composite_cc_state_pointers(intel_screen_private *intel,
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drm_intel_bo *blend_state_bo,
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uint32_t blend_state_offset,
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drm_intel_bo *depth_stencil_state_bo,
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uint32_t depth_stencil_state_offset,
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drm_intel_bo *cc_state_bo,
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uint32_t cc_state_offset)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(GEN6_3DSTATE_CC_STATE_POINTERS | (4 - 2));
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OUT_RELOC(blend_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, blend_state_offset | 1);
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OUT_RELOC(depth_stencil_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, depth_stencil_state_offset | 1);
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@ -2256,10 +2248,9 @@ gen6_composite_cc_state_pointers(ScrnInfoPtr scrn,
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}
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static void
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gen6_composite_sampler_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *ps_sampler_state_bo)
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gen6_composite_sampler_state_pointers(intel_screen_private *intel,
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drm_intel_bo *ps_sampler_state_bo)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(GEN6_3DSTATE_SAMPLER_STATE_POINTERS |
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GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS |
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(4 - 2));
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@ -2268,18 +2259,16 @@ gen6_composite_sampler_state_pointers(ScrnInfoPtr scrn, drm_intel_bo *ps_sampler
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OUT_RELOC(ps_sampler_state_bo, I915_GEM_DOMAIN_INSTRUCTION, 0, 0);
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}
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static void
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gen6_composite_vs_state(ScrnInfoPtr scrn)
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static void
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gen6_composite_vs_state(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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/* disable VS constant buffer */
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_VS | (5 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_VS | (6 - 2));
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OUT_BATCH(0); /* without VS kernel */
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OUT_BATCH(0);
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@ -2288,18 +2277,16 @@ gen6_composite_vs_state(ScrnInfoPtr scrn)
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OUT_BATCH(0); /* pass-through */
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}
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static void
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gen6_composite_gs_state(ScrnInfoPtr scrn)
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static void
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gen6_composite_gs_state(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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/* disable GS constant buffer */
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OUT_BATCH(GEN6_3DSTATE_CONSTANT_GS | (5 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(0);
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OUT_BATCH(GEN6_3DSTATE_GS | (7 - 2));
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OUT_BATCH(0); /* without GS kernel */
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OUT_BATCH(0);
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@ -2309,21 +2296,19 @@ gen6_composite_gs_state(ScrnInfoPtr scrn)
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OUT_BATCH(0); /* pass-through */
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}
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static void
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gen6_composite_clip_state(ScrnInfoPtr scrn)
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static void
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gen6_composite_clip_state(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(GEN6_3DSTATE_CLIP | (4 - 2));
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OUT_BATCH(0);
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OUT_BATCH(0); /* pass-through */
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OUT_BATCH(0);
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}
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static void
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gen6_composite_sf_state(ScrnInfoPtr scrn, Bool has_mask)
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static void
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gen6_composite_sf_state(intel_screen_private *intel,
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Bool has_mask)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int num_sf_outputs = has_mask ? 2 : 1;
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OUT_BATCH(GEN6_3DSTATE_SF | (20 - 2));
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@ -2350,10 +2335,11 @@ gen6_composite_sf_state(ScrnInfoPtr scrn, Bool has_mask)
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OUT_BATCH(0); /* DW19 */
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}
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static void
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gen6_composite_wm_state(ScrnInfoPtr scrn, Bool has_mask, drm_intel_bo *kernel_bo)
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static void
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gen6_composite_wm_state(intel_screen_private *intel,
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Bool has_mask,
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drm_intel_bo *kernel_bo)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int num_surfaces = has_mask ? 3 : 2;
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int num_sf_outputs = has_mask ? 2 : 1;
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@ -2373,19 +2359,17 @@ gen6_composite_wm_state(ScrnInfoPtr scrn, Bool has_mask, drm_intel_bo *kernel_bo
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OUT_BATCH(0);
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OUT_BATCH((6 << GEN6_3DSTATE_WM_DISPATCH_START_GRF_0_SHIFT)); /* DW4 */
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OUT_BATCH(((40 - 1) << GEN6_3DSTATE_WM_MAX_THREADS_SHIFT) |
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GEN6_3DSTATE_WM_DISPATCH_ENABLE |
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GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
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GEN6_3DSTATE_WM_DISPATCH_ENABLE |
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GEN6_3DSTATE_WM_16_DISPATCH_ENABLE);
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OUT_BATCH((num_sf_outputs << GEN6_3DSTATE_WM_NUM_SF_OUTPUTS_SHIFT) |
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GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
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GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC);
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OUT_BATCH(0);
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OUT_BATCH(0);
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}
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static void
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gen6_composite_binding_table_pointers(ScrnInfoPtr scrn)
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gen6_composite_binding_table_pointers(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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/* Binding table pointers */
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OUT_BATCH(BRW_3DSTATE_BINDING_TABLE_POINTERS |
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GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
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@ -2397,10 +2381,8 @@ gen6_composite_binding_table_pointers(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_depth_buffer_state(ScrnInfoPtr scrn)
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gen6_composite_depth_buffer_state(intel_screen_private *intel)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(BRW_3DSTATE_DEPTH_BUFFER | (7 - 2));
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OUT_BATCH((BRW_SURFACE_NULL << BRW_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT) |
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(BRW_DEPTHFORMAT_D32_FLOAT << BRW_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT));
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@ -2415,10 +2397,9 @@ gen6_composite_depth_buffer_state(ScrnInfoPtr scrn)
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}
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static void
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gen6_composite_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr dest)
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gen6_composite_drawing_rectangle(intel_screen_private *intel,
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PixmapPtr dest)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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OUT_BATCH(BRW_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
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OUT_BATCH(0x00000000); /* ymin, xmin */
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OUT_BATCH(DRAW_YMAX(dest->drawable.height - 1) | DRAW_XMAX(dest->drawable.width - 1)); /* ymax, xmax */
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@ -2426,9 +2407,10 @@ gen6_composite_drawing_rectangle(ScrnInfoPtr scrn, PixmapPtr dest)
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}
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static void
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gen6_composite_vertex_element_state(ScrnInfoPtr scrn, Bool has_mask, Bool is_affine)
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gen6_composite_vertex_element_state(intel_screen_private *intel,
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Bool has_mask,
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Bool is_affine)
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{
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intel_screen_private *intel = intel_get_screen_private(scrn);
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/*
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* vertex data in vertex buffer
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* position: (x, y)
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@ -2521,37 +2503,45 @@ gen6_emit_composite_state(ScrnInfoPtr scrn)
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drm_intel_bo *ps_sampler_state_bo = render_state->ps_sampler_state_bo[src_filter][src_extend][mask_filter][mask_extend];
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intel->needs_render_state_emit = FALSE;
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IntelEmitInvarientState(scrn);
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intel->last_3d = LAST_3D_RENDER;
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if (intel->needs_3d_invariant) {
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gen6_composite_invariant_states(intel);
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gen6_composite_viewport_state_pointers(intel,
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render_state->cc_vp_bo);
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gen6_composite_urb(intel);
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gen6_composite_vs_state(intel);
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gen6_composite_gs_state(intel);
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gen6_composite_clip_state(intel);
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gen6_composite_depth_buffer_state(intel);
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intel->needs_3d_invariant = FALSE;
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}
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i965_get_blend_cntl(op,
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mask_picture,
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dest_picture->format,
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&src_blend,
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&dst_blend);
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assert(intel->in_batch_atomic);
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gen6_composite_invarient_states(scrn);
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if (intel->surface_reloc == 0)
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gen6_composite_state_base_address(scrn);
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gen6_composite_viewport_state_pointers(scrn, render_state->cc_vp_bo);
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gen6_composite_urb(scrn);
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gen6_composite_cc_state_pointers(scrn,
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gen6_composite_state_base_address(intel);
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gen6_composite_cc_state_pointers(intel,
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render_state->gen6_blend_bo,
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((src_blend * BRW_BLENDFACTOR_COUNT) + dst_blend) * GEN6_BLEND_STATE_PADDED_SIZE,
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render_state->gen6_depth_stencil_bo,
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0,
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render_state->cc_state_bo,
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0);
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gen6_composite_sampler_state_pointers(scrn, ps_sampler_state_bo);
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gen6_composite_vs_state(scrn);
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gen6_composite_gs_state(scrn);
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gen6_composite_clip_state(scrn);
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gen6_composite_sf_state(scrn, mask != 0);
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gen6_composite_wm_state(scrn, mask != 0, render_state->wm_kernel_bo[composite_op->wm_kernel]);
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gen6_composite_binding_table_pointers(scrn);
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gen6_composite_depth_buffer_state(scrn);
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gen6_composite_drawing_rectangle(scrn, dest);
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gen6_composite_vertex_element_state(scrn, mask != 0, is_affine);
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gen6_composite_sampler_state_pointers(intel, ps_sampler_state_bo);
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gen6_composite_sf_state(intel, mask != 0);
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gen6_composite_wm_state(intel,
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mask != 0,
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render_state->wm_kernel_bo[composite_op->wm_kernel]);
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gen6_composite_binding_table_pointers(intel);
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gen6_composite_drawing_rectangle(intel, dest);
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gen6_composite_vertex_element_state(intel, mask != 0, is_affine);
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}
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static void
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