i915 render: use tiling bits where possible
This is in preparation to explicit fence allocation with execbuf2. Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
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@ -275,7 +275,7 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
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intel_screen_private *intel = intel_get_screen_private(scrn);
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uint32_t format, pitch, filter;
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int w, h, i;
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uint32_t wrap_mode;
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uint32_t wrap_mode, tiling_bits;
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pitch = intel_get_pixmap_pitch(pixmap);
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w = picture->pDrawable->width;
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@ -328,10 +328,18 @@ static Bool i915_texture_setup(PicturePtr picture, PixmapPtr pixmap, int unit)
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}
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/* offset filled in at emit time */
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if (i830_pixmap_tiled(pixmap)) {
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tiling_bits = MS3_TILED_SURFACE;
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if (i830_get_pixmap_intel(pixmap)->tiling
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== I915_TILING_Y)
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tiling_bits |= MS3_TILE_WALK;
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} else
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tiling_bits = 0;
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intel->texture[unit] = pixmap;
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intel->mapstate[unit * 3 + 0] = 0;
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intel->mapstate[unit * 3 + 1] = format |
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MS3_USE_FENCE_REGS |
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tiling_bits |
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((pixmap->drawable.height - 1) << MS3_HEIGHT_SHIFT) |
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((pixmap->drawable.width - 1) << MS3_WIDTH_SHIFT);
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intel->mapstate[unit * 3 + 2] = ((pitch / 4) - 1) << MS4_PITCH_SHIFT;
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@ -482,7 +490,7 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
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PixmapPtr mask = intel->render_mask;
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PixmapPtr dest = intel->render_dest;
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uint32_t dst_format = intel->i915_render_state.dst_format, dst_pitch;
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uint32_t blendctl;
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uint32_t blendctl, tiling_bits;
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Bool is_affine_src, is_affine_mask;
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Bool is_solid_src, is_solid_mask;
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int tex_count, t;
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@ -540,8 +548,16 @@ static void i915_emit_composite_setup(ScrnInfoPtr scrn)
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OUT_BATCH (intel->render_mask_solid);
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}
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if (i830_pixmap_tiled(dest)) {
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tiling_bits = BUF_3D_TILED_SURFACE;
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if (i830_get_pixmap_intel(dest)->tiling
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== I915_TILING_Y)
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tiling_bits |= BUF_3D_TILE_WALK_Y;
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} else
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tiling_bits = 0;
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OUT_BATCH(_3DSTATE_BUF_INFO_CMD);
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OUT_BATCH(BUF_3D_ID_COLOR_BACK | BUF_3D_USE_FENCE |
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OUT_BATCH(BUF_3D_ID_COLOR_BACK | tiling_bits |
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BUF_3D_PITCH(dst_pitch));
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OUT_RELOC_PIXMAP(dest, I915_GEM_DOMAIN_RENDER,
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I915_GEM_DOMAIN_RENDER, 0);
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