Replace i830WaitSync with just I830Sync(), as nearly all callers had it wrong.
People were trying to BEGIN_BATCH()/ADVANCE_BATCH() then i830WaitSync on the results, which wouldn't necessarily wait and lead to various painful bugs, since only EXA called MarkSync and only for certain rendering operations.
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@ -440,7 +440,6 @@ typedef struct _I830Rec {
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uxa_driver_t *uxa_driver;
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Bool need_flush;
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Bool need_sync;
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PixmapPtr pSrcPixmap;
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int accel_pixmap_pitch_alignment;
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int accel_pixmap_offset_alignment;
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@ -758,9 +757,6 @@ void i830_hdmi_init(ScrnInfoPtr pScrn, int output_reg);
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/* i830_lvds.c */
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void i830_lvds_init(ScrnInfoPtr pScrn);
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extern void i830MarkSync(ScrnInfoPtr pScrn);
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extern void i830WaitSync(ScrnInfoPtr pScrn);
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/* i830_memory.c */
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Bool i830_bind_all_memory(ScrnInfoPtr pScrn);
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Bool i830_unbind_all_memory(ScrnInfoPtr pScrn);
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@ -1266,8 +1266,10 @@ i830_crtc_dpms(xf86CrtcPtr crtc, int mode)
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static Bool
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i830_crtc_lock (xf86CrtcPtr crtc)
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{
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/* Sync the engine before mode switch */
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i830WaitSync(crtc->scrn);
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/* Sync the engine before mode switch, to finish any outstanding
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* WAIT_FOR_EVENTS that may rely on CRTC state.
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*/
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I830Sync(crtc->scrn);
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return FALSE;
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}
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@ -1935,7 +1935,6 @@ i830_refresh_ring(ScrnInfoPtr pScrn)
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pI830->ring.space = pI830->ring.head - (pI830->ring.tail + 8);
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if (pI830->ring.space < 0)
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pI830->ring.space += pI830->ring.mem->size;
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i830MarkSync(pScrn);
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}
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enum pipe {
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@ -3050,7 +3049,7 @@ i830AdjustFrame(int scrnIndex, int x, int y, int flags)
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if (crtc && crtc->enabled)
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{
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/* Sync the engine before adjust frame */
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i830WaitSync(pScrn);
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I830Sync(pScrn);
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i830PipeSetBase(crtc, crtc->desiredX + x, crtc->desiredY + y);
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crtc->x = output->initial_x + x;
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crtc->y = output->initial_y + y;
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@ -3453,26 +3452,6 @@ i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe)
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return NULL;
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}
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void
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i830WaitSync(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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if (pI830->uxa_driver && pI830->need_sync) {
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pI830->need_sync = FALSE;
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I830Sync(pScrn);
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}
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}
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void
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i830MarkSync(ScrnInfoPtr pScrn)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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if (pI830->uxa_driver)
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pI830->need_sync = TRUE;
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}
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void
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I830InitpScrn(ScrnInfoPtr pScrn)
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{
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@ -492,11 +492,6 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
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I830Ptr i830 = I830PTR(scrn);
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intel_batch_flush(scrn, FALSE);
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/* XXX: dri_bo_map should handle syncing for us, what's the deal? */
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if (i830->need_sync) {
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I830Sync(scrn);
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i830->need_sync = FALSE;
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}
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/* No VT sema or GEM? No GTT mapping. */
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if (!scrn->vtSema || !i830->memory_manager) {
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@ -1368,10 +1368,7 @@ i830_set_tiling(ScrnInfoPtr pScrn, unsigned int offset,
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assert(tile_format != TILE_NONE);
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if (pI830->need_sync) {
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I830Sync(pScrn);
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pI830->need_sync = FALSE;
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}
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I830Sync(pScrn);
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if (IS_I965G(pI830))
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max_fence = FENCE_NEW_NR;
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@ -461,7 +461,7 @@ i830_overlay_on(ScrnInfoPtr pScrn)
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OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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i830WaitSync(pScrn);
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I830Sync(pScrn);
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/*
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* If we turned pipe A on up above, turn it
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@ -514,7 +514,7 @@ i830_overlay_off(ScrnInfoPtr pScrn)
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/*
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* Wait for overlay to go idle. This has to be
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* separated from the turning off state by a WaitSync
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* separated from the turning off state by a Sync
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* to ensure the overlay will not read OCMD early and
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* disable the overlay before the commands here are
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* executed
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@ -524,7 +524,7 @@ i830_overlay_off(ScrnInfoPtr pScrn)
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OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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i830WaitSync(pScrn);
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I830Sync(pScrn);
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}
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/*
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@ -545,7 +545,7 @@ i830_overlay_off(ScrnInfoPtr pScrn)
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OUT_BATCH(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
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OUT_BATCH(MI_NOOP);
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ADVANCE_BATCH();
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i830WaitSync(pScrn);
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I830Sync(pScrn);
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}
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pI830->overlayOn = FALSE;
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OVERLAY_DEBUG("overlay_off\n");
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