intel: Source our PCI IDs table from the copy in the kernel
Rather than duplicating the information we already use in the kernel, we can reuse the pci-id tables so long as we apply a little fuzz. Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
bb8484da48
commit
b6bcb7ae20
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@ -41,6 +41,7 @@ endif
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NULL:=#
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intel_drv_la_SOURCES = \
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i915_pciids.h \
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intel_list.h \
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intel_options.h \
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intel_device.c \
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@ -0,0 +1,211 @@
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/*
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* Copyright 2013 Intel Corporation
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef _I915_PCIIDS_H
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#define _I915_PCIIDS_H
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/*
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* A pci_device_id struct {
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* __u32 vendor, device;
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* __u32 subvendor, subdevice;
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* __u32 class, class_mask;
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* kernel_ulong_t driver_data;
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* };
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* Don't use C99 here because "class" is reserved and we want to
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* give userspace flexibility.
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*/
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#define INTEL_VGA_DEVICE(id, info) { \
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0x8086, id, \
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~0, ~0, \
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0x030000, 0xff0000, \
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(unsigned long) info }
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#define INTEL_QUANTA_VGA_DEVICE(info) { \
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0x8086, 0x16a, \
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0x152d, 0x8990, \
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0x030000, 0xff0000, \
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(unsigned long) info }
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#define INTEL_I830_IDS(info) \
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INTEL_VGA_DEVICE(0x3577, info)
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#define INTEL_I845G_IDS(info) \
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INTEL_VGA_DEVICE(0x2562, info)
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#define INTEL_I85X_IDS(info) \
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INTEL_VGA_DEVICE(0x3582, info), /* I855_GM */ \
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INTEL_VGA_DEVICE(0x358e, info)
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#define INTEL_I865G_IDS(info) \
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INTEL_VGA_DEVICE(0x2572, info) /* I865_G */
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#define INTEL_I915G_IDS(info) \
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INTEL_VGA_DEVICE(0x2582, info), /* I915_G */ \
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INTEL_VGA_DEVICE(0x258a, info) /* E7221_G */
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#define INTEL_I915GM_IDS(info) \
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INTEL_VGA_DEVICE(0x2592, info) /* I915_GM */
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#define INTEL_I945G_IDS(info) \
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INTEL_VGA_DEVICE(0x2772, info) /* I945_G */
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#define INTEL_I945GM_IDS(info) \
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INTEL_VGA_DEVICE(0x27a2, info), /* I945_GM */ \
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INTEL_VGA_DEVICE(0x27ae, info) /* I945_GME */
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#define INTEL_I965G_IDS(info) \
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INTEL_VGA_DEVICE(0x2972, info), /* I946_GZ */ \
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INTEL_VGA_DEVICE(0x2982, info), /* G35_G */ \
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INTEL_VGA_DEVICE(0x2992, info), /* I965_Q */ \
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INTEL_VGA_DEVICE(0x29a2, info) /* I965_G */
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#define INTEL_G33_IDS(info) \
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INTEL_VGA_DEVICE(0x29b2, info), /* Q35_G */ \
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INTEL_VGA_DEVICE(0x29c2, info), /* G33_G */ \
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INTEL_VGA_DEVICE(0x29d2, info) /* Q33_G */
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#define INTEL_I965GM_IDS(info) \
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INTEL_VGA_DEVICE(0x2a02, info), /* I965_GM */ \
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INTEL_VGA_DEVICE(0x2a12, info) /* I965_GME */
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#define INTEL_GM45_IDS(info) \
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INTEL_VGA_DEVICE(0x2a42, info) /* GM45_G */
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#define INTEL_G45_IDS(info) \
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INTEL_VGA_DEVICE(0x2e02, info), /* IGD_E_G */ \
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INTEL_VGA_DEVICE(0x2e12, info), /* Q45_G */ \
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INTEL_VGA_DEVICE(0x2e22, info), /* G45_G */ \
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INTEL_VGA_DEVICE(0x2e32, info), /* G41_G */ \
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INTEL_VGA_DEVICE(0x2e42, info), /* B43_G */ \
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INTEL_VGA_DEVICE(0x2e92, info) /* B43_G.1 */
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#define INTEL_PINEVIEW_IDS(info) \
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INTEL_VGA_DEVICE(0xa001, info), \
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INTEL_VGA_DEVICE(0xa011, info)
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#define INTEL_IRONLAKE_D_IDS(info) \
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INTEL_VGA_DEVICE(0x0042, info)
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#define INTEL_IRONLAKE_M_IDS(info) \
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INTEL_VGA_DEVICE(0x0046, info)
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#define INTEL_SNB_D_IDS(info) \
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INTEL_VGA_DEVICE(0x0102, info), \
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INTEL_VGA_DEVICE(0x0112, info), \
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INTEL_VGA_DEVICE(0x0122, info), \
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INTEL_VGA_DEVICE(0x010A, info)
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#define INTEL_SNB_M_IDS(info) \
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INTEL_VGA_DEVICE(0x0106, info), \
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INTEL_VGA_DEVICE(0x0116, info), \
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INTEL_VGA_DEVICE(0x0126, info)
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#define INTEL_IVB_M_IDS(info) \
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INTEL_VGA_DEVICE(0x0156, info), /* GT1 mobile */ \
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INTEL_VGA_DEVICE(0x0166, info) /* GT2 mobile */
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#define INTEL_IVB_D_IDS(info) \
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INTEL_VGA_DEVICE(0x0152, info), /* GT1 desktop */ \
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INTEL_VGA_DEVICE(0x0162, info), /* GT2 desktop */ \
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INTEL_VGA_DEVICE(0x015a, info), /* GT1 server */ \
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INTEL_VGA_DEVICE(0x016a, info) /* GT2 server */
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#define INTEL_IVB_Q_IDS(info) \
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INTEL_QUANTA_VGA_DEVICE(info) /* Quanta transcode */
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#define INTEL_HSW_D_IDS(info) \
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INTEL_VGA_DEVICE(0x0402, info), /* GT1 desktop */ \
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INTEL_VGA_DEVICE(0x0412, info), /* GT2 desktop */ \
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INTEL_VGA_DEVICE(0x0422, info), /* GT3 desktop */ \
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INTEL_VGA_DEVICE(0x040a, info), /* GT1 server */ \
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INTEL_VGA_DEVICE(0x041a, info), /* GT2 server */ \
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INTEL_VGA_DEVICE(0x042a, info), /* GT3 server */ \
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INTEL_VGA_DEVICE(0x040B, info), /* GT1 reserved */ \
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INTEL_VGA_DEVICE(0x041B, info), /* GT2 reserved */ \
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INTEL_VGA_DEVICE(0x042B, info), /* GT3 reserved */ \
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INTEL_VGA_DEVICE(0x040E, info), /* GT1 reserved */ \
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INTEL_VGA_DEVICE(0x041E, info), /* GT2 reserved */ \
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INTEL_VGA_DEVICE(0x042E, info), /* GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0C02, info), /* SDV GT1 desktop */ \
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INTEL_VGA_DEVICE(0x0C12, info), /* SDV GT2 desktop */ \
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INTEL_VGA_DEVICE(0x0C22, info), /* SDV GT3 desktop */ \
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INTEL_VGA_DEVICE(0x0C0A, info), /* SDV GT1 server */ \
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INTEL_VGA_DEVICE(0x0C1A, info), /* SDV GT2 server */ \
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INTEL_VGA_DEVICE(0x0C2A, info), /* SDV GT3 server */ \
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INTEL_VGA_DEVICE(0x0C0B, info), /* SDV GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0C1B, info), /* SDV GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0C2B, info), /* SDV GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0C0E, info), /* SDV GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0C1E, info), /* SDV GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0C2E, info), /* SDV GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0A02, info), /* ULT GT1 desktop */ \
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INTEL_VGA_DEVICE(0x0A12, info), /* ULT GT2 desktop */ \
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INTEL_VGA_DEVICE(0x0A22, info), /* ULT GT3 desktop */ \
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INTEL_VGA_DEVICE(0x0A0A, info), /* ULT GT1 server */ \
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INTEL_VGA_DEVICE(0x0A1A, info), /* ULT GT2 server */ \
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INTEL_VGA_DEVICE(0x0A2A, info), /* ULT GT3 server */ \
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INTEL_VGA_DEVICE(0x0A0B, info), /* ULT GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0A1B, info), /* ULT GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0A2B, info), /* ULT GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0D02, info), /* CRW GT1 desktop */ \
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INTEL_VGA_DEVICE(0x0D12, info), /* CRW GT2 desktop */ \
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INTEL_VGA_DEVICE(0x0D22, info), /* CRW GT3 desktop */ \
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INTEL_VGA_DEVICE(0x0D0A, info), /* CRW GT1 server */ \
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INTEL_VGA_DEVICE(0x0D1A, info), /* CRW GT2 server */ \
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INTEL_VGA_DEVICE(0x0D2A, info), /* CRW GT3 server */ \
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INTEL_VGA_DEVICE(0x0D0B, info), /* CRW GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0D1B, info), /* CRW GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0D2B, info), /* CRW GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0D0E, info), /* CRW GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0D1E, info), /* CRW GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0D2E, info) /* CRW GT3 reserved */ \
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#define INTEL_HSW_M_IDS(info) \
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INTEL_VGA_DEVICE(0x0406, info), /* GT1 mobile */ \
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INTEL_VGA_DEVICE(0x0416, info), /* GT2 mobile */ \
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INTEL_VGA_DEVICE(0x0426, info), /* GT2 mobile */ \
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INTEL_VGA_DEVICE(0x0C06, info), /* SDV GT1 mobile */ \
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INTEL_VGA_DEVICE(0x0C16, info), /* SDV GT2 mobile */ \
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INTEL_VGA_DEVICE(0x0C26, info), /* SDV GT3 mobile */ \
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INTEL_VGA_DEVICE(0x0A06, info), /* ULT GT1 mobile */ \
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INTEL_VGA_DEVICE(0x0A16, info), /* ULT GT2 mobile */ \
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INTEL_VGA_DEVICE(0x0A26, info), /* ULT GT3 mobile */ \
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INTEL_VGA_DEVICE(0x0A0E, info), /* ULT GT1 reserved */ \
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INTEL_VGA_DEVICE(0x0A1E, info), /* ULT GT2 reserved */ \
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INTEL_VGA_DEVICE(0x0A2E, info), /* ULT GT3 reserved */ \
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INTEL_VGA_DEVICE(0x0D06, info), /* CRW GT1 mobile */ \
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INTEL_VGA_DEVICE(0x0D16, info), /* CRW GT2 mobile */ \
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INTEL_VGA_DEVICE(0x0D26, info) /* CRW GT3 mobile */
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#define INTEL_VLV_M_IDS(info) \
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INTEL_VGA_DEVICE(0x0f30, info), \
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INTEL_VGA_DEVICE(0x0f31, info), \
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INTEL_VGA_DEVICE(0x0f32, info), \
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INTEL_VGA_DEVICE(0x0f33, info), \
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INTEL_VGA_DEVICE(0x0157, info)
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#define INTEL_VLV_D_IDS(info) \
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INTEL_VGA_DEVICE(0x0155, info)
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#endif /* _I915_PCIIDS_H */
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@ -41,6 +41,8 @@
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#include "legacy/legacy.h"
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#include "sna/sna_module.h"
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#include "i915_pciids.h" /* copied from (kernel) include/drm/i915_pciids.h */
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#ifdef XSERVER_PLATFORM_BUS
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#include <xf86platformBus.h>
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#endif
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@ -219,143 +221,50 @@ static const SymTabRec intel_chipsets[] = {
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};
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#define NUM_CHIPSETS (sizeof(intel_chipsets) / sizeof(intel_chipsets[0]))
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#define INTEL_DEVICE_MATCH(d,i) \
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{ 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }
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static const struct pci_id_match intel_device_match[] = {
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#if !KMS_ONLY
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INTEL_DEVICE_MATCH (PCI_CHIP_I810, &intel_i81x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I810_DC100, &intel_i81x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I810_E, &intel_i81x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I815, &intel_i81x_info ),
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INTEL_VGA_DEVICE(PCI_CHIP_I810, &intel_i81x_info),
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INTEL_VGA_DEVICE(PCI_CHIP_I810_DC100, &intel_i81x_info),
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INTEL_VGA_DEVICE(PCI_CHIP_I810_E, &intel_i81x_info),
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INTEL_VGA_DEVICE(PCI_CHIP_I815, &intel_i81x_info),
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#endif
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#if !UMS_ONLY
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INTEL_DEVICE_MATCH (PCI_CHIP_I830_M, &intel_i830_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_845_G, &intel_i845_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I854, &intel_i855_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I855_GM, &intel_i855_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I865_G, &intel_i865_info ),
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INTEL_I830_IDS(&intel_i830_info),
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INTEL_I845G_IDS(&intel_i830_info),
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INTEL_I85X_IDS(&intel_i855_info),
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INTEL_I865G_IDS(&intel_i865_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ),
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INTEL_I915G_IDS(&intel_i915_info),
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INTEL_I915GM_IDS(&intel_i915_info),
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INTEL_I945G_IDS(&intel_i945_info),
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INTEL_I945GM_IDS(&intel_i945_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ),
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/* Another marketing win: Q35 is another g33 device not a gen4 part
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* like its G35 brethren.
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*/
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INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ),
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INTEL_G33_IDS(&intel_g33_info),
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INTEL_PINEVIEW_IDS(&intel_g33_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ),
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INTEL_I965G_IDS(&intel_i965_info),
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INTEL_I965GM_IDS(&intel_i965_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ),
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INTEL_G45_IDS(&intel_g4x_info),
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INTEL_GM45_IDS(&intel_g4x_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ),
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INTEL_IRONLAKE_D_IDS(&intel_ironlake_info),
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INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ),
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INTEL_SNB_D_IDS(&intel_sandybridge_info),
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INTEL_SNB_M_IDS(&intel_sandybridge_info),
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INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ),
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INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ),
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||||
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ),
|
||||
INTEL_IVB_D_IDS(&intel_ivybridge_info),
|
||||
INTEL_IVB_M_IDS(&intel_ivybridge_info),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_B_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_E_GT3, &intel_haswell_info ),
|
||||
INTEL_HSW_D_IDS(&intel_haswell_info),
|
||||
INTEL_HSW_M_IDS(&intel_haswell_info),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_B_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_E_GT3, &intel_haswell_info ),
|
||||
INTEL_VLV_D_IDS(&intel_valleyview_info),
|
||||
INTEL_VLV_M_IDS(&intel_valleyview_info),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_B_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_E_GT3, &intel_haswell_info ),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_B_GT3, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT1, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT2, &intel_haswell_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_E_GT3, &intel_haswell_info ),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ),
|
||||
INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ),
|
||||
|
||||
INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ),
|
||||
INTEL_VGA_DEVICE(PCI_MATCH_ANY, &intel_generic_info),
|
||||
#endif
|
||||
|
||||
{ 0, 0, 0 },
|
||||
|
|
|
|||
Loading…
Reference in New Issue