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Remove UMS support. 

At this point, the only remaining feature regressions should be the lack of
overlay support (about to land), and the need to update the XVMC code to work
in the presence of KMS.

Acked-by: Keith Packard <keithp@keithp.com> (in principle)
Acked-by: Carl Worth <cworth@cworth.org> (in principle)
This commit is contained in:
Eric Anholt 2009-09-30 16:29:53 -07:00
parent d26f4c4937
commit b9b159c498
56 changed files with 119 additions and 17938 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
man/intel.man
View File

@ -156,12 +156,6 @@ have options for selecting adaptors.
.IP .IP
Default: Textured video adaptor is preferred. Default: Textured video adaptor is preferred.
.TP .TP
.BI "Option \*qModeDebug\*q \*q" boolean \*q
Enable printing of additional debugging information about modesetting to
the server log.
.IP
Default: Disabled
.TP
.BI "Option \*qFallbackDebug\*q \*q" boolean \*q .BI "Option \*qFallbackDebug\*q \*q" boolean \*q
Enable printing of debugging information on acceleration fallbacks to the Enable printing of debugging information on acceleration fallbacks to the
server log. server log.

19
src/Makefile.am
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@ -18,7 +18,7 @@
# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN # IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
SUBDIRS = xvmc bios_reader ch7017 ch7xxx ivch sil164 tfp410 reg_dumper render_program SUBDIRS = xvmc bios_reader reg_dumper render_program
# this is obnoxious: # this is obnoxious:
# -module lets us name the module exactly how we want # -module lets us name the module exactly how we want
@ -70,35 +70,18 @@ intel_drv_la_SOURCES = \
i810_wmark.c \ i810_wmark.c \
i830_3d.c \ i830_3d.c \
i830_accel.c \ i830_accel.c \
i830_bios.c \
i830_bios.h \
i830_batchbuffer.c \ i830_batchbuffer.c \
i830_batchbuffer.h \ i830_batchbuffer.h \
i830_common.h \ i830_common.h \
i830_crt.c \
i830_cursor.c \
i830_debug.c \ i830_debug.c \
i830_debug.h \ i830_debug.h \
i830_display.c \
i830_display.h \
i830_quirks.c \
i830_driver.c \ i830_driver.c \
i830_dvo.c \
i830.h \ i830.h \
i830_hdmi.c \
i830_i2c.c \
i830_io.c \
i830_lvds.c \
i830_memory.c \ i830_memory.c \
i830_modes.c \
i830_video.c \ i830_video.c \
i830_video.h \ i830_video.h \
i830_reg.h \ i830_reg.h \
i830_ring.h \ i830_ring.h \
i830_sdvo.c \
i830_sdvo.h \
i830_sdvo_regs.h \
i830_tv.c \
i915_3d.c \ i915_3d.c \
i915_3d.h \ i915_3d.h \
i915_reg.h \ i915_reg.h \

16
src/ch7017/Makefile.am
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@ -1,16 +0,0 @@
# this is obnoxious:
# -module lets us name the module exactly how we want
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
@PCIACCESS_CFLAGS@
ch7017_la_LTLIBRARIES = ch7017.la
ch7017_la_LDFLAGS = -module -avoid-version
ch7017_ladir = @moduledir@/drivers
ch7017_la_SOURCES = \
ch7017.c \
ch7017_module.c \
ch7017_reg.h

330
src/ch7017/ch7017.c
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@ -1,330 +0,0 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdint.h>
#include <unistd.h>
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "miscstruct.h"
#include "xf86i2c.h"
#include "xf86Crtc.h"
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include "../i2c_vid.h"
#include "ch7017_reg.h"
struct ch7017_priv {
I2CDevRec d;
uint8_t save_hapi;
uint8_t save_vali;
uint8_t save_valo;
uint8_t save_ailo;
uint8_t save_lvds_pll_vco;
uint8_t save_feedback_div;
uint8_t save_lvds_control_2;
uint8_t save_outputs_enable;
uint8_t save_lvds_power_down;
uint8_t save_power_management;
};
static void
ch7017_dump_regs(I2CDevPtr d);
static void
ch7017_dpms(I2CDevPtr d, int mode);
static Bool
ch7017_read(struct ch7017_priv *priv, int addr, uint8_t *val)
{
if (!xf86I2CReadByte(&priv->d, addr, val)) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to read from %s Slave %d.\n",
priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
return FALSE;
}
return TRUE;
}
static Bool
ch7017_write(struct ch7017_priv *priv, int addr, uint8_t val)
{
if (!xf86I2CWriteByte(&priv->d, addr, val)) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to write to %s Slave %d.\n",
priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
return FALSE;
}
return TRUE;
}
/** Probes for a CH7017 on the given bus and slave address. */
static void *
ch7017_init(I2CBusPtr b, I2CSlaveAddr addr)
{
struct ch7017_priv *priv;
uint8_t val;
priv = xcalloc(1, sizeof(struct ch7017_priv));
if (priv == NULL)
return NULL;
priv->d.DevName = "CH7017/7018/7019 LVDS Controller";
priv->d.SlaveAddr = addr;
priv->d.pI2CBus = b;
priv->d.StartTimeout = b->StartTimeout;
priv->d.BitTimeout = b->BitTimeout;
priv->d.AcknTimeout = b->AcknTimeout;
priv->d.ByteTimeout = b->ByteTimeout;
priv->d.DriverPrivate.ptr = priv;
if (!xf86I2CReadByte(&priv->d, CH7017_DEVICE_ID, &val))
goto fail;
if (val != CH7017_DEVICE_ID_VALUE &&
val != CH7018_DEVICE_ID_VALUE &&
val != CH7019_DEVICE_ID_VALUE) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"ch701x not detected, got %d: from %s Slave %d.\n",
val, priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
goto fail;
}
if (!xf86I2CDevInit(&(priv->d)))
goto fail;
return priv;
fail:
xfree(priv);
return NULL;
}
static xf86OutputStatus
ch7017_detect(I2CDevPtr d)
{
return XF86OutputStatusUnknown;
}
static ModeStatus
ch7017_mode_valid(I2CDevPtr d, DisplayModePtr mode)
{
if (mode->Clock > 160000)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static void
ch7017_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
{
struct ch7017_priv *priv = d->DriverPrivate.ptr;
uint8_t lvds_pll_feedback_div, lvds_pll_vco_control;
uint8_t outputs_enable, lvds_control_2, lvds_power_down;
uint8_t horizontal_active_pixel_input;
uint8_t horizontal_active_pixel_output, vertical_active_line_output;
uint8_t active_input_line_output;
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO,
"Registers before mode setting\n");
ch7017_dump_regs(d);
/* LVDS PLL settings from page 75 of 7017-7017ds.pdf*/
if (mode->Clock < 100000) {
outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_LOW;
lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
(13 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
(2 << CH7017_LVDS_PLL_VCO_SHIFT) |
(3 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
lvds_control_2 = (1 << CH7017_LOOP_FILTER_SHIFT) |
(0 << CH7017_PHASE_DETECTOR_SHIFT);
} else {
outputs_enable = CH7017_LVDS_CHANNEL_A | CH7017_CHARGE_PUMP_HIGH;
lvds_pll_feedback_div = CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED |
(2 << CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT) |
(3 << CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT);
lvds_pll_feedback_div = 35;
lvds_control_2 = (3 << CH7017_LOOP_FILTER_SHIFT) |
(0 << CH7017_PHASE_DETECTOR_SHIFT);
if (1) { /* XXX: dual channel panel detection. Assume yes for now. */
outputs_enable |= CH7017_LVDS_CHANNEL_B;
lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
(2 << CH7017_LVDS_PLL_VCO_SHIFT) |
(13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
} else {
lvds_pll_vco_control = CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED |
(1 << CH7017_LVDS_PLL_VCO_SHIFT) |
(13 << CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT);
}
}
horizontal_active_pixel_input = mode->HDisplay & 0x00ff;
vertical_active_line_output = mode->VDisplay & 0x00ff;
horizontal_active_pixel_output = mode->HDisplay & 0x00ff;
active_input_line_output = ((mode->HDisplay & 0x0700) >> 8) |
(((mode->VDisplay & 0x0700) >> 8) << 3);
lvds_power_down = CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED |
(mode->HDisplay & 0x0700) >> 8;
ch7017_dpms(d, DPMSModeOff);
ch7017_write(priv, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT,
horizontal_active_pixel_input);
ch7017_write(priv, CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT,
horizontal_active_pixel_output);
ch7017_write(priv, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT,
vertical_active_line_output);
ch7017_write(priv, CH7017_ACTIVE_INPUT_LINE_OUTPUT,
active_input_line_output);
ch7017_write(priv, CH7017_LVDS_PLL_VCO_CONTROL, lvds_pll_vco_control);
ch7017_write(priv, CH7017_LVDS_PLL_FEEDBACK_DIV, lvds_pll_feedback_div);
ch7017_write(priv, CH7017_LVDS_CONTROL_2, lvds_control_2);
ch7017_write(priv, CH7017_OUTPUTS_ENABLE, outputs_enable);
/* Turn the LVDS back on with new settings. */
ch7017_write(priv, CH7017_LVDS_POWER_DOWN, lvds_power_down);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO,
"Registers after mode setting\n");
ch7017_dump_regs(d);
}
/* set the CH7017 power state */
static void
ch7017_dpms(I2CDevPtr d, int mode)
{
struct ch7017_priv *priv = d->DriverPrivate.ptr;
uint8_t val;
ch7017_read(priv, CH7017_LVDS_POWER_DOWN, &val);
/* Turn off TV/VGA, and never turn it on since we don't support it. */
ch7017_write(priv, CH7017_POWER_MANAGEMENT,
CH7017_DAC0_POWER_DOWN |
CH7017_DAC1_POWER_DOWN |
CH7017_DAC2_POWER_DOWN |
CH7017_DAC3_POWER_DOWN |
CH7017_TV_POWER_DOWN_EN);
if (mode == DPMSModeOn) {
/* Turn on the LVDS */
ch7017_write(priv, CH7017_LVDS_POWER_DOWN,
val & ~CH7017_LVDS_POWER_DOWN_EN);
} else {
/* Turn off the LVDS */
ch7017_write(priv, CH7017_LVDS_POWER_DOWN,
val | CH7017_LVDS_POWER_DOWN_EN);
}
/* XXX: Should actually wait for update power status somehow */
usleep(50000);
}
static void
ch7017_dump_regs(I2CDevPtr d)
{
struct ch7017_priv *priv = d->DriverPrivate.ptr;
uint8_t val;
#define DUMP(reg) \
do { \
ch7017_read(priv, reg, &val); \
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, \
#reg ": %02x\n", val); \
} while (0)
DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT);
DUMP(CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT);
DUMP(CH7017_VERTICAL_ACTIVE_LINE_OUTPUT);
DUMP(CH7017_ACTIVE_INPUT_LINE_OUTPUT);
DUMP(CH7017_LVDS_PLL_VCO_CONTROL);
DUMP(CH7017_LVDS_PLL_FEEDBACK_DIV);
DUMP(CH7017_LVDS_CONTROL_2);
DUMP(CH7017_OUTPUTS_ENABLE);
DUMP(CH7017_LVDS_POWER_DOWN);
}
static void
ch7017_save(I2CDevPtr d)
{
struct ch7017_priv *priv = d->DriverPrivate.ptr;
ch7017_read(priv, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, &priv->save_hapi);
ch7017_read(priv, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, &priv->save_valo);
ch7017_read(priv, CH7017_ACTIVE_INPUT_LINE_OUTPUT, &priv->save_ailo);
ch7017_read(priv, CH7017_LVDS_PLL_VCO_CONTROL, &priv->save_lvds_pll_vco);
ch7017_read(priv, CH7017_LVDS_PLL_FEEDBACK_DIV, &priv->save_feedback_div);
ch7017_read(priv, CH7017_LVDS_CONTROL_2, &priv->save_lvds_control_2);
ch7017_read(priv, CH7017_OUTPUTS_ENABLE, &priv->save_outputs_enable);
ch7017_read(priv, CH7017_LVDS_POWER_DOWN, &priv->save_lvds_power_down);
ch7017_read(priv, CH7017_POWER_MANAGEMENT, &priv->save_power_management);
}
static void
ch7017_restore(I2CDevPtr d)
{
struct ch7017_priv *priv = d->DriverPrivate.ptr;
/* Power down before changing mode */
ch7017_dpms(d, DPMSModeOff);
ch7017_write(priv, CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT, priv->save_hapi);
ch7017_write(priv, CH7017_VERTICAL_ACTIVE_LINE_OUTPUT, priv->save_valo);
ch7017_write(priv, CH7017_ACTIVE_INPUT_LINE_OUTPUT, priv->save_ailo);
ch7017_write(priv, CH7017_LVDS_PLL_VCO_CONTROL, priv->save_lvds_pll_vco);
ch7017_write(priv, CH7017_LVDS_PLL_FEEDBACK_DIV, priv->save_feedback_div);
ch7017_write(priv, CH7017_LVDS_CONTROL_2, priv->save_lvds_control_2);
ch7017_write(priv, CH7017_OUTPUTS_ENABLE, priv->save_outputs_enable);
ch7017_write(priv, CH7017_LVDS_POWER_DOWN, priv->save_lvds_power_down);
ch7017_write(priv, CH7017_POWER_MANAGEMENT, priv->save_power_management);
}
_X_EXPORT I830I2CVidOutputRec ch7017_methods = {
.init = ch7017_init,
.detect = ch7017_detect,
.mode_valid = ch7017_mode_valid,
.mode_set = ch7017_mode_set,
.dpms = ch7017_dpms,
.dump_regs = ch7017_dump_regs,
.save = ch7017_save,
.restore = ch7017_restore,
};

36
src/ch7017/ch7017_module.c
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@ -1,36 +0,0 @@
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(ch7017Setup);
static XF86ModuleVersionInfo ch7017VersRec =
{
"ch7017",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{ 0,0,0,0 }
};
_X_EXPORT XF86ModuleData ch7017ModuleData = {
&ch7017VersRec,
ch7017Setup,
NULL
};
static pointer
ch7017Setup(pointer module, pointer opts, int *errmaj, int *errmin) {
return (pointer)1;
}

162
src/ch7017/ch7017_reg.h
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@ -1,162 +0,0 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifndef CH7017_REG_H
#define CH7017_REG_H
#define CH7017_TV_DISPLAY_MODE 0x00
#define CH7017_FLICKER_FILTER 0x01
#define CH7017_VIDEO_BANDWIDTH 0x02
#define CH7017_TEXT_ENHANCEMENT 0x03
#define CH7017_START_ACTIVE_VIDEO 0x04
#define CH7017_HORIZONTAL_POSITION 0x05
#define CH7017_VERTICAL_POSITION 0x06
#define CH7017_BLACK_LEVEL 0x07
#define CH7017_CONTRAST_ENHANCEMENT 0x08
#define CH7017_TV_PLL 0x09
#define CH7017_TV_PLL_M 0x0a
#define CH7017_TV_PLL_N 0x0b
#define CH7017_SUB_CARRIER_0 0x0c
#define CH7017_CIV_CONTROL 0x10
#define CH7017_CIV_0 0x11
#define CH7017_CHROMA_BOOST 0x14
#define CH7017_CLOCK_MODE 0x1c
#define CH7017_INPUT_CLOCK 0x1d
#define CH7017_GPIO_CONTROL 0x1e
#define CH7017_INPUT_DATA_FORMAT 0x1f
#define CH7017_CONNECTION_DETECT 0x20
#define CH7017_DAC_CONTROL 0x21
#define CH7017_BUFFERED_CLOCK_OUTPUT 0x22
#define CH7017_DEFEAT_VSYNC 0x47
#define CH7017_TEST_PATTERN 0x48
#define CH7017_POWER_MANAGEMENT 0x49
/** Enables the TV output path. */
#define CH7017_TV_EN (1 << 0)
#define CH7017_DAC0_POWER_DOWN (1 << 1)
#define CH7017_DAC1_POWER_DOWN (1 << 2)
#define CH7017_DAC2_POWER_DOWN (1 << 3)
#define CH7017_DAC3_POWER_DOWN (1 << 4)
/** Powers down the TV out block, and DAC0-3 */
#define CH7017_TV_POWER_DOWN_EN (1 << 5)
#define CH7017_VERSION_ID 0x4a
#define CH7017_DEVICE_ID 0x4b
#define CH7017_DEVICE_ID_VALUE 0x1b
#define CH7018_DEVICE_ID_VALUE 0x1a
#define CH7019_DEVICE_ID_VALUE 0x19
#define CH7017_XCLK_D2_ADJUST 0x53
#define CH7017_UP_SCALER_COEFF_0 0x55
#define CH7017_UP_SCALER_COEFF_1 0x56
#define CH7017_UP_SCALER_COEFF_2 0x57
#define CH7017_UP_SCALER_COEFF_3 0x58
#define CH7017_UP_SCALER_COEFF_4 0x59
#define CH7017_UP_SCALER_VERTICAL_INC_0 0x5a
#define CH7017_UP_SCALER_VERTICAL_INC_1 0x5b
#define CH7017_GPIO_INVERT 0x5c
#define CH7017_UP_SCALER_HORIZONTAL_INC_0 0x5d
#define CH7017_UP_SCALER_HORIZONTAL_INC_1 0x5e
#define CH7017_HORIZONTAL_ACTIVE_PIXEL_INPUT 0x5f
/**< Low bits of horizontal active pixel input */
#define CH7017_ACTIVE_INPUT_LINE_OUTPUT 0x60
/** High bits of horizontal active pixel input */
#define CH7017_LVDS_HAP_INPUT_MASK (0x7 << 0)
/** High bits of vertical active line output */
#define CH7017_LVDS_VAL_HIGH_MASK (0x7 << 3)
#define CH7017_VERTICAL_ACTIVE_LINE_OUTPUT 0x61
/**< Low bits of vertical active line output */
#define CH7017_HORIZONTAL_ACTIVE_PIXEL_OUTPUT 0x62
/**< Low bits of horizontal active pixel output */
#define CH7017_LVDS_POWER_DOWN 0x63
/** High bits of horizontal active pixel output */
#define CH7017_LVDS_HAP_HIGH_MASK (0x7 << 0)
/** Enables the LVDS power down state transition */
#define CH7017_LVDS_POWER_DOWN_EN (1 << 6)
/** Enables the LVDS upscaler */
#define CH7017_LVDS_UPSCALER_EN (1 << 7)
#define CH7017_LVDS_POWER_DOWN_DEFAULT_RESERVED 0x08
#define CH7017_LVDS_ENCODING 0x64
#define CH7017_LVDS_DITHER_2D (1 << 2)
#define CH7017_LVDS_DITHER_DIS (1 << 3)
#define CH7017_LVDS_DUAL_CHANNEL_EN (1 << 4)
#define CH7017_LVDS_24_BIT (1 << 5)
#define CH7017_LVDS_ENCODING_2 0x65
#define CH7017_LVDS_PLL_CONTROL 0x66
/** Enables the LVDS panel output path */
#define CH7017_LVDS_PANEN (1 << 0)
/** Enables the LVDS panel backlight */
#define CH7017_LVDS_BKLEN (1 << 3)
#define CH7017_POWER_SEQUENCING_T1 0x67
#define CH7017_POWER_SEQUENCING_T2 0x68
#define CH7017_POWER_SEQUENCING_T3 0x69
#define CH7017_POWER_SEQUENCING_T4 0x6a
#define CH7017_POWER_SEQUENCING_T5 0x6b
#define CH7017_GPIO_DRIVER_TYPE 0x6c
#define CH7017_GPIO_DATA 0x6d
#define CH7017_GPIO_DIRECTION_CONTROL 0x6e
#define CH7017_LVDS_PLL_FEEDBACK_DIV 0x71
# define CH7017_LVDS_PLL_FEED_BACK_DIVIDER_SHIFT 4
# define CH7017_LVDS_PLL_FEED_FORWARD_DIVIDER_SHIFT 0
# define CH7017_LVDS_PLL_FEEDBACK_DEFAULT_RESERVED 0x80
#define CH7017_LVDS_PLL_VCO_CONTROL 0x72
# define CH7017_LVDS_PLL_VCO_DEFAULT_RESERVED 0x80
# define CH7017_LVDS_PLL_VCO_SHIFT 4
# define CH7017_LVDS_PLL_POST_SCALE_DIV_SHIFT 0
#define CH7017_OUTPUTS_ENABLE 0x73
# define CH7017_CHARGE_PUMP_LOW 0x0
# define CH7017_CHARGE_PUMP_HIGH 0x3
# define CH7017_LVDS_CHANNEL_A (1 << 3)
# define CH7017_LVDS_CHANNEL_B (1 << 4)
# define CH7017_TV_DAC_A (1 << 5)
# define CH7017_TV_DAC_B (1 << 6)
# define CH7017_DDC_SELECT_DC2 (1 << 7)
#define CH7017_LVDS_OUTPUT_AMPLITUDE 0x74
#define CH7017_LVDS_PLL_EMI_REDUCTION 0x75
#define CH7017_LVDS_POWER_DOWN_FLICKER 0x76
#define CH7017_LVDS_CONTROL_2 0x78
# define CH7017_LOOP_FILTER_SHIFT 5
# define CH7017_PHASE_DETECTOR_SHIFT 0
#define CH7017_BANG_LIMIT_CONTROL 0x7f
#endif /* CH7017_REG_H */

17
src/ch7xxx/Makefile.am
View File

@ -1,17 +0,0 @@
# this is obnoxious:
# -module lets us name the module exactly how we want
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
@PCIACCESS_CFLAGS@
ch7xxx_la_LTLIBRARIES = ch7xxx.la
ch7xxx_la_LDFLAGS = -module -avoid-version
ch7xxx_ladir = @moduledir@/drivers
ch7xxx_la_SOURCES = \
ch7xxx.c \
ch7xxx_module.c \
ch7xxx.h \
ch7xxx_reg.h

323
src/ch7xxx/ch7xxx.c
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@ -1,323 +0,0 @@
/**************************************************************************
Copyright © 2006 Dave Airlie
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdint.h>
#include <string.h>
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "miscstruct.h"
#include "xf86i2c.h"
#include "xf86Crtc.h"
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include "../i2c_vid.h"
#include "ch7xxx.h"
#include "ch7xxx_reg.h"
/** @file
* driver for the Chrontel 7xxx DVI chip over DVO.
*/
static struct ch7xxx_id_struct {
uint8_t vid;
char *name;
} ch7xxx_ids[] = {
{ CH7011_VID, "CH7011" },
{ CH7009A_VID, "CH7009A" },
{ CH7009B_VID, "CH7009B" },
{ CH7301_VID, "CH7301" },
};
#define ID_ARRAY_SIZE (sizeof(ch7xxx_ids) / sizeof(ch7xxx_ids[0]))
struct ch7xxx_reg_state {
uint8_t regs[CH7xxx_NUM_REGS];
};
struct ch7xxx_priv {
I2CDevRec d;
Bool quiet;
struct ch7xxx_reg_state SavedReg;
struct ch7xxx_reg_state ModeReg;
uint8_t save_TCTL, save_TPCP, save_TPD, save_TPVT;
uint8_t save_TLPF, save_TCT, save_PM, save_IDF;
};
static void ch7xxx_save(I2CDevPtr d);
static char *ch7xxx_get_id(uint8_t vid)
{
int i;
for (i = 0; i < ID_ARRAY_SIZE; i++) {
if (ch7xxx_ids[i].vid == vid)
return ch7xxx_ids[i].name;
}
return NULL;
}
/** Reads an 8 bit register */
static Bool
ch7xxx_read(struct ch7xxx_priv *dev_priv, int addr, unsigned char *ch)
{
if (!xf86I2CReadByte(&dev_priv->d, addr, ch)) {
if (!dev_priv->quiet) {
xf86DrvMsg(dev_priv->d.pI2CBus->scrnIndex,
X_ERROR, "Unable to read from %s Slave %d.\n",
dev_priv->d.pI2CBus->BusName, dev_priv->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
/** Writes an 8 bit register */
static Bool
ch7xxx_write(struct ch7xxx_priv *dev_priv, int addr, unsigned char ch)
{
if (!xf86I2CWriteByte(&dev_priv->d, addr, ch)) {
if (!dev_priv->quiet) {
xf86DrvMsg(dev_priv->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to write to %s Slave %d.\n",
dev_priv->d.pI2CBus->BusName, dev_priv->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
static void *
ch7xxx_init(I2CBusPtr b, I2CSlaveAddr addr)
{
/* this will detect the CH7xxx chip on the specified i2c bus */
struct ch7xxx_priv *dev_priv;
uint8_t vendor, device;
char *name;
dev_priv = xcalloc(1, sizeof(struct ch7xxx_priv));
if (dev_priv == NULL)
return NULL;
dev_priv->d.DevName = "CH7xxx TMDS Controller";
dev_priv->d.SlaveAddr = addr;
dev_priv->d.pI2CBus = b;
dev_priv->d.StartTimeout = b->StartTimeout;
dev_priv->d.BitTimeout = b->BitTimeout;
dev_priv->d.AcknTimeout = b->AcknTimeout;
dev_priv->d.ByteTimeout = b->ByteTimeout;
dev_priv->d.DriverPrivate.ptr = dev_priv;
dev_priv->quiet = TRUE;
if (!ch7xxx_read(dev_priv, CH7xxx_REG_VID, &vendor))
goto out;
name = ch7xxx_get_id(vendor);
if (!name) {
xf86DrvMsg(dev_priv->d.pI2CBus->scrnIndex, X_INFO,
"ch7xxx not detected; got 0x%02x from %s slave %d.\n",
vendor, dev_priv->d.pI2CBus->BusName,
dev_priv->d.SlaveAddr);
goto out;
}
if (!ch7xxx_read(dev_priv, CH7xxx_REG_DID, &device))
goto out;
if (device != CH7xxx_DID) {
xf86DrvMsg(dev_priv->d.pI2CBus->scrnIndex, X_INFO,
"ch7xxx not detected; got 0x%02x from %s slave %d.\n",
device, dev_priv->d.pI2CBus->BusName,
dev_priv->d.SlaveAddr);
goto out;
}
dev_priv->quiet = FALSE;
xf86DrvMsg(dev_priv->d.pI2CBus->scrnIndex, X_INFO,
"Detected %s chipset, vendor/device ID 0x%02x/0x%02x\n",
name, vendor, device);
if (!xf86I2CDevInit(&dev_priv->d)) {
goto out;
}
return dev_priv;
out:
xfree(dev_priv);
return NULL;
}
static xf86OutputStatus
ch7xxx_detect(I2CDevPtr d)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
uint8_t cdet, orig_pm, pm;
ch7xxx_read(dev_priv, CH7xxx_PM, &orig_pm);
pm = orig_pm;
pm &= ~CH7xxx_PM_FPD;
pm |= CH7xxx_PM_DVIL | CH7xxx_PM_DVIP;
ch7xxx_write(dev_priv, CH7xxx_PM, pm);
ch7xxx_read(dev_priv, CH7xxx_CONNECTION_DETECT, &cdet);
ch7xxx_write(dev_priv, CH7xxx_PM, orig_pm);
if (cdet & CH7xxx_CDET_DVI)
return XF86OutputStatusConnected;
return XF86OutputStatusDisconnected;
}
static ModeStatus
ch7xxx_mode_valid(I2CDevPtr d, DisplayModePtr mode)
{
if (mode->Clock > 165000)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static void
ch7xxx_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
uint8_t tvco, tpcp, tpd, tlpf, idf;
if (mode->Clock <= 65000) {
tvco = 0x23;
tpcp = 0x08;
tpd = 0x16;
tlpf = 0x60;
} else {
tvco = 0x2d;
tpcp = 0x06;
tpd = 0x26;
tlpf = 0xa0;
}
ch7xxx_write(dev_priv, CH7xxx_TCTL, 0x00);
ch7xxx_write(dev_priv, CH7xxx_TVCO, tvco);
ch7xxx_write(dev_priv, CH7xxx_TPCP, tpcp);
ch7xxx_write(dev_priv, CH7xxx_TPD, tpd);
ch7xxx_write(dev_priv, CH7xxx_TPVT, 0x30);
ch7xxx_write(dev_priv, CH7xxx_TLPF, tlpf);
ch7xxx_write(dev_priv, CH7xxx_TCT, 0x00);
ch7xxx_read(dev_priv, CH7xxx_IDF, &idf);
idf &= ~(CH7xxx_IDF_HSP | CH7xxx_IDF_VSP);
if (mode->Flags & V_PHSYNC)
idf |= CH7xxx_IDF_HSP;
if (mode->Flags & V_PVSYNC)
idf |= CH7xxx_IDF_HSP;
ch7xxx_write(dev_priv, CH7xxx_IDF, idf);
}
/* set the CH7xxx power state */
static void
ch7xxx_dpms(I2CDevPtr d, int mode)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
if (mode == DPMSModeOn)
ch7xxx_write(dev_priv, CH7xxx_PM, CH7xxx_PM_DVIL | CH7xxx_PM_DVIP);
else
ch7xxx_write(dev_priv, CH7xxx_PM, CH7xxx_PM_FPD);
}
static void
ch7xxx_dump_regs(I2CDevPtr d)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
int i;
for (i = 0; i < CH7xxx_NUM_REGS; i++) {
if (( i % 8 ) == 0 )
ErrorF("\n %02X: ", i);
ErrorF("%02X ", dev_priv->ModeReg.regs[i]);
}
}
static void
ch7xxx_save(I2CDevPtr d)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
ch7xxx_read(dev_priv, CH7xxx_TCTL, &dev_priv->save_TCTL);
ch7xxx_read(dev_priv, CH7xxx_TPCP, &dev_priv->save_TPCP);
ch7xxx_read(dev_priv, CH7xxx_TPD, &dev_priv->save_TPD);
ch7xxx_read(dev_priv, CH7xxx_TPVT, &dev_priv->save_TPVT);
ch7xxx_read(dev_priv, CH7xxx_TLPF, &dev_priv->save_TLPF);
ch7xxx_read(dev_priv, CH7xxx_PM, &dev_priv->save_PM);
ch7xxx_read(dev_priv, CH7xxx_IDF, &dev_priv->save_IDF);
}
static void
ch7xxx_restore(I2CDevPtr d)
{
struct ch7xxx_priv *dev_priv = d->DriverPrivate.ptr;
ch7xxx_write(dev_priv, CH7xxx_TCTL, dev_priv->save_TCTL);
ch7xxx_write(dev_priv, CH7xxx_TPCP, dev_priv->save_TPCP);
ch7xxx_write(dev_priv, CH7xxx_TPD, dev_priv->save_TPD);
ch7xxx_write(dev_priv, CH7xxx_TPVT, dev_priv->save_TPVT);
ch7xxx_write(dev_priv, CH7xxx_TLPF, dev_priv->save_TLPF);
ch7xxx_write(dev_priv, CH7xxx_IDF, dev_priv->save_IDF);
ch7xxx_write(dev_priv, CH7xxx_PM, dev_priv->save_PM);
}
_X_EXPORT I830I2CVidOutputRec CH7xxxVidOutput = {
.init = ch7xxx_init,
.detect = ch7xxx_detect,
.mode_valid = ch7xxx_mode_valid,
.mode_set = ch7xxx_mode_set,
.dpms = ch7xxx_dpms,
.dump_regs = ch7xxx_dump_regs,
.save = ch7xxx_save,
.restore = ch7xxx_restore,
};

31
src/ch7xxx/ch7xxx.h
View File

@ -1,31 +0,0 @@
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifndef CH7xxx_H
#define CH7xxx_H
#define CH7xxx_ADDR_1 0x76
#endif

35
src/ch7xxx/ch7xxx_module.c
View File

@ -1,35 +0,0 @@
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(ch7xxxSetup);
static XF86ModuleVersionInfo ch7xxxVersRec = {
"ch7xxx",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{ 0,0,0,0 }
};
_X_EXPORT XF86ModuleData ch7xxxModuleData = {
&ch7xxxVersRec,
ch7xxxSetup,
NULL
};
static pointer
ch7xxxSetup(pointer module, pointer opts, int *errmaj, int *errmin) {
return (pointer)1;
}

80
src/ch7xxx/ch7xxx_reg.h
View File

@ -1,80 +0,0 @@
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifndef CH7xxx_REG_H
#define CH7xxx_REG_H
#define CH7xxx_REG_VID 0x4a
#define CH7xxx_REG_DID 0x4b
#define CH7011_VID 0x83 /* 7010 as well */
#define CH7009A_VID 0x84
#define CH7009B_VID 0x85
#define CH7301_VID 0x95
#define CH7xxx_VID 0x84
#define CH7xxx_DID 0x17
#define CH7xxx_NUM_REGS 0x4c
#define CH7xxx_CM 0x1C
#define CH7xxx_CM_XCM (1<<0)
#define CH7xxx_CM_MCP (1<<2)
#define CH7xxx_INPUT_CLOCK 0x1D
#define CH7xxx_GPIO 0x1E
#define CH7xxx_GPIO_HPIR (1<<3)
#define CH7xxx_IDF 0x1F
#define CH7xxx_IDF_HSP (1<<3)
#define CH7xxx_IDF_VSP (1<<4)
#define CH7xxx_CONNECTION_DETECT 0x20
#define CH7xxx_CDET_DVI (1<<5)
#define CH7301_DAC_CNTL 0x21
#define CH7301_HOTPLUG 0x23
#define CH7xxx_TCTL 0x31
#define CH7xxx_TVCO 0x32
#define CH7xxx_TPCP 0x33
#define CH7xxx_TPD 0x34
#define CH7xxx_TPVT 0x35
#define CH7xxx_TLPF 0x36
#define CH7xxx_TCT 0x37
#define CH7301_TEST_PATTERN 0x48
#define CH7xxx_PM 0x49
#define CH7xxx_PM_FPD (1<<0)
#define CH7301_PM_DACPD0 (1<<1)
#define CH7301_PM_DACPD1 (1<<2)
#define CH7301_PM_DACPD2 (1<<3)
#define CH7xxx_PM_DVIL (1<<6)
#define CH7xxx_PM_DVIP (1<<7)
#define CH7301_SYNC_POLARITY 0x56
#define CH7301_SYNC_RGB_YUV (1<<0)
#define CH7301_SYNC_POL_DVI (1<<5)
#endif

7
src/common.h
View File

@ -370,13 +370,6 @@ extern int I810_DEBUG;
#define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810)) #define OVERLAY_NOPHYSICAL(pI810) (IS_G33CLASS(pI810) || IS_I965G(pI810))
/* mark chipsets without overlay hw */ /* mark chipsets without overlay hw */
#define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) #define OVERLAY_NOEXIST(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* chipsets require graphics mem for hardware status page */
#define HWS_NEED_GFX(pI810) (!pI810->use_drm_mode && \
(IS_G33CLASS(pI810) ||\
IS_G4X(pI810) || IS_IGDNG(pI810)))
/* chipsets require status page in non stolen memory */
#define HWS_NEED_NONSTOLEN(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
#define SUPPORTS_INTEGRATED_HDMI(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* dsparb controlled by hw only */ /* dsparb controlled by hw only */
#define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810)) #define DSPARB_HWCONTROL(pI810) (IS_G4X(pI810) || IS_IGDNG(pI810))
/* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */ /* supports Y tiled surfaces (pre-965 Mesa isn't ready yet) */

132
src/i2c_vid.h
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@ -1,132 +0,0 @@
/*
* Copyright © 2006 Eric Anholt
*
* Permission to use, copy, modify, distribute, and sell this software and its
* documentation for any purpose is hereby granted without fee, provided that
* the above copyright notice appear in all copies and that both that copyright
* notice and this permission notice appear in supporting documentation, and
* that the name of the copyright holders not be used in advertising or
* publicity pertaining to distribution of the software without specific,
* written prior permission. The copyright holders make no representations
* about the suitability of this software for any purpose. It is provided "as
* is" without express or implied warranty.
*
* THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
* EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
* DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
* OF THIS SOFTWARE.
*/
#ifndef I2C_VID_H
#define I2C_VID_H
#include <randrstr.h>
typedef struct _I830I2CVidOutputRec {
/**
* Initialize the device at startup time.
* Returns NULL if the device does not exist.
*/
void *(*init)(I2CBusPtr b, I2CSlaveAddr addr);
/**
* Called to allow the output a chance to create properties after the
* RandR objects have been created.
*/
void
(*create_resources)(I2CDevPtr d);
/**
* Turns the output on/off, or sets intermediate power levels if available.
*
* Unsupported intermediate modes drop to the lower power setting. If the
* mode is DPMSModeOff, the output must be disabled, as the DPLL may be
* disabled afterwards.
*/
void (*dpms)(I2CDevPtr d, int mode);
/**
* Saves the output's state for restoration on VT switch.
*/
void (*save)(I2CDevPtr d);
/**
* Restore's the output's state at VT switch.
*/
void (*restore)(I2CDevPtr d);
/**
* Callback for testing a video mode for a given output.
*
* This function should only check for cases where a mode can't be supported
* on the output specifically, and not represent generic CRTC limitations.
*
* \return MODE_OK if the mode is valid, or another MODE_* otherwise.
*/
int (*mode_valid)(I2CDevPtr d, DisplayModePtr mode);
/**
* Callback to adjust the mode to be set in the CRTC.
*
* This allows an output to adjust the clock or even the entire set of
* timings, which is used for panels with fixed timings or for
* buses with clock limitations.
*/
Bool (*mode_fixup)(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode);
/**
* Callback for preparing mode changes on an output
*/
void (*prepare)(I2CDevPtr d);
/**
* Callback for committing mode changes on an output
*/
void (*commit)(I2CDevPtr d);
/**
* Callback for setting up a video mode after fixups have been made.
*
* This is only called while the output is disabled. The dpms callback
* must be all that's necessary for the output, to turn the output on
* after this function is called.
*/
void (*mode_set)(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode);
/**
* Probe for a connected output, and return detect_status.
*/
xf86OutputStatus (*detect)(I2CDevPtr d);
/**
* Query the device for the modes it provides.
*
* This function may also update MonInfo, mm_width, and mm_height.
*
* \return singly-linked list of modes or NULL if no modes found.
*/
DisplayModePtr
(*get_modes)(I2CDevPtr d);
#ifdef RANDR_12_INTERFACE
/**
* Callback when an output's property has changed.
*/
Bool
(*set_property)(I2CDevPtr d, Atom property, RRPropertyValuePtr value);
#endif
/**
* Clean up driver-specific bits of the output
*/
void (*destroy) (I2CDevPtr d);
/**
* Debugging hook to dump device registers to log file
*/
void (*dump_regs)(I2CDevPtr d);
} I830I2CVidOutputRec, *I830I2CVidOutputPtr;
#endif

368
src/i830.h
View File

@ -83,8 +83,6 @@ void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo *bo);
typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr; typedef struct _I830OutputRec I830OutputRec, *I830OutputPtr;
#include "common.h" #include "common.h"
#include "i830_sdvo.h"
#include "i2c_vid.h"
#ifdef XvMCExtension #ifdef XvMCExtension
#ifdef ENABLE_XVMC #ifdef ENABLE_XVMC
@ -126,35 +124,8 @@ struct _i830_memory {
* Any bound memory will cover offset to (offset + size). * Any bound memory will cover offset to (offset + size).
*/ */
unsigned long size; unsigned long size;
/**
* Allocated aperture size, taking into account padding to allow for
* tiling.
*/
unsigned long allocated_size;
/**
* Physical (or more properly, bus) address of the allocation.
* Only set if requested during allocation.
*/
uint64_t bus_addr;
/** AGP memory handle */
int key;
/**
* Whether or not the AGP memory (if any) is currently bound.
*/
Bool bound;
/**
* Offset that the AGP-allocated memory (if any) is to be bound to.
*
* This is either @offset or pI830->stolen_size
*/
unsigned long agp_offset;
enum tile_format tiling; enum tile_format tiling;
/**
* Index of the fence register representing the tiled surface, when
* bound.
*/
int fence_nr;
/** Pitch value in bytes for tiled surfaces */ /** Pitch value in bytes for tiled surfaces */
unsigned int pitch; unsigned int pitch;
@ -171,48 +142,6 @@ struct _i830_memory {
dri_bo *bo; dri_bo *bo;
uint32_t alignment; uint32_t alignment;
uint32_t gem_name; uint32_t gem_name;
Bool lifetime_fixed_offset;
};
typedef struct {
int tail_mask;
i830_memory *mem;
unsigned char *virtual_start;
int head;
int tail;
int space;
} I830RingBuffer;
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
#define MAX_OUTPUTS 6
#define I830_I2C_BUS_DVO 1
#define I830_I2C_BUS_SDVO 2
/* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
#define I830_OUTPUT_UNUSED 0
#define I830_OUTPUT_ANALOG 1
#define I830_OUTPUT_DVO_TMDS 2
#define I830_OUTPUT_DVO_LVDS 3
#define I830_OUTPUT_DVO_TVOUT 4
#define I830_OUTPUT_SDVO 5
#define I830_OUTPUT_LVDS 6
#define I830_OUTPUT_TVOUT 7
#define I830_OUTPUT_HDMI 8
struct _I830DVODriver {
int type;
char *modulename;
char *fntablename;
unsigned int dvo_reg;
uint32_t gpio;
int address;
I830I2CVidOutputRec *vid_rec;
void *dev_priv;
pointer modhandle;
}; };
typedef struct _I830CrtcPrivateRec { typedef struct _I830CrtcPrivateRec {
@ -227,37 +156,10 @@ typedef struct _I830CrtcPrivateRec {
/* Lookup table values to be set when the CRTC is enabled */ /* Lookup table values to be set when the CRTC is enabled */
uint8_t lut_r[256], lut_g[256], lut_b[256]; uint8_t lut_r[256], lut_g[256], lut_b[256];
i830_memory *rotate_mem;
/* Card virtual address of the cursor */
unsigned long cursor_offset;
unsigned long cursor_argb_offset;
/* Physical or virtual addresses of the cursor for setting in the cursor
* registers.
*/
uint64_t cursor_addr;
unsigned long cursor_argb_addr;
Bool cursor_is_argb;
} I830CrtcPrivateRec, *I830CrtcPrivatePtr; } I830CrtcPrivateRec, *I830CrtcPrivatePtr;
#define I830CrtcPrivate(c) ((I830CrtcPrivatePtr) (c)->driver_private) #define I830CrtcPrivate(c) ((I830CrtcPrivatePtr) (c)->driver_private)
typedef struct _I830OutputPrivateRec {
int type;
I2CBusPtr pI2CBus;
I2CBusPtr pDDCBus;
struct _I830DVODriver *i2c_drv;
Bool load_detect_temp;
Bool needs_tv_clock;
uint32_t lvds_bits;
int pipe_mask;
int clone_mask;
/** Output-private structure. Should replace i2c_drv */
void *dev_priv;
} I830OutputPrivateRec, *I830OutputPrivatePtr;
#define I830OutputPrivate(o) ((I830OutputPrivatePtr) (o)->driver_private)
/** enumeration of 3d consumers so some can maintain invariant state. */ /** enumeration of 3d consumers so some can maintain invariant state. */
enum last_3d { enum last_3d {
LAST_3D_OTHER, LAST_3D_OTHER,
@ -266,72 +168,14 @@ enum last_3d {
LAST_3D_ROTATION LAST_3D_ROTATION
}; };
/*
* Backlight control has some unfortunate properties:
* - many machines won't give us brightness change notifications
* o brightness hotkeys
* o events like AC plug/unplug (can be controlled via _DOS setting)
* o ambient light sensor triggered changes
* - some machines use the so-called "legacy" backlight interface
* o resulting brightness is a combo of LBB and PWM values
* o LBB sits in config space
* - some machines have ACPI methods for changing brightness
* o one of the few ways the X server and firmware can stay in sync
* - new machines have the IGD OpRegion interface available
* o a reliable way of keeping the firmware and X in sync
*
* So the real problem is on machines where ACPI or OpRegion methods aren't
* available. In that case, problems can occur:
* 1) the BIOS and X will have different ideas of what the brightness is,
* leading to unexpected results when the brightness is increased or
* decreased via hotkey or X protocol
* 2) unless X takes the legacy register into account, machines using it
* may prevent X from raising the brightness above 0 if the firmware
* set LBB to 0
* Given these problems, we provide the user with a selection of methods,
* so they can choose an ideal one for their platform (assuming our quirk
* code picks the wrong one).
*
* Four different backlight control methods are available:
* BCM_NATIVE: only ever touch the native backlight control registers
* This method may be susceptible to problem (2) above if the firmware
* modifies the legacy registers.
* BCM_LEGACY: only ever touch the legacy backlight control registers
* This method may be susceptible to problem (1) above if the firmware
* also modifies the legacy registers.
* BCM_COMBO: try to use both sets
* In this case, the driver will try to modify both sets of registers
* if needed. To avoid problem (2) above it may set the LBB register
* to a non-zero value if the brightness is to be increased. It's still
* susceptible to problem (1), but to a lesser extent than the LEGACY only
* method.
* BCM_KERNEL: use kernel methods for controlling the backlight
* This is only available on some platforms, but where present this can
* provide the best user experience.
*/
enum backlight_control {
BCM_NATIVE = 0,
BCM_LEGACY,
BCM_COMBO,
BCM_KERNEL,
};
enum dri_type { enum dri_type {
DRI_DISABLED, DRI_DISABLED,
DRI_NONE, DRI_NONE,
DRI_DRI2 DRI_DRI2
}; };
struct sdvo_device_mapping {
uint8_t dvo_port;
uint8_t slave_addr;
uint8_t dvo_wiring;
uint8_t initialized;
};
typedef struct _I830Rec { typedef struct _I830Rec {
unsigned char *MMIOBase; unsigned char *MMIOBase;
unsigned char *GTTBase;
unsigned char *FbBase;
int cpp; int cpp;
unsigned int bufferOffset; /* for I830SelectBuffer */ unsigned int bufferOffset; /* for I830SelectBuffer */
@ -347,28 +191,10 @@ typedef struct _I830Rec {
i830_memory *memory_list; i830_memory *memory_list;
/** Linked list of buffer object memory allocations */ /** Linked list of buffer object memory allocations */
i830_memory *bo_list; i830_memory *bo_list;
long stolen_size; /**< bytes of pre-bound stolen memory */
int gtt_acquired; /**< whether we currently own the AGP */
i830_memory *front_buffer; i830_memory *front_buffer;
i830_memory *compressed_front_buffer;
i830_memory *compressed_ll_buffer;
/* One big buffer for all cursors for kernels that support this */ /* One big buffer for all cursors for kernels that support this */
i830_memory *cursor_mem;
/* separate small buffers for kernels that support this */
i830_memory *cursor_mem_classic[2];
i830_memory *cursor_mem_argb[2]; i830_memory *cursor_mem_argb[2];
i830_memory *fake_bufmgr_mem;
/* Regions allocated either from the above pools, or from agpgart. */
I830RingBuffer ring;
/** Number of bytes being emitted in the current BEGIN_LP_RING */
unsigned int ring_emitting;
/** Number of bytes that have been emitted in the current BEGIN_LP_RING */
unsigned int ring_used;
/** Offset in the ring for the next DWORD emit */
uint32_t ring_next;
dri_bufmgr *bufmgr; dri_bufmgr *bufmgr;
@ -393,36 +219,21 @@ typedef struct _I830Rec {
Bool XvMCEnabled; Bool XvMCEnabled;
#endif #endif
XF86ModReqInfo shadowReq; /* to test for later libshadow */
CreateScreenResourcesProcPtr CreateScreenResources; CreateScreenResourcesProcPtr CreateScreenResources;
i830_memory *power_context;
i830_memory *memory_manager; /**< DRI memory manager aperture */
Bool have_gem;
Bool need_mi_flush; Bool need_mi_flush;
Bool tiling; Bool tiling;
Bool fb_compression;
Bool swapbuffers_wait; Bool swapbuffers_wait;
Bool CursorNeedsPhysical;
int Chipset; int Chipset;
unsigned long LinearAddr; unsigned long LinearAddr;
unsigned long MMIOAddr;
unsigned int MMIOSize;
IOADDRESS ioBase;
EntityInfoPtr pEnt; EntityInfoPtr pEnt;
struct pci_device *PciInfo; struct pci_device *PciInfo;
uint8_t variant; uint8_t variant;
unsigned int BR[20]; unsigned int BR[20];
Bool fence_used[FENCE_NEW_NR];
CloseScreenProcPtr CloseScreen; CloseScreenProcPtr CloseScreen;
void (*batch_flush_notify)(ScrnInfoPtr pScrn); void (*batch_flush_notify)(ScrnInfoPtr pScrn);
@ -436,11 +247,6 @@ typedef struct _I830Rec {
int accel_max_y; int accel_max_y;
int max_gtt_map_size; int max_gtt_map_size;
I830WriteIndexedByteFunc writeControl;
I830ReadIndexedByteFunc readControl;
I830WriteByteFunc writeStandard;
I830ReadByteFunc readStandard;
Bool XvDisabled; /* Xv disabled in PreInit. */ Bool XvDisabled; /* Xv disabled in PreInit. */
Bool XvEnabled; /* Xv enabled for this generation. */ Bool XvEnabled; /* Xv enabled for this generation. */
Bool XvPreferOverlay; Bool XvPreferOverlay;
@ -498,31 +304,8 @@ typedef struct _I830Rec {
/* Broken-out options. */ /* Broken-out options. */
OptionInfoPtr Options; OptionInfoPtr Options;
Bool lvds_24_bit_mode;
Bool lvds_use_ssc;
int lvds_ssc_freq; /* in MHz */
Bool lvds_dither;
DisplayModePtr lvds_fixed_mode;
DisplayModePtr sdvo_lvds_fixed_mode;
Bool skip_panel_detect;
Bool integrated_lvds; /* LVDS config from driver feature BDB */
Bool tv_present; /* TV connector present (from VBIOS) */
/* Driver phase/state information */ /* Driver phase/state information */
Bool preinit;
Bool starting;
Bool closing;
Bool suspended; Bool suspended;
Bool leaving;
unsigned int SaveGeneration;
OsTimerPtr devicesTimer;
int ddc2;
enum backlight_control backlight_control_method;
uint32_t saveDSPARB; uint32_t saveDSPARB;
uint32_t saveDSPACNTR; uint32_t saveDSPACNTR;
@ -603,16 +386,8 @@ typedef struct _I830Rec {
enum last_3d last_3d; enum last_3d last_3d;
Bool use_drm_mode;
Bool kernel_exec_fencing;
/** Enables logging of debug output related to mode switching. */
Bool debug_modes;
unsigned int quirk_flag;
/** User option to print acceleration fallback info to the server log. */ /** User option to print acceleration fallback info to the server log. */
Bool fallback_debug; Bool fallback_debug;
struct sdvo_device_mapping sdvo_mappings[2];
} I830Rec; } I830Rec;
#define I830PTR(p) ((I830Ptr)((p)->driverPrivate)) #define I830PTR(p) ((I830Ptr)((p)->driverPrivate))
@ -621,71 +396,26 @@ typedef struct _I830Rec {
#define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1)) #define ALIGN(i,m) (((i) + (m) - 1) & ~((m) - 1))
#define MIN(a,b) ((a) < (b) ? (a) : (b)) #define MIN(a,b) ((a) < (b) ? (a) : (b))
#define I830_SELECT_FRONT 0
#define I830_SELECT_BACK 1
#define I830_SELECT_DEPTH 2
#define I830_SELECT_THIRD 3
unsigned long intel_get_pixmap_offset(PixmapPtr pPix);
unsigned long intel_get_pixmap_pitch(PixmapPtr pPix); unsigned long intel_get_pixmap_pitch(PixmapPtr pPix);
/* Batchbuffer support macros and functions */ /* Batchbuffer support macros and functions */
#include "i830_batchbuffer.h" #include "i830_batchbuffer.h"
/* I830 specific functions */ /* I830 specific functions */
extern int I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis);
extern void I830SetPIOAccess(I830Ptr pI830);
extern void I830SetMMIOAccess(I830Ptr pI830);
extern void I830Sync(ScrnInfoPtr pScrn); extern void I830Sync(ScrnInfoPtr pScrn);
extern void I830InitHWCursor(ScrnInfoPtr pScrn);
extern void I830SetPipeCursor (xf86CrtcPtr crtc, Bool force);
extern Bool I830CursorInit(ScreenPtr pScreen);
extern void IntelEmitInvarientState(ScrnInfoPtr pScrn); extern void IntelEmitInvarientState(ScrnInfoPtr pScrn);
extern void I830EmitInvarientState(ScrnInfoPtr pScrn); extern void I830EmitInvarientState(ScrnInfoPtr pScrn);
extern void I915EmitInvarientState(ScrnInfoPtr pScrn); extern void I915EmitInvarientState(ScrnInfoPtr pScrn);
extern Bool I830SelectBuffer(ScrnInfoPtr pScrn, int buffer);
void i830_update_cursor_offsets(ScrnInfoPtr pScrn);
/* CRTC-based cursor functions */
void
i830_crtc_load_cursor_image (xf86CrtcPtr crtc, unsigned char *src);
#ifdef ARGB_CURSOR
void
i830_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image);
#endif
void
i830_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y);
void
i830_crtc_show_cursor (xf86CrtcPtr crtc);
void
i830_crtc_hide_cursor (xf86CrtcPtr crtc);
void
i830_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg);
extern void i830_refresh_ring(ScrnInfoPtr pScrn);
extern void I830EmitFlush(ScrnInfoPtr pScrn); extern void I830EmitFlush(ScrnInfoPtr pScrn);
extern void I830InitVideo(ScreenPtr pScreen); extern void I830InitVideo(ScreenPtr pScreen);
extern void i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on);
extern xf86CrtcPtr i830_covering_crtc (ScrnInfoPtr pScrn, BoxPtr box, extern xf86CrtcPtr i830_covering_crtc (ScrnInfoPtr pScrn, BoxPtr box,
xf86CrtcPtr desired, xf86CrtcPtr desired,
BoxPtr crtc_box_ret); BoxPtr crtc_box_ret);
int
i830_crtc_pipe (xf86CrtcPtr crtc);
extern xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe); extern xf86CrtcPtr i830_pipe_to_crtc(ScrnInfoPtr pScrn, int pipe);
Bool
i830_pipe_a_require_activate (ScrnInfoPtr scrn);
void
i830_pipe_a_require_deactivate (ScrnInfoPtr scrn);
Bool I830DRI2ScreenInit(ScreenPtr pScreen); Bool I830DRI2ScreenInit(ScreenPtr pScreen);
void I830DRI2CloseScreen(ScreenPtr pScreen); void I830DRI2CloseScreen(ScreenPtr pScreen);
@ -699,17 +429,6 @@ drmmode_crtc_set_cursor_bo(xf86CrtcPtr crtc, dri_bo *cursor);
extern Bool i830_crtc_on(xf86CrtcPtr crtc); extern Bool i830_crtc_on(xf86CrtcPtr crtc);
extern int i830_crtc_to_pipe(xf86CrtcPtr crtc); extern int i830_crtc_to_pipe(xf86CrtcPtr crtc);
extern Bool I830AccelInit(ScreenPtr pScreen); extern Bool I830AccelInit(ScreenPtr pScreen);
extern void I830SetupForScreenToScreenCopy(ScrnInfoPtr pScrn, int xdir,
int ydir, int rop,
unsigned int planemask,
int trans_color);
extern void I830SubsequentScreenToScreenCopy(ScrnInfoPtr pScrn, int srcX,
int srcY, int dstX, int dstY,
int w, int h);
extern void I830SetupForSolidFill(ScrnInfoPtr pScrn, int color, int rop,
unsigned int planemask);
extern void I830SubsequentSolidFillRect(ScrnInfoPtr pScrn, int x, int y,
int w, int h);
Bool i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size); Bool i830_allocator_init(ScrnInfoPtr pScrn, unsigned long size);
void i830_allocator_fini(ScrnInfoPtr pScrn); void i830_allocator_fini(ScrnInfoPtr pScrn);
@ -722,9 +441,7 @@ void i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity,
void i830_reset_allocations(ScrnInfoPtr pScrn); void i830_reset_allocations(ScrnInfoPtr pScrn);
void i830_free_3d_memory(ScrnInfoPtr pScrn); void i830_free_3d_memory(ScrnInfoPtr pScrn);
void i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem); void i830_free_memory(ScrnInfoPtr pScrn, i830_memory *mem);
extern long I830CheckAvailableMemory(ScrnInfoPtr pScrn);
Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn); Bool i830_allocate_2d_memory(ScrnInfoPtr pScrn);
Bool i830_allocate_pwrctx(ScrnInfoPtr pScrn);
Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn); Bool i830_allocate_3d_memory(ScrnInfoPtr pScrn);
void i830_init_bufmgr(ScrnInfoPtr pScrn); void i830_init_bufmgr(ScrnInfoPtr pScrn);
#ifdef INTEL_XVMC #ifdef INTEL_XVMC
@ -732,8 +449,6 @@ Bool i830_allocate_xvmc_buffer(ScrnInfoPtr pScrn, const char *name,
i830_memory **buffer, unsigned long size, int flags); i830_memory **buffer, unsigned long size, int flags);
void i830_free_xvmc_buffer(ScrnInfoPtr pScrn, i830_memory *buffer); void i830_free_xvmc_buffer(ScrnInfoPtr pScrn, i830_memory *buffer);
#endif #endif
extern uint32_t i830_create_new_fb(ScrnInfoPtr pScrn, int width, int height,
int *pitch);
Bool Bool
i830_tiled_width(I830Ptr i830, int *width, int cpp); i830_tiled_width(I830Ptr i830, int *width, int cpp);
@ -741,45 +456,15 @@ i830_tiled_width(I830Ptr i830, int *width, int cpp);
int int
i830_pad_drawable_width(int width, int cpp); i830_pad_drawable_width(int width, int cpp);
extern Bool I830I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg,
char *name);
/* i830_display.c */
Bool
i830PipeHasType (xf86CrtcPtr crtc, int type);
/* i830_crt.c */
void i830_crt_init(ScrnInfoPtr pScrn);
/* i830_dvo.c */
void i830_dvo_init(ScrnInfoPtr pScrn);
/* i830_hdmi.c */
void i830_hdmi_init(ScrnInfoPtr pScrn, int output_reg);
/* i830_lvds.c */
void i830_lvds_init(ScrnInfoPtr pScrn);
/* i830_memory.c */ /* i830_memory.c */
Bool i830_bind_all_memory(ScrnInfoPtr pScrn); Bool i830_bind_all_memory(ScrnInfoPtr pScrn);
Bool i830_unbind_all_memory(ScrnInfoPtr pScrn);
unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size); unsigned long i830_get_fence_size(I830Ptr pI830, unsigned long size);
unsigned long i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format); unsigned long i830_get_fence_pitch(I830Ptr pI830, unsigned long pitch, int format);
void i830_set_max_gtt_map_size(ScrnInfoPtr pScrn); void i830_set_max_gtt_map_size(ScrnInfoPtr pScrn);
Bool I830BindAGPMemory(ScrnInfoPtr pScrn);
Bool I830UnbindAGPMemory(ScrnInfoPtr pScrn);
i830_memory * i830_memory *
i830_allocate_framebuffer(ScrnInfoPtr pScrn); i830_allocate_framebuffer(ScrnInfoPtr pScrn);
/* i830_modes.c */
DisplayModePtr i830_ddc_get_modes(xf86OutputPtr output);
/* i830_tv.c */
void i830_tv_init(ScrnInfoPtr pScrn);
/* i830_render.c */ /* i830_render.c */
Bool i830_check_composite(int op, PicturePtr pSrc, PicturePtr pMask, Bool i830_check_composite(int op, PicturePtr pSrc, PicturePtr pMask,
PicturePtr pDst); PicturePtr pDst);
@ -827,38 +512,6 @@ i830_get_transformed_coordinates_3d(int x, int y, PictTransformPtr transform,
void i830_enter_render(ScrnInfoPtr); void i830_enter_render(ScrnInfoPtr);
static inline void
i830_wait_ring_idle(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830WaitLpRing(pScrn, pI830->ring.mem->size - 8, 0);
}
static inline int i830_fb_compression_supported(I830Ptr pI830)
{
if (!IS_MOBILE(pI830))
return FALSE;
if (IS_I810(pI830) || IS_I815(pI830) || IS_I830(pI830))
return FALSE;
if (IS_IGD(pI830))
return FALSE;
if (IS_IGDNG(pI830))
return FALSE;
/* fbc depends on tiled surface.
*/
if (!pI830->tiling)
return FALSE;
/* We have not gotten FBC to work consistently on 965GM. Our best
* working theory right now is that FBC simply isn't reliable on
* that device. See this bug report for more details:
* https://bugs.freedesktop.org/show_bug.cgi?id=16257
*/
if (IS_I965GM(pI830))
return FALSE;
return TRUE;
}
#define I830FALLBACK(s, arg...) \ #define I830FALLBACK(s, arg...) \
do { \ do { \
if (I830PTR(pScrn)->fallback_debug) { \ if (I830PTR(pScrn)->fallback_debug) { \
@ -919,28 +572,9 @@ extern const int I830CopyROP[16];
/* Flags for memory allocation function */ /* Flags for memory allocation function */
#define NEED_PHYSICAL_ADDR 0x00000001 #define NEED_PHYSICAL_ADDR 0x00000001
#define ALIGN_BOTH_ENDS 0x00000002 #define ALIGN_BOTH_ENDS 0x00000002
#define NEED_NON_STOLEN 0x00000004
#define NEED_LIFETIME_FIXED 0x00000008
#define ALLOW_SHARING 0x00000010 #define ALLOW_SHARING 0x00000010
#define DISABLE_REUSE 0x00000020 #define DISABLE_REUSE 0x00000020
/* Chipset registers for VIDEO BIOS memory RW access */
#define _855_DRAM_RW_CONTROL 0x58
#define _845_DRAM_RW_CONTROL 0x90
#define DRAM_WRITE 0x33330000
/* quirk flag definition */
#define QUIRK_IGNORE_TV 0x00000001
#define QUIRK_IGNORE_LVDS 0x00000002
#define QUIRK_IGNORE_MACMINI_LVDS 0x00000004
#define QUIRK_PIPEA_FORCE 0x00000008
#define QUIRK_IVCH_NEED_DVOB 0x00000010
#define QUIRK_RESET_MODES 0x00000020
#define QUIRK_PFIT_SAFE 0x00000040
#define QUIRK_IGNORE_CRT 0x00000080
#define QUIRK_BROKEN_ACPI_LID 0x00000100
extern void i830_fixup_devices(ScrnInfoPtr);
/** /**
* Hints to CreatePixmap to tell the driver how the pixmap is going to be * Hints to CreatePixmap to tell the driver how the pixmap is going to be
* used. * used.

69
src/i830_accel.c
View File

@ -49,81 +49,12 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#include "i830_ring.h" #include "i830_ring.h"
#include "i915_drm.h" #include "i915_drm.h"
unsigned long
intel_get_pixmap_offset(PixmapPtr pPix)
{
ScreenPtr pScreen = pPix->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
return (unsigned long)pPix->devPrivate.ptr - (unsigned long)pI830->FbBase;
}
unsigned long unsigned long
intel_get_pixmap_pitch(PixmapPtr pPix) intel_get_pixmap_pitch(PixmapPtr pPix)
{ {
return (unsigned long)pPix->devKind; return (unsigned long)pPix->devKind;
} }
int
I830WaitLpRing(ScrnInfoPtr pScrn, int n, int timeout_millis)
{
I830Ptr pI830 = I830PTR(pScrn);
I830RingBuffer *ring = &pI830->ring;
int iters = 0;
unsigned int start = 0;
unsigned int now = 0;
int last_head = 0;
unsigned int first = 0;
/* If your system hasn't moved the head pointer in 2 seconds, I'm going to
* call it crashed.
*/
if (timeout_millis == 0)
timeout_millis = 2000;
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
ErrorF("I830WaitLpRing %d\n", n);
first = GetTimeInMillis();
}
while (ring->space < n) {
ring->head = INREG(LP_RING + RING_HEAD) & I830_HEAD_MASK;
ring->space = ring->head - (ring->tail + 8);
if (ring->space < 0)
ring->space += ring->mem->size;
iters++;
now = GetTimeInMillis();
if (start == 0 || now < start || ring->head != last_head) {
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL)
if (now > start)
ErrorF("space: %d wanted %d\n", ring->space, n);
start = now;
last_head = ring->head;
} else if (now - start > timeout_millis) {
ErrorF("Error in I830WaitLpRing(), timeout for %d seconds\n",
timeout_millis/1000);
ErrorF("space: %d wanted %d\n", ring->space, n);
pI830->uxa_driver = NULL;
FatalError("lockup\n");
}
DELAY(10);
}
if (I810_DEBUG & DEBUG_VERBOSE_ACCEL) {
now = GetTimeInMillis();
if (now - first) {
ErrorF("Elapsed %u ms\n", now - first);
ErrorF("space: %d wanted %d\n", ring->space, n);
}
}
return iters;
}
void void
I830Sync(ScrnInfoPtr pScrn) I830Sync(ScrnInfoPtr pScrn)
{ {

92
src/i830_batchbuffer.c
View File

@ -39,68 +39,6 @@
#include "i830_ring.h" #include "i830_ring.h"
#include "i915_drm.h" #include "i915_drm.h"
static int
intel_nondrm_exec(dri_bo *bo, unsigned int used, void *priv)
{
ScrnInfoPtr pScrn = priv;
I830Ptr pI830 = I830PTR(pScrn);
BEGIN_LP_RING(4);
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
OUT_RING(bo->offset);
OUT_RING(MI_NOOP);
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
return 0;
}
static int
intel_nondrm_exec_i830(dri_bo *bo, unsigned int used, void *priv)
{
ScrnInfoPtr pScrn = priv;
I830Ptr pI830 = I830PTR(pScrn);
BEGIN_LP_RING(4);
OUT_RING(MI_BATCH_BUFFER);
OUT_RING(bo->offset);
OUT_RING(bo->offset + pI830->batch_used - 4);
OUT_RING(MI_NOOP);
ADVANCE_LP_RING();
return 0;
}
/**
* Creates a fence value representing a request to be passed.
*
* Stub implementation that should be avoided when DRM functions are available.
*/
static unsigned int
intel_nondrm_emit(void *priv)
{
static unsigned int fence = 0;
/* Match DRM in not using half the range. The fake bufmgr relies on this. */
if (++fence >= 0x8000000)
fence = 1;
return fence;
}
/**
* Waits on a fence representing a request to be passed.
*
* Stub implementation that should be avoided when DRM functions are available.
*/
static void
intel_nondrm_wait(unsigned int fence, void *priv)
{
ScrnInfoPtr pScrn = priv;
i830_wait_ring_idle(pScrn);
}
static void static void
intel_next_batch(ScrnInfoPtr pScrn) intel_next_batch(ScrnInfoPtr pScrn)
{ {
@ -134,22 +72,6 @@ intel_batch_init(ScrnInfoPtr pScrn)
pI830->batch_emitting = 0; pI830->batch_emitting = 0;
intel_next_batch(pScrn); intel_next_batch(pScrn);
if (!pI830->have_gem) {
if (IS_I830(pI830) || IS_845G(pI830)) {
intel_bufmgr_fake_set_exec_callback(pI830->bufmgr,
intel_nondrm_exec_i830,
pScrn);
} else {
intel_bufmgr_fake_set_exec_callback(pI830->bufmgr,
intel_nondrm_exec,
pScrn);
}
intel_bufmgr_fake_set_fence_callback(pI830->bufmgr,
intel_nondrm_emit,
intel_nondrm_wait,
pScrn);
}
} }
void void
@ -178,17 +100,6 @@ intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
if (pI830->batch_used == 0) if (pI830->batch_used == 0)
return; return;
/* If we're not using GEM, then emit a flush after each batch buffer */
if (!pI830->have_gem && !flushed) {
int flags = MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE;
if (IS_I965G(pI830))
flags = 0;
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_FLUSH | flags;
pI830->batch_used += 4;
}
/* Emit a padding dword if we aren't going to be quad-word aligned. */ /* Emit a padding dword if we aren't going to be quad-word aligned. */
if ((pI830->batch_used & 4) == 0) { if ((pI830->batch_used & 4) == 0) {
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP; *(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = MI_NOOP;
@ -219,8 +130,7 @@ intel_batch_flush(ScrnInfoPtr pScrn, Bool flushed)
* blockhandler. We could set this less often, but it's probably not worth * blockhandler. We could set this less often, but it's probably not worth
* the work. * the work.
*/ */
if (pI830->have_gem) pI830->need_mi_flush = TRUE;
pI830->need_mi_flush = TRUE;
if (pI830->batch_flush_notify) if (pI830->batch_flush_notify)
pI830->batch_flush_notify (pScrn); pI830->batch_flush_notify (pScrn);

9
src/i830_batchbuffer.h
View File

@ -102,16 +102,9 @@ intel_batch_emit_reloc_pixmap(I830Ptr pI830, PixmapPtr pPixmap,
uint32_t delta) uint32_t delta)
{ {
dri_bo *bo = i830_get_pixmap_bo(pPixmap); dri_bo *bo = i830_get_pixmap_bo(pPixmap);
uint32_t offset;
assert(pI830->batch_ptr != NULL); assert(pI830->batch_ptr != NULL);
assert(intel_batch_space(pI830) >= 4); assert(intel_batch_space(pI830) >= 4);
if (bo) { intel_batch_emit_reloc(pI830, bo, read_domains, write_domain, delta);
intel_batch_emit_reloc(pI830, bo, read_domains, write_domain, delta);
return;
}
offset = intel_get_pixmap_offset(pPixmap);
*(uint32_t *)(pI830->batch_ptr + pI830->batch_used) = offset + delta;
pI830->batch_used += 4;
} }
#define OUT_BATCH(dword) intel_batch_emit_dword(pI830, dword) #define OUT_BATCH(dword) intel_batch_emit_dword(pI830, dword)

557
src/i830_crt.c
View File

@ -1,557 +0,0 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "xf86Modes.h"
#include "i830_display.h"
static void
i830_crt_dpms(xf86OutputPtr output, int mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t temp;
temp = INREG(ADPA);
temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
temp &= ~ADPA_DAC_ENABLE;
switch(mode) {
case DPMSModeOn:
temp |= ADPA_DAC_ENABLE;
break;
case DPMSModeStandby:
temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
break;
case DPMSModeSuspend:
temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
break;
case DPMSModeOff:
temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
break;
}
OUTREG(ADPA, temp);
}
static void
i830_crt_save (xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
pI830->saveADPA = INREG(ADPA);
}
static void
i830_crt_restore (xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
OUTREG(ADPA, pI830->saveADPA);
}
static int
i830_crt_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
int maxclock;
if (pMode->Flags & V_DBLSCAN)
return MODE_NO_DBLESCAN;
if (pMode->Clock < 25000)
return MODE_CLOCK_LOW;
if (!IS_I9XX(pI830))
maxclock = 350000;
else
maxclock = 400000;
if (pMode->Clock > maxclock)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
static Bool
i830_crt_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
return TRUE;
}
static void
i830_crt_mode_set(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcPtr crtc = output->crtc;
I830CrtcPrivatePtr i830_crtc = crtc->driver_private;
int dpll_md_reg;
uint32_t adpa, dpll_md;
if (i830_crtc->pipe == 0)
dpll_md_reg = DPLL_A_MD;
else
dpll_md_reg = DPLL_B_MD;
/*
* Disable separate mode multiplier used when cloning SDVO to CRT
* XXX this needs to be adjusted when we really are cloning
*/
if (IS_I965G(pI830))
{
dpll_md = INREG(dpll_md_reg);
OUTREG(dpll_md_reg, dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
}
adpa = 0;
if (adjusted_mode->Flags & V_PHSYNC)
adpa |= ADPA_HSYNC_ACTIVE_HIGH;
if (adjusted_mode->Flags & V_PVSYNC)
adpa |= ADPA_VSYNC_ACTIVE_HIGH;
if (i830_crtc->pipe == 0)
{
adpa |= ADPA_PIPE_A_SELECT;
OUTREG(BCLRPAT_A, 0);
}
else
{
adpa |= ADPA_PIPE_B_SELECT;
OUTREG(BCLRPAT_B, 0);
}
OUTREG(ADPA, adpa);
}
/**
* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
*
* Only for I945G/GM.
*
* \return TRUE if CRT is connected.
* \return FALSE if CRT is disconnected.
*/
static Bool
i830_crt_detect_hotplug(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t hotplug_en, temp;
const int timeout_ms = 1000;
int starttime, curtime;
int tries = 1;
int try;
/* On 4 series desktop, CRT detect sequence need to be done twice
* to get a reliable result. */
if (IS_G4X(pI830) && !IS_GM45(pI830))
tries = 2;
else
tries = 1;
hotplug_en = INREG(PORT_HOTPLUG_EN);
hotplug_en &= CRT_FORCE_HOTPLUG_MASK;
/* This starts the detection sequence */
hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
/* GM45 requires a longer activation period to reliably
* detect CRT
*/
if (IS_G4X(pI830))
hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
/* Use the default voltage value */
hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
for (try = 0; try < tries; try++) {
/* turn FORCE_DETECT on */
OUTREG(PORT_HOTPLUG_EN, hotplug_en);
/* wait for FORCE_DETECT to go off */
for (curtime = starttime = GetTimeInMillis();
(curtime - starttime) < timeout_ms;
curtime = GetTimeInMillis())
{
temp = INREG(PORT_HOTPLUG_EN);
if ((temp & CRT_HOTPLUG_FORCE_DETECT) == 0)
break;
}
}
/* Check the status to see if both blue and green are on now */
temp = INREG(PORT_HOTPLUG_STAT);
return ((temp & CRT_HOTPLUG_MONITOR_MASK) ==
CRT_HOTPLUG_MONITOR_COLOR);
}
/**
* Detects CRT presence by checking for load.
*
* Requires that the current pipe's DPLL is active. This will cause flicker
* on the CRT, so it should not be used while the display is being used. Only
* color (not monochrome) displays are detected.
*
* \return TRUE if CRT is connected.
* \return FALSE if CRT is disconnected.
*/
static Bool
i830_crt_detect_load (xf86CrtcPtr crtc,
xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830CrtcPrivatePtr i830_crtc = I830CrtcPrivate(crtc);
uint32_t save_bclrpat;
uint32_t save_vtotal;
uint32_t vtotal, vactive;
uint32_t vsample;
uint32_t vblank, vblank_start, vblank_end;
uint32_t dsl;
uint8_t st00;
int bclrpat_reg, pipeconf_reg, pipe_dsl_reg;
int vtotal_reg, vblank_reg, vsync_reg;
int pipe = i830_crtc->pipe;
Bool present;
if (pipe == 0)
{
bclrpat_reg = BCLRPAT_A;
vtotal_reg = VTOTAL_A;
vblank_reg = VBLANK_A;
vsync_reg = VSYNC_A;
pipeconf_reg = PIPEACONF;
pipe_dsl_reg = PIPEA_DSL;
}
else
{
bclrpat_reg = BCLRPAT_B;
vtotal_reg = VTOTAL_B;
vblank_reg = VBLANK_B;
vsync_reg = VSYNC_B;
pipeconf_reg = PIPEBCONF;
pipe_dsl_reg = PIPEB_DSL;
}
save_bclrpat = INREG(bclrpat_reg);
save_vtotal = INREG(vtotal_reg);
vblank = INREG(vblank_reg);
vtotal = ((save_vtotal >> 16) & 0xfff) + 1;
vactive = (save_vtotal & 0x7ff) + 1;
vblank_start = (vblank & 0xfff) + 1;
vblank_end = ((vblank >> 16) & 0xfff) + 1;
/* Set the border color to purple. */
OUTREG(bclrpat_reg, 0x500050);
if (IS_I9XX (pI830))
{
uint32_t pipeconf = INREG(pipeconf_reg);
OUTREG(pipeconf_reg, pipeconf | PIPECONF_FORCE_BORDER);
/* Wait for next Vblank to substitue border color for Color info */
i830WaitForVblank (pScrn);
st00 = pI830->readStandard (pI830, 0x3c2);
present = (st00 & (1 << 4)) != 0;
OUTREG(pipeconf_reg, pipeconf);
}
else
{
Bool restore_vblank = FALSE;
int count, detect;
/*
* If there isn't any border, add some.
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal)
{
uint32_t vsync = INREG(vsync_reg);
uint32_t vsync_start = (vsync & 0xffff) + 1;
vblank_start = vsync_start;
OUTREG(vblank_reg, (vblank_start - 1) | ((vblank_end - 1) << 16));
restore_vblank = TRUE;
}
/* sample in the vertical border, selecting the larger one */
if (vblank_start - vactive >= vtotal - vblank_end)
vsample = (vblank_start + vactive) >> 1;
else
vsample = (vtotal + vblank_end) >> 1;
/*
* Wait for the border to be displayed
*/
while (INREG(pipe_dsl_reg) >= vactive)
;
while ((dsl = INREG(pipe_dsl_reg)) <= vsample)
;
/*
* Watch ST00 for an entire scanline
*/
detect = 0;
count = 0;
do {
count++;
/* Read the ST00 VGA status register */
st00 = pI830->readStandard(pI830, 0x3c2);
if (st00 & (1 << 4))
detect++;
} while ((INREG(pipe_dsl_reg) == dsl));
/* restore vblank if necessary */
if (restore_vblank)
OUTREG(vblank_reg, vblank);
/*
* If more than 3/4 of the scanline detected a monitor,
* then it is assumed to be present. This works even on i830,
* where there isn't any way to force the border color across
* the screen
*/
present = detect * 4 > count * 3;
}
/* Restore previous settings */
OUTREG(bclrpat_reg, save_bclrpat);
return present;
}
/**
* Detects CRT presence by probing for a response on the DDC address.
*
* This takes approximately 5ms in testing on an i915GM, with CRT connected or
* not.
*
* \return TRUE if the CRT is connected and responded to DDC.
* \return FALSE if no DDC response was detected.
*/
static Bool
i830_crt_detect_ddc(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr i830_output = output->driver_private;
Bool detect;
/* CRT should always be at 0, but check anyway */
if (i830_output->type != I830_OUTPUT_ANALOG)
return FALSE;
I830I2CInit(pScrn, &i830_output->pDDCBus, GPIOA, "CRTDDC_A");
detect = xf86I2CProbeAddress(i830_output->pDDCBus, 0x00A0);
xf86DestroyI2CBusRec(i830_output->pDDCBus, TRUE, TRUE);
return detect;
}
/**
* Attempts to detect CRT presence through any method available.
*
* @param allow_disturb enables detection methods that may cause flickering
* on active displays.
*/
static xf86OutputStatus
i830_crt_detect(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcPtr crtc;
int dpms_mode;
xf86OutputStatus status;
Bool connected;
/*
* Try hotplug detection where supported
*/
if (IS_I945G(pI830) || IS_I945GM(pI830) || IS_I965G(pI830) ||
IS_G33CLASS(pI830)) {
if (i830_crt_detect_hotplug(output))
status = XF86OutputStatusConnected;
else
status = XF86OutputStatusDisconnected;
goto done;
}
/*
* DDC is next best, no flicker
*/
crtc = i830GetLoadDetectPipe (output, NULL, &dpms_mode);
if (!crtc)
return XF86OutputStatusUnknown;
if (i830_crt_detect_ddc(output)) {
status = XF86OutputStatusConnected;
goto out_release_pipe;
}
/* Use the load-detect method if we have no other way of telling. */
connected = i830_crt_detect_load (crtc, output);
if (connected)
status = XF86OutputStatusConnected;
else
status = XF86OutputStatusDisconnected;
out_release_pipe:
i830ReleaseLoadDetectPipe (output, dpms_mode);
done:
return status;
}
static void
i830_crt_destroy (xf86OutputPtr output)
{
if (output->driver_private)
xfree (output->driver_private);
}
#ifdef RANDR_GET_CRTC_INTERFACE
static xf86CrtcPtr
i830_crt_get_crtc(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
int pipe = !!(INREG(ADPA) & ADPA_PIPE_SELECT_MASK);
return i830_pipe_to_crtc(pScrn, pipe);
}
#endif
static xf86MonPtr
i830_get_edid(xf86OutputPtr output, int gpio_reg, char *gpio_str)
{
I830OutputPrivatePtr intel_output = output->driver_private;
xf86MonPtr edid_mon = NULL;
/* Set up the DDC bus. */
I830I2CInit(output->scrn, &intel_output->pDDCBus, gpio_reg, gpio_str);
edid_mon = xf86OutputGetEDID (output, intel_output->pDDCBus);
if (!edid_mon || DIGITAL(edid_mon->features.input_type)) {
xf86DestroyI2CBusRec(intel_output->pDDCBus, TRUE, TRUE);
intel_output->pDDCBus = NULL;
if (edid_mon) {
xfree(edid_mon);
edid_mon = NULL;
}
}
return edid_mon;
}
static DisplayModePtr
i830_crt_get_modes (xf86OutputPtr output)
{
DisplayModePtr modes;
xf86MonPtr edid_mon = NULL;
I830OutputPrivatePtr intel_output = output->driver_private;
/* Try to probe normal CRT port, and also digital port for output
in DVI-I mode. */
if ((edid_mon = i830_get_edid(output, GPIOA, "CRTDDC_A")))
goto found;
if ((edid_mon = i830_get_edid(output, GPIOD, "CRTDDC_D")))
goto found;
if ((edid_mon = i830_get_edid(output, GPIOE, "CRTDDC_E")))
goto found;
found:
/* Destroy DDC bus after probe, so every other new probe will
scan all ports again */
if (intel_output->pDDCBus)
xf86DestroyI2CBusRec(intel_output->pDDCBus, TRUE, TRUE);
xf86OutputSetEDID (output, edid_mon);
modes = xf86OutputGetEDIDModes (output);
return modes;
}
static const xf86OutputFuncsRec i830_crt_output_funcs = {
.dpms = i830_crt_dpms,
.save = i830_crt_save,
.restore = i830_crt_restore,
.mode_valid = i830_crt_mode_valid,
.mode_fixup = i830_crt_mode_fixup,
.prepare = i830_output_prepare,
.mode_set = i830_crt_mode_set,
.commit = i830_output_commit,
.detect = i830_crt_detect,
.get_modes = i830_crt_get_modes,
.destroy = i830_crt_destroy,
#ifdef RANDR_GET_CRTC_INTERFACE
.get_crtc = i830_crt_get_crtc,
#endif
};
void
i830_crt_init(ScrnInfoPtr pScrn)
{
xf86OutputPtr output;
I830OutputPrivatePtr i830_output;
I830Ptr pI830 = I830PTR(pScrn);
if (pI830->quirk_flag & QUIRK_IGNORE_CRT)
return;
output = xf86OutputCreate (pScrn, &i830_crt_output_funcs, "VGA");
if (!output)
return;
i830_output = xnfcalloc (sizeof (I830OutputPrivateRec), 1);
if (!i830_output)
{
xf86OutputDestroy (output);
return;
}
i830_output->type = I830_OUTPUT_ANALOG;
/* i830 (almador) cannot place the analog adaptor on pipe B */
if (IS_I830(pI830))
i830_output->pipe_mask = (1 << 0);
else
i830_output->pipe_mask = ((1 << 0) | (1 << 1));
i830_output->clone_mask = ((1 << I830_OUTPUT_ANALOG) |
(1 << I830_OUTPUT_DVO_TMDS));
output->driver_private = i830_output;
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;
}

307
src/i830_cursor.c
View File

@ -1,307 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
/**************************************************************************
Copyright 1998-1999 Precision Insight, Inc., Cedar Park, Texas.
Copyright © 2002 David Dawes
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Keith Whitwell <keith@tungstengraphics.com>
* David Dawes <dawes@xfree86.org>
*
* Updated for Dual Head capabilities:
* Alan Hourihane <alanh@tungstengraphics.com>
*
* Add ARGB HW cursor support:
* Alan Hourihane <alanh@tungstengraphics.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <string.h>
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "xf86fbman.h"
#include "i830.h"
static void
I830SetPipeCursorBase (xf86CrtcPtr crtc)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
int pipe = intel_crtc->pipe;
I830Ptr pI830 = I830PTR(pScrn);
int cursor_base;
cursor_base = (pipe == 0) ? CURSOR_A_BASE : CURSOR_B_BASE;
if (intel_crtc->cursor_is_argb)
OUTREG(cursor_base, intel_crtc->cursor_argb_addr);
else
OUTREG(cursor_base, intel_crtc->cursor_addr);
}
void
I830InitHWCursor(ScrnInfoPtr pScrn)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
I830Ptr pI830 = I830PTR(pScrn);
uint32_t temp;
int i;
DPRINTF(PFX, "I830InitHWCursor\n");
if (!IS_I9XX(pI830))
OUTREG(CURSOR_SIZE, (I810_CURSOR_Y << 12) | I810_CURSOR_X);
/* Initialise the HW cursor registers, leaving the cursor hidden. */
for (i = 0; i < xf86_config->num_crtc; i++)
{
int cursor_control = i == 0 ? CURSOR_A_CONTROL : CURSOR_B_CONTROL;
temp = INREG(cursor_control);
if (IS_MOBILE(pI830) || IS_I9XX(pI830))
{
temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE |
MCURSOR_MEM_TYPE_LOCAL |
MCURSOR_PIPE_SELECT);
temp |= (i << 28);
temp |= CURSOR_MODE_DISABLE;
}
else
{
temp &= ~(CURSOR_ENABLE|CURSOR_GAMMA_ENABLE);
}
/* Need to set control, then address. */
OUTREG(cursor_control, temp);
I830SetPipeCursorBase(xf86_config->crtc[i]);
}
}
Bool
I830CursorInit(ScreenPtr pScreen)
{
return xf86_cursors_init (pScreen, I810_CURSOR_X, I810_CURSOR_Y,
(HARDWARE_CURSOR_TRUECOLOR_AT_8BPP |
HARDWARE_CURSOR_BIT_ORDER_MSBFIRST |
HARDWARE_CURSOR_INVERT_MASK |
HARDWARE_CURSOR_SWAP_SOURCE_AND_MASK |
HARDWARE_CURSOR_AND_SOURCE_WITH_MASK |
HARDWARE_CURSOR_SOURCE_MASK_INTERLEAVE_64 |
HARDWARE_CURSOR_UPDATE_UNHIDDEN |
HARDWARE_CURSOR_ARGB));
}
#ifdef ARGB_CURSOR
void
i830_crtc_load_cursor_argb (xf86CrtcPtr crtc, CARD32 *image)
{
I830Ptr pI830 = I830PTR(crtc->scrn);
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
uint32_t *pcurs;
pcurs = (uint32_t *) (pI830->FbBase + intel_crtc->cursor_argb_offset);
intel_crtc->cursor_is_argb = TRUE;
memcpy (pcurs, image, I810_CURSOR_Y * I810_CURSOR_X * 4);
}
#endif
void
i830_crtc_set_cursor_position (xf86CrtcPtr crtc, int x, int y)
{
ScrnInfoPtr scrn = crtc->scrn;
I830Ptr pI830 = I830PTR(scrn);
I830CrtcPrivatePtr intel_crtc = I830CrtcPrivate(crtc);
uint32_t temp;
temp = 0;
if (x < 0) {
temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
x = -x;
}
if (y < 0) {
temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
y = -y;
}
temp |= x << CURSOR_X_SHIFT;
temp |= y << CURSOR_Y_SHIFT;
switch (intel_crtc->pipe) {
case 0:
OUTREG(CURSOR_A_POSITION, temp);
break;
case 1:
OUTREG(CURSOR_B_POSITION, temp);
break;
}
if (crtc->cursor_shown)
I830SetPipeCursorBase (crtc);
}
void
i830_crtc_show_cursor (xf86CrtcPtr crtc)
{
ScrnInfoPtr scrn = crtc->scrn;
I830Ptr pI830 = I830PTR(scrn);
I830CrtcPrivatePtr intel_crtc = I830CrtcPrivate(crtc);
int pipe = intel_crtc->pipe;
uint32_t temp;
int cursor_control = (pipe == 0 ? CURSOR_A_CONTROL :
CURSOR_B_CONTROL);
temp = INREG(cursor_control);
if (IS_MOBILE(pI830) || IS_I9XX(pI830))
{
temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
if (intel_crtc->cursor_is_argb)
temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_MODE_64_4C_AX;
temp |= (pipe << 28); /* Connect to correct pipe */
}
else
{
temp &= ~(CURSOR_FORMAT_MASK);
temp |= CURSOR_ENABLE;
if (intel_crtc->cursor_is_argb)
temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
else
temp |= CURSOR_FORMAT_3C;
}
/* Need to set mode, then address. */
OUTREG(cursor_control, temp);
I830SetPipeCursorBase (crtc);
}
void
i830_crtc_hide_cursor (xf86CrtcPtr crtc)
{
ScrnInfoPtr scrn = crtc->scrn;
I830Ptr pI830 = I830PTR(scrn);
I830CrtcPrivatePtr intel_crtc = I830CrtcPrivate(crtc);
int pipe = intel_crtc->pipe;
uint32_t temp;
int cursor_control = (pipe == 0 ? CURSOR_A_CONTROL :
CURSOR_B_CONTROL);
temp = INREG(cursor_control);
if (IS_MOBILE(pI830) || IS_I9XX(pI830))
{
temp &= ~(CURSOR_MODE|MCURSOR_GAMMA_ENABLE);
temp |= CURSOR_MODE_DISABLE;
}
else
temp &= ~(CURSOR_ENABLE|CURSOR_GAMMA_ENABLE);
/* Need to set mode, then address. */
OUTREG(cursor_control, temp);
I830SetPipeCursorBase (crtc);
}
void
i830_crtc_set_cursor_colors (xf86CrtcPtr crtc, int bg, int fg)
{
ScrnInfoPtr scrn = crtc->scrn;
I830Ptr pI830 = I830PTR(scrn);
I830CrtcPrivatePtr intel_crtc = I830CrtcPrivate(crtc);
int pipe = intel_crtc->pipe;
int pal0 = pipe == 0 ? CURSOR_A_PALETTE0 : CURSOR_B_PALETTE0;
OUTREG(pal0 + 0, bg & 0x00ffffff);
OUTREG(pal0 + 4, fg & 0x00ffffff);
OUTREG(pal0 + 8, fg & 0x00ffffff);
OUTREG(pal0 + 12, bg & 0x00ffffff);
}
void
i830_update_cursor_offsets (ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int i;
if (pI830->cursor_mem) {
unsigned long cursor_offset_base = pI830->cursor_mem->offset;
unsigned long cursor_addr_base, offset = 0;
/* Single memory buffer for cursors */
if (pI830->CursorNeedsPhysical) {
/* On any hardware that requires physical addresses for cursors,
* the PTEs don't support memory above 4GB, so we can safely
* ignore the top 32 bits of cursor_mem->bus_addr.
*/
cursor_addr_base = (unsigned long)pI830->cursor_mem->bus_addr;
} else
cursor_addr_base = pI830->cursor_mem->offset;
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
intel_crtc->cursor_argb_addr = cursor_addr_base + offset;
intel_crtc->cursor_argb_offset = cursor_offset_base + offset;
offset += HWCURSOR_SIZE_ARGB;
intel_crtc->cursor_addr = cursor_addr_base + offset;
intel_crtc->cursor_offset = cursor_offset_base + offset;
offset += HWCURSOR_SIZE;
}
} else {
/* Separate allocations per cursor */
for (i = 0; i < xf86_config->num_crtc; i++) {
xf86CrtcPtr crtc = xf86_config->crtc[i];
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
if (pI830->CursorNeedsPhysical) {
intel_crtc->cursor_addr =
pI830->cursor_mem_classic[i]->bus_addr;
intel_crtc->cursor_argb_addr =
pI830->cursor_mem_argb[i]->bus_addr;
} else {
intel_crtc->cursor_addr =
pI830->cursor_mem_classic[i]->offset;
intel_crtc->cursor_argb_addr =
pI830->cursor_mem_argb[i]->offset;
}
intel_crtc->cursor_offset = pI830->cursor_mem_classic[i]->offset;
intel_crtc->cursor_argb_offset = pI830->cursor_mem_argb[i]->offset;
}
}
}

2367
src/i830_display.c
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File diff suppressed because it is too large Load Diff

1
src/i830_display.h
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@ -32,7 +32,6 @@ void i830PipeSetBase(xf86CrtcPtr crtc, int x, int y);
void i830WaitForVblank(ScrnInfoPtr pScrn); void i830WaitForVblank(ScrnInfoPtr pScrn);
void i830DescribeOutputConfiguration(ScrnInfoPtr pScrn); void i830DescribeOutputConfiguration(ScrnInfoPtr pScrn);
void i830_set_new_crtc_bo(ScrnInfoPtr pScrn); void i830_set_new_crtc_bo(ScrnInfoPtr pScrn);
void i830_crtc_disable(xf86CrtcPtr crtc, Bool disable_pipe);
xf86CrtcPtr i830GetLoadDetectPipe(xf86OutputPtr output, DisplayModePtr mode, int *dpms_mode); xf86CrtcPtr i830GetLoadDetectPipe(xf86OutputPtr output, DisplayModePtr mode, int *dpms_mode);
void i830ReleaseLoadDetectPipe(xf86OutputPtr output, int dpms_mode); void i830ReleaseLoadDetectPipe(xf86OutputPtr output, int dpms_mode);

6
src/i830_dri.c
View File

@ -126,8 +126,7 @@ I830DRI2CreateBuffers(DrawablePtr pDraw, unsigned int *attachments, int count)
break; break;
} }
if (!pI830->tiling || if (!pI830->tiling)
(!IS_I965G(pI830) && !pI830->kernel_exec_fencing))
hint = 0; hint = 0;
pPixmap = (*pScreen->CreatePixmap)(pScreen, pPixmap = (*pScreen->CreatePixmap)(pScreen,
@ -204,8 +203,7 @@ I830DRI2CreateBuffer(DrawablePtr pDraw, unsigned int attachment,
break; break;
} }
if (!pI830->tiling || if (!pI830->tiling)
(!IS_I965G(pI830) && !pI830->kernel_exec_fencing))
hint = 0; hint = 0;
pPixmap = (*pScreen->CreatePixmap)(pScreen, pPixmap = (*pScreen->CreatePixmap)(pScreen,

1655
src/i830_driver.c
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File diff suppressed because it is too large Load Diff

521
src/i830_dvo.c
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@ -1,521 +0,0 @@
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
******
********************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "i830_display.h"
#include "i810_reg.h"
#include "sil164/sil164.h"
#include "ch7xxx/ch7xxx.h"
#include "tfp410/tfp410.h"
/* driver list */
static struct _I830DVODriver i830_dvo_drivers[] =
{
{
.type = I830_OUTPUT_DVO_TMDS,
.modulename = "sil164",
.fntablename = "SIL164VidOutput",
.dvo_reg = DVOC,
.address = (SIL164_ADDR_1<<1),
},
{
.type = I830_OUTPUT_DVO_TMDS,
.modulename = "ch7xxx",
.fntablename = "CH7xxxVidOutput",
.dvo_reg = DVOC,
.address = (CH7xxx_ADDR_1<<1),
},
{
.type = I830_OUTPUT_DVO_LVDS,
.modulename = "ivch",
.fntablename = "ivch_methods",
.dvo_reg = DVOA,
.address = 0x04, /* Might also be 0x44, 0x84, 0xc4 */
},
{
.type = I830_OUTPUT_DVO_TMDS,
.modulename = "tfp410",
.fntablename = "TFP410VidOutput",
.dvo_reg = DVOC,
.address = (TFP410_ADDR_1<<1),
},
{
.type = I830_OUTPUT_DVO_LVDS,
.modulename = "ch7017",
.fntablename = "ch7017_methods",
.dvo_reg = DVOC,
.address = 0xea,
.gpio = GPIOE,
}
};
#define I830_NUM_DVO_DRIVERS (sizeof(i830_dvo_drivers)/sizeof(struct _I830DVODriver))
static void
i830_dvo_dpms(xf86OutputPtr output, int mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct _I830DVODriver *drv = intel_output->i2c_drv;
void * dev_priv = drv->dev_priv;
unsigned int dvo_reg = drv->dvo_reg;
if (mode == DPMSModeOn) {
OUTREG(dvo_reg, INREG(dvo_reg) | DVO_ENABLE);
POSTING_READ(dvo_reg);
(*intel_output->i2c_drv->vid_rec->dpms)(dev_priv, mode);
} else {
(*intel_output->i2c_drv->vid_rec->dpms)(dev_priv, mode);
OUTREG(dvo_reg, INREG(dvo_reg) & ~DVO_ENABLE);
POSTING_READ(dvo_reg);
}
}
static void
i830_dvo_save(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
void * dev_priv = intel_output->i2c_drv->dev_priv;
/* Each output should probably just save the registers it touches, but for
* now, use more overkill.
*/
pI830->saveDVOA = INREG(DVOA);
pI830->saveDVOB = INREG(DVOB);
pI830->saveDVOC = INREG(DVOC);
(*intel_output->i2c_drv->vid_rec->save)(dev_priv);
}
static void
i830_dvo_restore(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
void * dev_priv = intel_output->i2c_drv->dev_priv;
(*intel_output->i2c_drv->vid_rec->restore)(dev_priv);
OUTREG(DVOA, pI830->saveDVOA);
OUTREG(DVOB, pI830->saveDVOB);
OUTREG(DVOC, pI830->saveDVOC);
}
static int
i830_dvo_mode_valid(xf86OutputPtr output, DisplayModePtr pMode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
void *dev_priv = intel_output->i2c_drv->dev_priv;
if (pMode->Flags & V_DBLSCAN)
return MODE_NO_DBLESCAN;
/* XXX: Validate clock range */
if (pI830->lvds_fixed_mode) {
if (pMode->HDisplay > pI830->lvds_fixed_mode->HDisplay)
return MODE_PANEL;
if (pMode->VDisplay > pI830->lvds_fixed_mode->VDisplay)
return MODE_PANEL;
}
return intel_output->i2c_drv->vid_rec->mode_valid(dev_priv, pMode);
}
static Bool
i830_dvo_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
/* If we have timings from the BIOS for the panel, put them in
* to the adjusted mode. The CRTC will be set up for this mode,
* with the panel scaling set up to source from the H/VDisplay
* of the original mode.
*/
if (pI830->lvds_fixed_mode != NULL) {
adjusted_mode->HDisplay = pI830->lvds_fixed_mode->HDisplay;
adjusted_mode->HSyncStart = pI830->lvds_fixed_mode->HSyncStart;
adjusted_mode->HSyncEnd = pI830->lvds_fixed_mode->HSyncEnd;
adjusted_mode->HTotal = pI830->lvds_fixed_mode->HTotal;
adjusted_mode->VDisplay = pI830->lvds_fixed_mode->VDisplay;
adjusted_mode->VSyncStart = pI830->lvds_fixed_mode->VSyncStart;
adjusted_mode->VSyncEnd = pI830->lvds_fixed_mode->VSyncEnd;
adjusted_mode->VTotal = pI830->lvds_fixed_mode->VTotal;
adjusted_mode->Clock = pI830->lvds_fixed_mode->Clock;
xf86SetModeCrtc(adjusted_mode, INTERLACE_HALVE_V);
}
if (intel_output->i2c_drv->vid_rec->mode_fixup)
return intel_output->i2c_drv->vid_rec->mode_fixup (intel_output->i2c_drv->dev_priv,
mode, adjusted_mode);
return TRUE;
}
static void
i830_dvo_mode_set(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcPtr crtc = output->crtc;
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
I830OutputPrivatePtr intel_output = output->driver_private;
struct _I830DVODriver *drv = intel_output->i2c_drv;
int pipe = intel_crtc->pipe;
uint32_t dvo;
unsigned int dvo_reg = drv->dvo_reg, dvo_srcdim_reg;
int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
switch (dvo_reg) {
case DVOA:
default:
dvo_srcdim_reg = DVOA_SRCDIM;
break;
case DVOB:
dvo_srcdim_reg = DVOB_SRCDIM;
break;
case DVOC:
dvo_srcdim_reg = DVOC_SRCDIM;
break;
}
intel_output->i2c_drv->vid_rec->mode_set(intel_output->i2c_drv->dev_priv,
mode, adjusted_mode);
/* Save the data order, since I don't know what it should be set to. */
dvo = INREG(dvo_reg) & (DVO_PRESERVE_MASK | DVO_DATA_ORDER_GBRG);
dvo |= DVO_DATA_ORDER_FP | DVO_BORDER_ENABLE | DVO_BLANK_ACTIVE_HIGH;
if (pipe == 1)
dvo |= DVO_PIPE_B_SELECT;
dvo |= DVO_PIPE_STALL;
if (adjusted_mode->Flags & V_PHSYNC)
dvo |= DVO_HSYNC_ACTIVE_HIGH;
if (adjusted_mode->Flags & V_PVSYNC)
dvo |= DVO_VSYNC_ACTIVE_HIGH;
OUTREG(dpll_reg, INREG(dpll_reg) | DPLL_DVO_HIGH_SPEED);
/*OUTREG(DVOB_SRCDIM,
(adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));*/
OUTREG(dvo_srcdim_reg,
(adjusted_mode->HDisplay << DVO_SRCDIM_HORIZONTAL_SHIFT) |
(adjusted_mode->VDisplay << DVO_SRCDIM_VERTICAL_SHIFT));
/*OUTREG(DVOB, dvo);*/
OUTREG(dvo_reg, dvo);
}
/**
* Detect the output connection on our DVO device.
*
* Unimplemented.
*/
static xf86OutputStatus
i830_dvo_detect(xf86OutputPtr output)
{
I830OutputPrivatePtr intel_output = output->driver_private;
void *dev_priv = intel_output->i2c_drv->dev_priv;
return intel_output->i2c_drv->vid_rec->detect(dev_priv);
}
static DisplayModePtr
i830_dvo_get_modes(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
DisplayModePtr modes;
/* We should probably have an i2c driver get_modes function for those
* devices which will have a fixed set of modes determined by the chip
* (TV-out, for example), but for now with just TMDS and LVDS, that's not
* the case.
*/
modes = i830_ddc_get_modes(output);
if (modes != NULL)
return modes;
if (intel_output->i2c_drv->vid_rec->get_modes)
{
modes = intel_output->i2c_drv->vid_rec->get_modes (intel_output->i2c_drv->dev_priv);
if (modes != NULL)
return modes;
}
if (pI830->lvds_fixed_mode != NULL)
return xf86DuplicateMode(pI830->lvds_fixed_mode);
return NULL;
}
static void
i830_dvo_destroy (xf86OutputPtr output)
{
I830OutputPrivatePtr intel_output = output->driver_private;
if (intel_output)
{
if (intel_output->i2c_drv->vid_rec->destroy)
intel_output->i2c_drv->vid_rec->destroy (intel_output->i2c_drv->dev_priv);
if (intel_output->pI2CBus)
xf86DestroyI2CBusRec (intel_output->pI2CBus, TRUE, TRUE);
if (intel_output->pDDCBus)
xf86DestroyI2CBusRec (intel_output->pDDCBus, TRUE, TRUE);
xfree (intel_output);
}
}
#ifdef RANDR_GET_CRTC_INTERFACE
static xf86CrtcPtr
i830_dvo_get_crtc(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct _I830DVODriver *drv = intel_output->i2c_drv;
int pipe = !!(INREG(drv->dvo_reg) & SDVO_PIPE_B_SELECT);
return i830_pipe_to_crtc(pScrn, pipe);
}
#endif
static const xf86OutputFuncsRec i830_dvo_output_funcs = {
.dpms = i830_dvo_dpms,
.save = i830_dvo_save,
.restore = i830_dvo_restore,
.mode_valid = i830_dvo_mode_valid,
.mode_fixup = i830_dvo_mode_fixup,
.prepare = i830_output_prepare,
.mode_set = i830_dvo_mode_set,
.commit = i830_output_commit,
.detect = i830_dvo_detect,
.get_modes = i830_dvo_get_modes,
.destroy = i830_dvo_destroy,
#ifdef RANDR_GET_CRTC_INTERFACE
.get_crtc = i830_dvo_get_crtc,
#endif
};
/**
* Attempts to get a fixed panel timing for LVDS (currently only the i830).
*
* Other chips with DVO LVDS will need to extend this to deal with the LVDS
* chip being on DVOB/C and having multiple pipes.
*/
static DisplayModePtr
i830_dvo_get_current_mode (xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
I830Ptr pI830 = I830PTR(pScrn);
struct _I830DVODriver *drv = intel_output->i2c_drv;
unsigned int dvo_reg = drv->dvo_reg;
uint32_t dvo = INREG(dvo_reg);
DisplayModePtr mode = NULL;
/* If the DVO port is active, that'll be the LVDS, so we can pull out
* its timings to get how the BIOS set up the panel.
*/
if (dvo & DVO_ENABLE)
{
xf86CrtcConfigPtr xf86_config = XF86_CRTC_CONFIG_PTR(pScrn);
int pipe = (dvo & DVO_PIPE_B_SELECT) ? 1 : 0;
int c;
for (c = 0; c < xf86_config->num_crtc; c++)
{
xf86CrtcPtr crtc = xf86_config->crtc[c];
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
if (intel_crtc->pipe == pipe)
{
mode = i830_crtc_mode_get(pScrn, crtc);
if (mode)
{
mode->type |= M_T_PREFERRED;
if (dvo & DVO_HSYNC_ACTIVE_HIGH)
mode->Flags |= V_PHSYNC;
if (dvo & DVO_VSYNC_ACTIVE_HIGH)
mode->Flags |= V_PVSYNC;
}
break;
}
}
}
return mode;
}
void
i830_dvo_init(ScrnInfoPtr pScrn)
{
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output;
int ret;
int i;
void *ret_ptr;
struct _I830DVODriver *drv;
int gpio_inited = 0;
I2CBusPtr pI2CBus = NULL;
intel_output = xnfcalloc (sizeof (I830OutputPrivateRec), 1);
if (!intel_output)
return;
/* Set up the DDC bus */
ret = I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOD, "DVODDC_D");
if (!ret) {
xfree(intel_output);
return;
}
/* Now, try to find a controller */
for (i = 0; i < I830_NUM_DVO_DRIVERS; i++) {
int gpio;
drv = &i830_dvo_drivers[i];
drv->modhandle = xf86LoadSubModule(pScrn, drv->modulename);
if (drv->modhandle == NULL)
continue;
ret_ptr = NULL;
drv->vid_rec = LoaderSymbol(drv->fntablename);
if (!strcmp(drv->modulename, "ivch") &&
pI830->quirk_flag & QUIRK_IVCH_NEED_DVOB) {
drv->dvo_reg = DVOB;
}
/* Allow the I2C driver info to specify the GPIO to be used in
* special cases, but otherwise default to what's defined in the spec.
*/
if (drv->gpio != 0)
gpio = drv->gpio;
else if (drv->type == I830_OUTPUT_DVO_LVDS)
gpio = GPIOB;
else
gpio = GPIOE;
/* Set up the I2C bus necessary for the chip we're probing. It appears
* that everything is on GPIOE except for panels on i830 laptops, which
* are on GPIOB (DVOA).
*/
if (gpio_inited != gpio) {
if (pI2CBus != NULL)
xf86DestroyI2CBusRec(pI2CBus, TRUE, TRUE);
if (!I830I2CInit(pScrn, &pI2CBus, gpio,
gpio == GPIOB ? "DVOI2C_B" : "DVOI2C_E")) {
continue;
}
}
if (drv->vid_rec != NULL)
ret_ptr = drv->vid_rec->init(pI2CBus, drv->address);
if (ret_ptr != NULL) {
xf86OutputPtr output = NULL;
intel_output->type = drv->type;
switch (drv->type) {
case I830_OUTPUT_DVO_TMDS:
intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = ((1 << I830_OUTPUT_ANALOG) |
(1 << I830_OUTPUT_DVO_TMDS));
output = xf86OutputCreate(pScrn, &i830_dvo_output_funcs,
"TMDS");
break;
case I830_OUTPUT_DVO_LVDS:
intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = (1 << I830_OUTPUT_DVO_LVDS);
output = xf86OutputCreate(pScrn, &i830_dvo_output_funcs,
"LVDS");
break;
case I830_OUTPUT_DVO_TVOUT:
intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = (1 << I830_OUTPUT_DVO_TVOUT);
output = xf86OutputCreate(pScrn, &i830_dvo_output_funcs,
"TV");
break;
}
if (output == NULL) {
xf86DestroyI2CBusRec(pI2CBus, TRUE, TRUE);
xf86DestroyI2CBusRec(intel_output->pDDCBus, TRUE, TRUE);
xfree(intel_output);
xf86UnloadSubModule(drv->modhandle);
return;
}
output->driver_private = intel_output;
output->subpixel_order = SubPixelHorizontalRGB;
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;
drv->dev_priv = ret_ptr;
intel_output->i2c_drv = drv;
intel_output->pI2CBus = pI2CBus;
if (intel_output->type == I830_OUTPUT_DVO_LVDS) {
/* For our LVDS chipsets, we should hopefully be able to
* dig the fixed panel mode out of the BIOS data. However,
* it's in a different format from the BIOS data on chipsets
* with integrated LVDS (stored in AIM headers, liekly),
* so for now, just get the current mode being output through
* DVO.
*/
pI830->lvds_fixed_mode = i830_dvo_get_current_mode(output);
pI830->lvds_dither = TRUE;
}
return;
}
xf86UnloadSubModule(drv->modhandle);
}
/* Didn't find a chip, so tear down. */
if (pI2CBus != NULL)
xf86DestroyI2CBusRec(pI2CBus, TRUE, TRUE);
xf86DestroyI2CBusRec(intel_output->pDDCBus, TRUE, TRUE);
xfree(intel_output);
}

368
src/i830_hdmi.c
View File

@ -1,368 +0,0 @@
/*
* Copyright © 2007 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "i830.h"
#include "xf86Modes.h"
#include "i830_display.h"
#include "X11/Xatom.h"
struct i830_hdmi_priv {
uint32_t output_reg;
uint32_t save_SDVO;
Bool has_hdmi_sink;
/* Default 0 for full RGB range 0-255, 1 is for RGB range 16-235 */
uint32_t broadcast_rgb;
};
static Atom broadcast_atom;
static int
i830_hdmi_mode_valid(xf86OutputPtr output, DisplayModePtr mode)
{
if (mode->Clock > 165000)
return MODE_CLOCK_HIGH;
if (mode->Clock < 20000)
return MODE_CLOCK_LOW;
return MODE_OK;
}
static Bool
i830_hdmi_mode_fixup(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
/* The HDMI output doesn't need the pixel multiplication that SDVO does,
* so no fixup.
*/
return TRUE;
}
static void
i830_hdmi_mode_set(xf86OutputPtr output, DisplayModePtr mode,
DisplayModePtr adjusted_mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
I830Ptr pI830 = I830PTR(pScrn);
xf86CrtcPtr crtc = output->crtc;
I830CrtcPrivatePtr intel_crtc = crtc->driver_private;
uint32_t sdvox;
sdvox = SDVO_ENCODING_HDMI |
SDVO_BORDER_ENABLE |
SDVO_VSYNC_ACTIVE_HIGH |
SDVO_HSYNC_ACTIVE_HIGH;
if (dev_priv->has_hdmi_sink)
sdvox |= SDVO_AUDIO_ENABLE;
if (intel_crtc->pipe == 1)
sdvox |= SDVO_PIPE_B_SELECT;
OUTREG(dev_priv->output_reg, sdvox);
POSTING_READ(dev_priv->output_reg);
}
static void
i830_hdmi_dpms(xf86OutputPtr output, int mode)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t temp;
if (mode == DPMSModeOff) {
temp = INREG(dev_priv->output_reg);
OUTREG(dev_priv->output_reg, temp & ~SDVO_ENABLE);
} else {
temp = INREG(dev_priv->output_reg);
OUTREG(dev_priv->output_reg, temp | SDVO_ENABLE);
}
}
static void
i830_hdmi_save(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
I830Ptr pI830 = I830PTR(pScrn);
dev_priv->save_SDVO = INREG(dev_priv->output_reg);
}
static void
i830_hdmi_restore(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
I830Ptr pI830 = I830PTR(pScrn);
OUTREG(dev_priv->output_reg, dev_priv->save_SDVO);
}
/**
* Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect HDMI connection.
*
* \return TRUE if HDMI port is connected.
* \return FALSE if HDMI port is disconnected.
*/
static xf86OutputStatus
i830_hdmi_detect(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
I830Ptr pI830 = I830PTR(pScrn);
uint32_t temp, bit;
xf86OutputStatus status;
xf86MonPtr edid_mon;
dev_priv->has_hdmi_sink = FALSE;
/* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 0xd.
* Failure to do so will result in spurious interrupts being
* generated on the port when a cable is not attached.
*/
if (IS_G4X(pI830) && !IS_GM45(pI830)) {
temp = INREG(PEG_BAND_GAP_DATA);
OUTREG(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
}
temp = INREG(PORT_HOTPLUG_EN);
switch (dev_priv->output_reg) {
case SDVOB:
temp |= HDMIB_HOTPLUG_INT_EN;
break;
case SDVOC:
temp |= HDMIC_HOTPLUG_INT_EN;
break;
default:
return XF86OutputStatusUnknown;
}
OUTREG(PORT_HOTPLUG_EN, temp);
POSTING_READ(PORT_HOTPLUG_EN);
i830WaitForVblank(pScrn);
switch (dev_priv->output_reg) {
case SDVOB:
bit = HDMIB_HOTPLUG_INT_STATUS;
break;
case SDVOC:
bit = HDMIC_HOTPLUG_INT_STATUS;
break;
default:
return XF86OutputStatusUnknown;
}
if ((INREG(PORT_HOTPLUG_STAT) & bit) != 0)
status = XF86OutputStatusConnected;
else
return XF86OutputStatusDisconnected;
edid_mon = xf86OutputGetEDID (output, intel_output->pDDCBus);
if (!edid_mon || !DIGITAL(edid_mon->features.input_type))
status = XF86OutputStatusDisconnected;
if (xf86LoaderCheckSymbol("xf86MonitorIsHDMI") &&
xf86MonitorIsHDMI(edid_mon))
dev_priv->has_hdmi_sink = TRUE;
if (pI830->debug_modes)
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"%s monitor detected on HDMI-%d\n",
dev_priv->has_hdmi_sink ? "HDMI" : "DVI",
(dev_priv->output_reg == SDVOB) ? 1 : 2);
xfree(edid_mon);
return status;
}
static void
i830_hdmi_destroy (xf86OutputPtr output)
{
I830OutputPrivatePtr intel_output = output->driver_private;
if (intel_output != NULL) {
xf86DestroyI2CBusRec(intel_output->pDDCBus, FALSE, FALSE);
xfree(intel_output);
}
}
static void
i830_hdmi_create_resources(xf86OutputPtr output)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
INT32 broadcast_range[2];
int err;
/* only R G B are 8bit color mode */
if (pScrn->depth != 24 ||
/* only 965G and G4X platform */
!(IS_I965G(pI830) || IS_G4X(pI830)))
return;
broadcast_atom =
MakeAtom("BROADCAST_RGB", sizeof("BROADCAST_RGB") - 1, TRUE);
broadcast_range[0] = 0;
broadcast_range[1] = 1;
err = RRConfigureOutputProperty(output->randr_output,
broadcast_atom,
FALSE, TRUE, FALSE, 2, broadcast_range);
if (err != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRConfigureOutputProperty error, %d\n", err);
return;
}
/* Set the current value of the broadcast property as full range */
dev_priv->broadcast_rgb = 0;
err = RRChangeOutputProperty(output->randr_output,
broadcast_atom,
XA_INTEGER, 32, PropModeReplace,
1, &dev_priv->broadcast_rgb,
FALSE, TRUE);
if (err != 0) {
xf86DrvMsg(pScrn->scrnIndex, X_ERROR,
"RRChangeOutputProperty error, %d\n", err);
return;
}
}
static Bool
i830_hdmi_set_property(xf86OutputPtr output, Atom property,
RRPropertyValuePtr value)
{
ScrnInfoPtr pScrn = output->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830OutputPrivatePtr intel_output = output->driver_private;
struct i830_hdmi_priv *dev_priv = intel_output->dev_priv;
uint32_t temp;
if (property == broadcast_atom) {
uint32_t val;
if (value->type != XA_INTEGER || value->format != 32 ||
value->size != 1)
{
return FALSE;
}
val = *(INT32 *)value->data;
if (val < 0 || val > 1)
{
return FALSE;
}
if (val == dev_priv->broadcast_rgb)
return TRUE;
temp = INREG(dev_priv->output_reg);
if (val == 1)
temp |= SDVO_COLOR_NOT_FULL_RANGE;
else if (val == 0)
temp &= ~SDVO_COLOR_NOT_FULL_RANGE;
OUTREG(dev_priv->output_reg, temp);
dev_priv->broadcast_rgb = val;
}
return TRUE;
}
static const xf86OutputFuncsRec i830_hdmi_output_funcs = {
.create_resources = i830_hdmi_create_resources,
.dpms = i830_hdmi_dpms,
.save = i830_hdmi_save,
.restore = i830_hdmi_restore,
.mode_valid = i830_hdmi_mode_valid,
.mode_fixup = i830_hdmi_mode_fixup,
.prepare = i830_output_prepare,
.mode_set = i830_hdmi_mode_set,
.commit = i830_output_commit,
.detect = i830_hdmi_detect,
.get_modes = i830_ddc_get_modes,
.set_property = i830_hdmi_set_property,
.destroy = i830_hdmi_destroy
};
void
i830_hdmi_init(ScrnInfoPtr pScrn, int output_reg)
{
xf86OutputPtr output;
I830OutputPrivatePtr intel_output;
struct i830_hdmi_priv *dev_priv;
output = xf86OutputCreate(pScrn, &i830_hdmi_output_funcs,
(output_reg == SDVOB) ? "HDMI-1" : "HDMI-2");
if (!output)
return;
intel_output = xnfcalloc(sizeof (I830OutputPrivateRec) +
sizeof (struct i830_hdmi_priv), 1);
if (intel_output == NULL) {
xf86OutputDestroy(output);
return;
}
output->driver_private = intel_output;
output->interlaceAllowed = FALSE;
output->doubleScanAllowed = FALSE;
dev_priv = (struct i830_hdmi_priv *)(intel_output + 1);
dev_priv->output_reg = output_reg;
dev_priv->has_hdmi_sink = FALSE;
intel_output->dev_priv = dev_priv;
intel_output->type = I830_OUTPUT_HDMI;
intel_output->pipe_mask = ((1 << 0) | (1 << 1));
intel_output->clone_mask = (1 << I830_OUTPUT_HDMI);
/* Set up the DDC bus. */
if (output_reg == SDVOB)
I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOE, "HDMIDDC_B");
else
I830I2CInit(pScrn, &intel_output->pDDCBus, GPIOD, "HDMIDDC_C");
xf86DrvMsg(pScrn->scrnIndex, X_INFO,
"HDMI output %d detected\n",
(output_reg == SDVOB) ? 1 : 2);
}

4
src/i830_hwmc.c
View File

@ -55,8 +55,8 @@ Bool intel_xvmc_probe(ScrnInfoPtr pScrn)
if (!pI830->XvMCEnabled) if (!pI830->XvMCEnabled)
return FALSE; return FALSE;
if (pI830->use_drm_mode && /* Needs KMS support. */
(IS_I915G(pI830) || IS_I915GM(pI830))) if (IS_I915G(pI830) || IS_I915GM(pI830))
return FALSE; return FALSE;
if (IS_I9XX(pI830)) { if (IS_I9XX(pI830)) {

392
src/i830_i2c.c
View File

@ -1,392 +0,0 @@
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "xf86cmap.h"
#include "compiler.h"
#include "mibstore.h"
#include "vgaHW.h"
#include "mipointer.h"
#include "micmap.h"
#include "shadowfb.h"
#include <X11/extensions/randr.h>
#include "fb.h"
#include "miscstruct.h"
#include "xf86xv.h"
#include <X11/extensions/Xv.h>
#include "shadow.h"
#include "i830.h"
#define AIRLIED_I2C 0
#if AIRLIED_I2C
#define I2C_TIMEOUT(x) /*(x)*/ /* Report timeouts */
#define I2C_TRACE(x) /*(x)*/ /* Report progress */
static void i830_setscl(I2CBusPtr b, int state)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t val;
OUTREG(b->DriverPrivate.uval,
(state ? GPIO_CLOCK_VAL_OUT : 0) | GPIO_CLOCK_DIR_OUT |
GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_VAL_MASK);
val = INREG(b->DriverPrivate.uval);
}
static void i830_setsda(I2CBusPtr b, int state)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t val;
OUTREG(b->DriverPrivate.uval,
(state ? GPIO_DATA_VAL_OUT : 0) | GPIO_DATA_DIR_OUT |
GPIO_DATA_DIR_MASK | GPIO_DATA_VAL_MASK);
val = INREG(b->DriverPrivate.uval);
}
static void i830_getscl(I2CBusPtr b, int *state)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t val;
OUTREG(b->DriverPrivate.uval, GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK);
OUTREG(b->DriverPrivate.uval, 0);
val = INREG(b->DriverPrivate.uval);
*state = ((val & GPIO_CLOCK_VAL_IN) != 0);
}
static int i830_getsda(I2CBusPtr b)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t val;
OUTREG(b->DriverPrivate.uval, GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK);
OUTREG(b->DriverPrivate.uval, 0);
val = INREG(b->DriverPrivate.uval);
return ((val & GPIO_DATA_VAL_IN) != 0);
}
static inline void sdalo(I2CBusPtr b)
{
i830_setsda(b, 0);
b->I2CUDelay(b, b->RiseFallTime);
}
static inline void sdahi(I2CBusPtr b)
{
i830_setsda(b, 1);
b->I2CUDelay(b, b->RiseFallTime);
}
static inline void scllo(I2CBusPtr b)
{
i830_setscl(b, 0);
b->I2CUDelay(b, b->RiseFallTime);
}
static inline int sclhi(I2CBusPtr b, int timeout)
{
int scl = 0;
int i;
i830_setscl(b, 1);
b->I2CUDelay(b, b->RiseFallTime);
for (i = timeout; i > 0; i -= b->RiseFallTime) {
i830_getscl(b, &scl);
if (scl) break;
b->I2CUDelay(b, b->RiseFallTime);
}
if (i <= 0) {
I2C_TIMEOUT(ErrorF("[I2CRaiseSCL(<%s>, %d) timeout]",
b->BusName, timeout));
return FALSE;
}
return TRUE;
}
static Bool
I830I2CGetByte(I2CDevPtr d, I2CByte *data, Bool last)
{
I2CBusPtr b = d->pI2CBus;
int i, sda;
unsigned char indata = 0;
sdahi(b);
for (i = 0; i < 8; i++) {
if (sclhi(b, d->BitTimeout) == FALSE) {
I2C_TRACE(ErrorF("timeout at bit #%d\n", 7-i));
return FALSE;
};
indata *= 2;
if (i830_getsda(b))
indata |= 0x01;
scllo(b);
}
if (last) {
sdahi(b);
} else {
sdalo(b);
}
if (sclhi(b, d->BitTimeout) == FALSE) {
sdahi(b);
return FALSE;
};
scllo(b);
sdahi(b);
*data = indata & 0xff;
I2C_TRACE(ErrorF("R%02x ", (int) *data));
return TRUE;
}
static Bool
I830I2CPutByte(I2CDevPtr d, I2CByte c)
{
Bool r;
int i, scl, sda;
int sb, ack;
I2CBusPtr b = d->pI2CBus;
for (i = 7; i >= 0; i--) {
sb = c & (1 << i);
i830_setsda(b, sb);
b->I2CUDelay(b, b->RiseFallTime);
if (sclhi(b, d->ByteTimeout) == FALSE) {
sdahi(b);
return FALSE;
}
i830_setscl(b, 0);
b->I2CUDelay(b, b->RiseFallTime);
}
sdahi(b);
if (sclhi(b, d->ByteTimeout) == FALSE) {
I2C_TIMEOUT(ErrorF("[I2CPutByte(<%s>, 0x%02x, %d, %d, %d) timeout]",
b->BusName, c, d->BitTimeout,
d->ByteTimeout, d->AcknTimeout));
return FALSE;
}
ack = i830_getsda(b);
I2C_TRACE(ErrorF("Put byte 0x%02x , getsda() = %d\n", c & 0xff, ack));
scllo(b);
return (0 == ack);
}
static Bool
I830I2CStart(I2CBusPtr b, int timeout)
{
if (sclhi(b, timeout) == FALSE)
return FALSE;
sdalo(b);
scllo(b);
return TRUE;
}
static void
I830I2CStop(I2CDevPtr d)
{
I2CBusPtr b = d->pI2CBus;
sdalo(b);
sclhi(b, d->ByteTimeout);
sdahi(b);
}
static Bool
I830I2CAddress(I2CDevPtr d, I2CSlaveAddr addr)
{
if (I830I2CStart(d->pI2CBus, d->StartTimeout)) {
if (I830I2CPutByte(d, addr & 0xFF)) {
if ((addr & 0xF8) != 0xF0 &&
(addr & 0xFE) != 0x00)
return TRUE;
if (I830I2CPutByte(d, (addr >> 8) & 0xFF))
return TRUE;
}
I830I2CStop(d);
}
return FALSE;
}
#else
#define I2C_DEBUG 0
#if I2C_DEBUG
static Bool first = TRUE;
#endif
static void
i830I2CGetBits(I2CBusPtr b, int *clock, int *data)
{
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
uint32_t val;
val = INREG(b->DriverPrivate.uval);
/*
* to read valid data, we must have written a 1 to
* the associated bit. Writing a 1 is done by
* tri-stating the bus in PutBits, so we needn't make
* sure that is true here
*/
*data = (val & GPIO_DATA_VAL_IN) != 0;
*clock = (val & GPIO_CLOCK_VAL_IN) != 0;
#if I2C_DEBUG
ErrorF("Getting %s: %c %c\n", b->BusName,
*clock ? '^' : 'v',
*data ? '^' : 'v');
#endif
}
static void
i830I2CPutBits(I2CBusPtr b, int clock, int data)
{
uint32_t reserved = 0;
uint32_t data_bits, clock_bits;
#if I2C_DEBUG
int cur_clock, cur_data;
#endif
ScrnInfoPtr pScrn = xf86Screens[b->scrnIndex];
I830Ptr pI830 = I830PTR(pScrn);
#if I2C_DEBUG
i830I2CGetBits(b, &cur_clock, &cur_data);
if (first) {
ErrorF("%s Debug: C D C D\n", b->BusName);
first = FALSE;
}
ErrorF("Setting %s 0x%08x to: %c %c\n", b->BusName,
(int)b->DriverPrivate.uval,
clock ? '^' : 'v',
data ? '^' : 'v');
#endif
if (!IS_I830(pI830) && !IS_845G(pI830)) {
/* On most chips, these bits must be preserved in software. */
reserved = INREG(b->DriverPrivate.uval) &
(GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
}
/* data or clock == 1 means to tristate the bus. otherwise, drive it low */
if (data)
data_bits = GPIO_DATA_DIR_IN|GPIO_DATA_DIR_MASK;
else
data_bits = GPIO_DATA_DIR_OUT|GPIO_DATA_DIR_MASK|GPIO_DATA_VAL_MASK;
if (clock)
clock_bits = GPIO_CLOCK_DIR_IN|GPIO_CLOCK_DIR_MASK;
else
clock_bits = GPIO_CLOCK_DIR_OUT|GPIO_CLOCK_DIR_MASK|GPIO_CLOCK_VAL_MASK;
OUTREG(b->DriverPrivate.uval, reserved | data_bits | clock_bits);
POSTING_READ(b->DriverPrivate.uval);
}
#endif
/* the i830 has a number of I2C Buses */
Bool
I830I2CInit(ScrnInfoPtr pScrn, I2CBusPtr *bus_ptr, int i2c_reg, char *name)
{
I2CBusPtr pI2CBus;
I830Ptr pI830 = I830PTR(pScrn);
pI2CBus = xf86CreateI2CBusRec();
if (!pI2CBus)
return FALSE;
pI2CBus->BusName = name;
pI2CBus->scrnIndex = pScrn->scrnIndex;
#if AIRLIED_I2C
pI2CBus->I2CGetByte = I830I2CGetByte;
pI2CBus->I2CPutByte = I830I2CPutByte;
pI2CBus->I2CStart = I830I2CStart;
pI2CBus->I2CStop = I830I2CStop;
pI2CBus->I2CAddress = I830I2CAddress;
#else
pI2CBus->I2CGetBits = i830I2CGetBits;
pI2CBus->I2CPutBits = i830I2CPutBits;
#endif
pI2CBus->DriverPrivate.uval = i2c_reg;
/* Assume all busses are used for DDCish stuff */
/*
* These were set incorrectly in the server pre-1.3, Having
* duplicate settings is sub-optimal, but this lets the driver
* work with older servers
*/
pI2CBus->ByteTimeout = 2200; /* VESA DDC spec 3 p. 43 (+10 %) */
pI2CBus->StartTimeout = 550;
pI2CBus->BitTimeout = 40;
pI2CBus->AcknTimeout = 40;
pI2CBus->RiseFallTime = 20;
/* Disable the GMBUS, which we won't use. If it is left enabled (for
* example, by Mac Mini EFI initialization), GPIO access to the pins it
* uses gets disabled.
*/
OUTREG(GMBUS0, 0);
if (!xf86I2CBusInit(pI2CBus))
return FALSE;
*bus_ptr = pI2CBus;
return TRUE;
}

35
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@ -1,35 +0,0 @@
/**************************************************************************
Copyright 2005 Red Hat, Inc.
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL RED HAT, INC AND/OR ITS SUPPLIERS BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
/*
* Authors:
* Kristian Høgsberg <krh@redhat.com>
*
*/
#define BUILD_FOR_I830 1
#include "i810_io.c"

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src/i830_memory.c
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69
src/i830_modes.c
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@ -1,69 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
#define DEBUG_VERB 2
/*
* Copyright © 2002 David Dawes
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the author(s) shall
* not be used in advertising or otherwise to promote the sale, use or other
* dealings in this Software without prior written authorization from
* the author(s).
*
* Authors: David Dawes <dawes@xfree86.org>
* Eric Anholt <eric.anholt@intel.com>
*
*/
/*
* Modified by Alan Hourihane <alanh@tungstengraphics.com>
* to support extended BIOS modes for the Intel chipsets
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdio.h>
#include <string.h>
#include <assert.h>
#include <math.h>
#include "xf86.h"
#include "xf86DDC.h"
#include "X11/Xatom.h"
#include "i830.h"
#include "i830_display.h"
#include "xf86Modes.h"
#include <randrstr.h>
DisplayModePtr
i830_ddc_get_modes (xf86OutputPtr output)
{
I830OutputPrivatePtr intel_output = output->driver_private;
xf86MonPtr edid_mon;
DisplayModePtr modes;
edid_mon = xf86OutputGetEDID (output, intel_output->pDDCBus);
xf86OutputSetEDID (output, edid_mon);
modes = xf86OutputGetEDIDModes (output);
return modes;
}

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@ -1,430 +0,0 @@
/*
* Copyright © 2007 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Zhenyu Wang <zhenyu.z.wang@intel.com>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "i830.h"
#define SUBSYS_ANY (~0)
#define DMIID_DIR "/sys/class/dmi/id/"
#define DMIID_FILE(x) (DMIID_DIR # x)
typedef struct {
int chipType;
int subsysVendor;
int subsysCard;
void (*hook)(I830Ptr);
} i830_quirk, *i830_quirk_ptr;
enum i830_dmi_data_t {
bios_vendor,
bios_version,
bios_date,
sys_vendor,
product_name,
product_version,
product_serial,
product_uuid,
board_vendor,
board_name,
board_version,
board_serial,
board_asset_tag,
chassis_vendor,
chassis_type,
chassis_version,
chassis_serial,
chassis_asset_tag,
dmi_data_max,
};
static char *i830_dmi_data[dmi_data_max];
#define I830_DMI_FIELD_FUNC(field) \
static void i830_dmi_store_##field(void) \
{\
FILE *f = NULL;\
int ret;\
f = fopen(DMIID_FILE(field), "r");\
if (f == NULL) {\
xfree(i830_dmi_data[field]); i830_dmi_data[field] = NULL;\
return;\
}\
ret = fread(i830_dmi_data[field], 64, 1, f); \
fclose(f);\
}
I830_DMI_FIELD_FUNC(bios_vendor);
I830_DMI_FIELD_FUNC(bios_version);
I830_DMI_FIELD_FUNC(bios_date);
I830_DMI_FIELD_FUNC(sys_vendor);
I830_DMI_FIELD_FUNC(product_name);
I830_DMI_FIELD_FUNC(product_version);
I830_DMI_FIELD_FUNC(product_serial);
I830_DMI_FIELD_FUNC(product_uuid);
I830_DMI_FIELD_FUNC(board_vendor);
I830_DMI_FIELD_FUNC(board_name);
I830_DMI_FIELD_FUNC(board_version);
I830_DMI_FIELD_FUNC(board_serial);
I830_DMI_FIELD_FUNC(board_asset_tag);
I830_DMI_FIELD_FUNC(chassis_vendor);
I830_DMI_FIELD_FUNC(chassis_type);
I830_DMI_FIELD_FUNC(chassis_version);
I830_DMI_FIELD_FUNC(chassis_serial);
I830_DMI_FIELD_FUNC(chassis_asset_tag);
static void i830_dmi_scan(void)
{
int i;
for (i = 0; i < dmi_data_max; i++) {
i830_dmi_data[i] = xcalloc(64, sizeof(char));
if (!i830_dmi_data[i]) {
int j;
for (j = 0; j < i; j++) {
xfree(i830_dmi_data[j]);
i830_dmi_data[i] = NULL;
}
return;
}
}
i830_dmi_store_bios_vendor();
i830_dmi_store_bios_version();
i830_dmi_store_bios_date();
i830_dmi_store_sys_vendor();
i830_dmi_store_product_name();
i830_dmi_store_product_version();
i830_dmi_store_product_serial();
i830_dmi_store_product_uuid();
i830_dmi_store_board_vendor();
i830_dmi_store_board_name();
i830_dmi_store_board_version();
i830_dmi_store_board_serial();
i830_dmi_store_board_asset_tag();
i830_dmi_store_chassis_vendor();
i830_dmi_store_chassis_type();
i830_dmi_store_chassis_version();
i830_dmi_store_chassis_serial();
i830_dmi_store_chassis_asset_tag();
}
#define DMIID_DUMP(field) \
ErrorF("\t" # field ": %s", i830_dmi_data[field] ?\
i830_dmi_data[field] : "unknown")
static void i830_dmi_dump(void)
{
ErrorF("i830_dmi_dump:\n");
DMIID_DUMP(bios_vendor);
DMIID_DUMP(bios_version);
DMIID_DUMP(bios_date);
DMIID_DUMP(sys_vendor);
DMIID_DUMP(product_name);
DMIID_DUMP(product_version);
DMIID_DUMP(product_serial);
DMIID_DUMP(product_uuid);
DMIID_DUMP(board_vendor);
DMIID_DUMP(board_name);
DMIID_DUMP(board_version);
DMIID_DUMP(board_serial);
DMIID_DUMP(board_asset_tag);
DMIID_DUMP(chassis_vendor);
DMIID_DUMP(chassis_type);
DMIID_DUMP(chassis_version);
DMIID_DUMP(chassis_serial);
DMIID_DUMP(chassis_asset_tag);
}
/*
* Old chips have undocumented panel fitting registers. Some of them actually
* work; this quirk indicates that.
*/
static void quirk_pfit_safe (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_PFIT_SAFE;
}
/*
* Some machines hose the display regs regardless of the ACPI DOS
* setting, so we need to reset modes at ACPI event time.
*/
static void quirk_reset_modes (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_RESET_MODES;
}
static void quirk_pipea_force (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_PIPEA_FORCE;
}
static void quirk_ignore_tv (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
static void quirk_ignore_lvds (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_LVDS;
}
static void quirk_ignore_crt (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_CRT;
}
static void quirk_mac_mini (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IGNORE_MACMINI_LVDS;
}
static void quirk_lenovo_tv_dmi (I830Ptr pI830)
{
/* X60, X60s has no TV output.
* Z61 has S-video TV output.
* And they have same subsys ids...
*
* http://www-307.ibm.com/pc/support/site.wss/MIGR-45120.html
* http://www.thinkwiki.org/wiki/List_of_DMI_IDs
*/
if (!i830_dmi_data[bios_version]) {
ErrorF("Failed to load DMI info, X60 TV quirk not applied.\n");
return;
}
if (!strncmp(i830_dmi_data[bios_version], "7B", 2) || /* X60, X60s */
!strncmp(i830_dmi_data[bios_version], "7E", 2)) /* R60e */
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
static void quirk_msi_lvds_dmi (I830Ptr pI830)
{
/* MSI IM-945GSE-A has no TV output, nor a LVDS connection.
*/
if (!i830_dmi_data[board_name]) {
ErrorF("Failed to load DMI info, MSI LVDS quirk not applied.\n");
return;
}
if (!strncmp(i830_dmi_data[board_name],"A9830IMS",8)) {
pI830->quirk_flag |= QUIRK_IGNORE_LVDS;
pI830->quirk_flag |= QUIRK_IGNORE_TV;
}
}
static void quirk_ibase_lvds (I830Ptr pI830)
{
if (!i830_dmi_data[board_name]) {
ErrorF("Failed to load DMI info, iBase LVDS quirk not applied.\n");
return;
}
if (!strncmp(i830_dmi_data[board_name], "i855-W83627HF", 13)) {
pI830->quirk_flag |= QUIRK_IGNORE_LVDS;
}
}
static void quirk_ivch_dvob (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_IVCH_NEED_DVOB;
}
/* For broken hw/bios for incorrect acpi _LID state that
can't be fixed with customed DSDT or other way */
static void quirk_broken_acpi_lid (I830Ptr pI830)
{
pI830->quirk_flag |= QUIRK_BROKEN_ACPI_LID;
}
/* keep this list sorted by OEM, then by chip ID */
static i830_quirk i830_quirk_list[] = {
/* Aopen mini pc */
{ PCI_CHIP_I915_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_I945_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_I965_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_GM45_GM, 0xa0a0, SUBSYS_ANY, quirk_ignore_lvds },
{ PCI_CHIP_I965_GM, 0x8086, 0x1999, quirk_ignore_lvds },
/* Apple Mac mini has no lvds, but macbook pro does */
{ PCI_CHIP_I945_GM, 0x8086, 0x7270, quirk_mac_mini },
/* Transtec Senyo 610 mini pc */
{ PCI_CHIP_I965_GM, 0x1509, 0x2f15, quirk_ignore_lvds },
/* Clevo M720R has no tv output */
{ PCI_CHIP_I965_GM, 0x1558, 0x0721, quirk_ignore_tv },
/* Dell Latitude X1 */
{ PCI_CHIP_I915_GM, 0x1028, 0x01a3, quirk_ignore_tv },
/* Dell Latitude X1 / D630 (LP: #197740) */
{ PCI_CHIP_I915_GM, 0x1028, 0x01f9, quirk_ignore_tv },
/* Dell XPS 1330 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0209, quirk_ignore_tv },
/* Dell Inspiron 1535 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0254, quirk_ignore_tv },
/* Dell Inspiron 1735 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0256, quirk_ignore_tv },
/* Dell Inspiron 1318 */
{ PCI_CHIP_I965_GM, 0x1028, 0x0286, quirk_ignore_tv },
/* Dell Vostro A840 (LP: #235155) */
{ PCI_CHIP_I965_GM, 0x1028, 0x0298, quirk_ignore_tv },
/* Dell Studio Hybrid */
{ PCI_CHIP_I965_GM, 0x1028, 0x0279, quirk_ignore_lvds },
/* Lenovo Napa TV (use dmi)*/
{ PCI_CHIP_I945_GM, 0x17aa, SUBSYS_ANY, quirk_lenovo_tv_dmi },
/* Lenovo 3000 v200 */
{ PCI_CHIP_I965_GM, 0x17aa, 0x3c18, quirk_ignore_tv },
/* MSI IM-945GSE-A has no LVDS or TV (use dmi) */
{ PCI_CHIP_I945_GME, 0x8086, 0x27ae, quirk_msi_lvds_dmi },
/* Panasonic Toughbook CF-Y4 has no TV output */
{ PCI_CHIP_I915_GM, 0x10f7, 0x8338, quirk_ignore_tv },
/* Panasonic Toughbook CF-Y7 has no TV output */
{ PCI_CHIP_I965_GM, 0x10f7, 0x8338, quirk_ignore_tv },
/* Toshiba Satellite U300 has no TV output */
{ PCI_CHIP_I965_GM, 0x1179, 0xff50, quirk_ignore_tv },
/* Toshiba i830M laptop (fix bug 11148) */
{ PCI_CHIP_I830_M, 0x1179, 0xff00, quirk_ivch_dvob },
/* Motion Computing M1200 reported on irc */
{ PCI_CHIP_I830_M, 0x14c0, 0x0012, quirk_ivch_dvob },
/* Samsung Q35 has no TV output */
{ PCI_CHIP_I945_GM, 0x144d, 0xc504, quirk_ignore_tv },
/* Samsung Q45 has no TV output */
{ PCI_CHIP_I965_GM, 0x144d, 0xc510, quirk_ignore_tv },
/* HP Compaq nx6110 has no TV output */
{ PCI_CHIP_I915_GM, 0x103c, 0x099c, quirk_ignore_tv },
/* HP Compaq nx6310 has no TV output */
{ PCI_CHIP_I945_GM, 0x103c, 0x30aa, quirk_ignore_tv },
/* HP Compaq 6730s has no TV output */
{ PCI_CHIP_GM45_GM, 0x103c, 0x30e8, quirk_ignore_tv },
/* HP Compaq 2730p needs pipe A force quirk (LP: #291555) */
{ PCI_CHIP_GM45_GM, 0x103c, 0x30eb, quirk_pipea_force },
/* HP Mini needs pipe A force quirk (LP: #322104) */
{ PCI_CHIP_I945_GME,0x103c, 0x361a, quirk_pipea_force },
/* HP Mini 5101 needs pipe A force quirk */
{ PCI_CHIP_I945_GME,0x103c, 0x3632, quirk_pipea_force },
/* Thinkpad R31 needs pipe A force quirk */
{ PCI_CHIP_I830_M, 0x1014, 0x0505, quirk_pipea_force },
/* Dell Latitude D400 needs pipe A force quirk (LP: #228519) */
{ PCI_CHIP_I855_GM, 0x1028, 0x0139, quirk_pipea_force },
/* Dell Latitude D500 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0152, quirk_pipea_force },
/* Dell Latitude D505 needs pipe A force quirk (LP: #235643) */
{ PCI_CHIP_I855_GM, 0x1028, 0x0163, quirk_pipea_force },
/* Dell Latitude X300 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x014f, quirk_pipea_force },
/* Dell Inspiron 510m needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0164, quirk_pipea_force },
/* Toshiba Satellite A30 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1179, 0xff00 , quirk_pipea_force },
/* Toshiba Protege R-205, S-209 needs pipe A force quirk */
{ PCI_CHIP_I915_GM, 0x1179, 0x0001, quirk_pipea_force },
/* Intel 855GM hardware (See LP: #216490) */
{ PCI_CHIP_I855_GM, 0x1028, 0x00c8, quirk_pipea_force },
/* Intel 855GM hardware (See Novell Bugzilla #406123) */
{ PCI_CHIP_I855_GM, 0x10cf, 0x1215, quirk_pipea_force },
/* HP Pavilion ze4944ea needs pipe A force quirk (See LP: #242389) */
{ PCI_CHIP_I855_GM, 0x103c, 0x3084, quirk_pipea_force },
{ PCI_CHIP_I855_GM, 0x161f, 0x2030, quirk_pfit_safe },
/* ThinkPad X30 needs pipe A force quirk (LP: #304614) */
{ PCI_CHIP_I830_M, 0x1014, 0x0513, quirk_pipea_force },
/* ThinkPad X40 needs pipe A force quirk */
{ PCI_CHIP_I855_GM, 0x1014, 0x0557, quirk_pipea_force },
/* ThinkPad T60 needs pipe A force quirk (bug #16494) */
{ PCI_CHIP_I945_GM, 0x17aa, 0x201a, quirk_pipea_force },
/* Sony vaio PCG-r600HFP (fix bug 13722) */
{ PCI_CHIP_I830_M, 0x104d, 0x8100, quirk_ivch_dvob },
/* Sony vaio VGN-SZ4MN (See LP: #212163) */
{ PCI_CHIP_I830_M, 0x104d, 0x81e6, quirk_pipea_force },
/* Sony VGC-LT71DB has no VGA output (bug #17395) */
{ PCI_CHIP_I965_GM, 0x104d, 0x9018, quirk_ignore_crt },
/* Quanta Gigabyte W251U (See LP: #244242) */
{ PCI_CHIP_I945_GM, 0x152d, 0x0755, quirk_pipea_force },
/* Ordi Enduro UW31 (See LP: #152416) */
{ PCI_CHIP_I945_GM, 0x1584, 0x9900, quirk_ignore_tv },
/* Dell Latitude D500 needs reset modes quirk */
{ PCI_CHIP_I855_GM, 0x1028, 0x0152, quirk_reset_modes },
/* Littlebit Sepia X35 (rebranded Asus Z37E) (See LP: #201257) */
{ PCI_CHIP_I965_GM, 0x1043, 0x8265, quirk_ignore_tv },
/* 855 & before need to leave pipe A & dpll A up */
{ PCI_CHIP_I855_GM, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
{ PCI_CHIP_845_G, SUBSYS_ANY, SUBSYS_ANY, quirk_pipea_force },
/* Asus Eee Box has no LVDS */
{ PCI_CHIP_I945_GME, 0x1043, 0x1252, quirk_ignore_lvds },
/* #19239: Mirrus Centrino laptop */
{ PCI_CHIP_I915_GM, 0x1584, 0x9800, quirk_broken_acpi_lid },
/* #19529: iBase MB890 board */
{ PCI_CHIP_I855_GM, 0x8086, 0x3582, quirk_ibase_lvds },
{ 0, 0, 0, NULL },
};
void i830_fixup_devices(ScrnInfoPtr scrn)
{
I830Ptr pI830 = I830PTR(scrn);
i830_quirk_ptr p = i830_quirk_list;
int i;
i830_dmi_scan();
if (0)
i830_dmi_dump();
while (p && p->chipType != 0) {
if (DEVICE_ID(pI830->PciInfo) == p->chipType &&
(SUBVENDOR_ID(pI830->PciInfo) == p->subsysVendor ||
p->subsysVendor == SUBSYS_ANY) &&
(SUBSYS_ID(pI830->PciInfo) == p->subsysCard ||
p->subsysCard == SUBSYS_ANY))
p->hook(pI830);
++p;
}
for (i = 0; i < dmi_data_max; i++)
if (i830_dmi_data[i])
xfree(i830_dmi_data[i]);
}

2443
src/i830_sdvo.c
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src/i830_sdvo.h
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@ -1,29 +0,0 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
Bool
i830_sdvo_init(ScrnInfoPtr pScrn, int output_device);

726
src/i830_sdvo_regs.h
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/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
/**
* @file SDVO command definitions and structures.
*/
#define SDVO_OUTPUT_FIRST (0)
#define SDVO_OUTPUT_TMDS0 (1 << 0)
#define SDVO_OUTPUT_RGB0 (1 << 1)
#define SDVO_OUTPUT_CVBS0 (1 << 2)
#define SDVO_OUTPUT_SVID0 (1 << 3)
#define SDVO_OUTPUT_YPRPB0 (1 << 4)
#define SDVO_OUTPUT_SCART0 (1 << 5)
#define SDVO_OUTPUT_LVDS0 (1 << 6)
#define SDVO_OUTPUT_TMDS1 (1 << 8)
#define SDVO_OUTPUT_RGB1 (1 << 9)
#define SDVO_OUTPUT_CVBS1 (1 << 10)
#define SDVO_OUTPUT_SVID1 (1 << 11)
#define SDVO_OUTPUT_YPRPB1 (1 << 12)
#define SDVO_OUTPUT_SCART1 (1 << 13)
#define SDVO_OUTPUT_LVDS1 (1 << 14)
#define SDVO_OUTPUT_LAST (14)
struct i830_sdvo_caps {
uint8_t vendor_id;
uint8_t device_id;
uint8_t device_rev_id;
uint8_t sdvo_version_minor;
uint8_t sdvo_version_major;
unsigned int sdvo_input_count:2;
unsigned int smooth_scaling:1;
unsigned int sharp_scaling:1;
unsigned int up_scaling:1;
unsigned int down_scaling:1;
unsigned int stall_support:1;
unsigned int pad:1;
uint16_t output_flags;
} __attribute__((packed));
/** This matches the EDID DTD structure, more or less */
struct i830_sdvo_dtd {
struct {
uint16_t clock; /**< pixel clock, in 10kHz units */
uint8_t h_active; /**< lower 8 bits (pixels) */
uint8_t h_blank; /**< lower 8 bits (pixels) */
uint8_t h_high; /**< upper 4 bits each h_active, h_blank */
uint8_t v_active; /**< lower 8 bits (lines) */
uint8_t v_blank; /**< lower 8 bits (lines) */
uint8_t v_high; /**< upper 4 bits each v_active, v_blank */
} part1;
struct {
uint8_t h_sync_off; /**< lower 8 bits, from hblank start */
uint8_t h_sync_width; /**< lower 8 bits (pixels) */
/** lower 4 bits each vsync offset, vsync width */
uint8_t v_sync_off_width;
/**
* 2 high bits of hsync offset, 2 high bits of hsync width,
* bits 4-5 of vsync offset, and 2 high bits of vsync width.
*/
uint8_t sync_off_width_high;
uint8_t dtd_flags;
uint8_t sdvo_flags;
/** bits 6-7 of vsync offset at bits 6-7 */
uint8_t v_sync_off_high;
uint8_t reserved;
} part2;
} __attribute__((packed));
struct i830_sdvo_pixel_clock_range {
uint16_t min; /**< pixel clock, in 10kHz units */
uint16_t max; /**< pixel clock, in 10kHz units */
} __attribute__((packed));
struct i830_sdvo_preferred_input_timing_args {
uint16_t clock;
uint16_t width;
uint16_t height;
uint8_t interlace:1;
uint8_t scaled:1;
uint8_t pad:6;
} __attribute__((packed));
/* I2C registers for SDVO */
#define SDVO_I2C_ARG_0 0x07
#define SDVO_I2C_ARG_1 0x06
#define SDVO_I2C_ARG_2 0x05
#define SDVO_I2C_ARG_3 0x04
#define SDVO_I2C_ARG_4 0x03
#define SDVO_I2C_ARG_5 0x02
#define SDVO_I2C_ARG_6 0x01
#define SDVO_I2C_ARG_7 0x00
#define SDVO_I2C_OPCODE 0x08
#define SDVO_I2C_CMD_STATUS 0x09
#define SDVO_I2C_RETURN_0 0x0a
#define SDVO_I2C_RETURN_1 0x0b
#define SDVO_I2C_RETURN_2 0x0c
#define SDVO_I2C_RETURN_3 0x0d
#define SDVO_I2C_RETURN_4 0x0e
#define SDVO_I2C_RETURN_5 0x0f
#define SDVO_I2C_RETURN_6 0x10
#define SDVO_I2C_RETURN_7 0x11
#define SDVO_I2C_VENDOR_BEGIN 0x20
/* Status results */
#define SDVO_CMD_STATUS_POWER_ON 0x0
#define SDVO_CMD_STATUS_SUCCESS 0x1
#define SDVO_CMD_STATUS_NOTSUPP 0x2
#define SDVO_CMD_STATUS_INVALID_ARG 0x3
#define SDVO_CMD_STATUS_PENDING 0x4
#define SDVO_CMD_STATUS_TARGET_NOT_SPECIFIED 0x5
#define SDVO_CMD_STATUS_SCALING_NOT_SUPP 0x6
/* SDVO commands, argument/result registers */
#define SDVO_CMD_RESET 0x01
/** Returns a struct i830_sdvo_caps */
#define SDVO_CMD_GET_DEVICE_CAPS 0x02
#define SDVO_CMD_GET_FIRMWARE_REV 0x86
# define SDVO_DEVICE_FIRMWARE_MINOR SDVO_I2C_RETURN_0
# define SDVO_DEVICE_FIRMWARE_MAJOR SDVO_I2C_RETURN_1
# define SDVO_DEVICE_FIRMWARE_PATCH SDVO_I2C_RETURN_2
/**
* Reports which inputs are trained (managed to sync).
*
* Devices must have trained within 2 vsyncs of a mode change.
*/
#define SDVO_CMD_GET_TRAINED_INPUTS 0x03
struct i830_sdvo_get_trained_inputs_response {
unsigned int input0_trained:1;
unsigned int input1_trained:1;
unsigned int pad:6;
} __attribute__((packed));
/** Returns a struct i830_sdvo_output_flags of active outputs. */
#define SDVO_CMD_GET_ACTIVE_OUTPUTS 0x04
/**
* Sets the current set of active outputs.
*
* Takes a struct i830_sdvo_output_flags. Must be preceded by a SET_IN_OUT_MAP
* on multi-output devices.
*/
#define SDVO_CMD_SET_ACTIVE_OUTPUTS 0x05
/**
* Returns the current mapping of SDVO inputs to outputs on the device.
*
* Returns two struct i830_sdvo_output_flags structures.
*/
#define SDVO_CMD_GET_IN_OUT_MAP 0x06
struct i830_sdvo_in_out_map {
uint16_t in0, in1;
};
/**
* Sets the current mapping of SDVO inputs to outputs on the device.
*
* Takes two struct i380_sdvo_output_flags structures.
*/
#define SDVO_CMD_SET_IN_OUT_MAP 0x07
/**
* Returns a struct i830_sdvo_output_flags of attached displays.
*/
#define SDVO_CMD_GET_ATTACHED_DISPLAYS 0x0b
/**
* Returns a struct i830_sdvo_ouptut_flags of displays supporting hot plugging.
*/
#define SDVO_CMD_GET_HOT_PLUG_SUPPORT 0x0c
/**
* Takes a struct i830_sdvo_output_flags.
*/
#define SDVO_CMD_SET_ACTIVE_HOT_PLUG 0x0d
/**
* Returns a struct i830_sdvo_output_flags of displays with hot plug
* interrupts enabled.
*/
#define SDVO_CMD_GET_ACTIVE_HOT_PLUG 0x0e
#define SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE 0x0f
struct i830_sdvo_get_interrupt_event_source_response {
uint16_t interrupt_status;
unsigned int ambient_light_interrupt:1;
unsigned int hdmi_audio_encrypt_change:1;
unsigned int pad:6;
} __attribute__((packed));
/**
* Selects which input is affected by future input commands.
*
* Commands affected include SET_INPUT_TIMINGS_PART[12],
* GET_INPUT_TIMINGS_PART[12], GET_PREFERRED_INPUT_TIMINGS_PART[12],
* GET_INPUT_PIXEL_CLOCK_RANGE, and CREATE_PREFERRED_INPUT_TIMINGS.
*/
#define SDVO_CMD_SET_TARGET_INPUT 0x10
struct i830_sdvo_set_target_input_args {
unsigned int target_1:1;
unsigned int pad:7;
} __attribute__((packed));
/**
* Takes a struct i830_sdvo_output_flags of which outputs are targetted by
* future output commands.
*
* Affected commands inclue SET_OUTPUT_TIMINGS_PART[12],
* GET_OUTPUT_TIMINGS_PART[12], and GET_OUTPUT_PIXEL_CLOCK_RANGE.
*/
#define SDVO_CMD_SET_TARGET_OUTPUT 0x11
#define SDVO_CMD_GET_INPUT_TIMINGS_PART1 0x12
#define SDVO_CMD_GET_INPUT_TIMINGS_PART2 0x13
#define SDVO_CMD_SET_INPUT_TIMINGS_PART1 0x14
#define SDVO_CMD_SET_INPUT_TIMINGS_PART2 0x15
#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART1 0x16
#define SDVO_CMD_SET_OUTPUT_TIMINGS_PART2 0x17
#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART1 0x18
#define SDVO_CMD_GET_OUTPUT_TIMINGS_PART2 0x19
/* Part 1 */
# define SDVO_DTD_CLOCK_LOW SDVO_I2C_ARG_0
# define SDVO_DTD_CLOCK_HIGH SDVO_I2C_ARG_1
# define SDVO_DTD_H_ACTIVE SDVO_I2C_ARG_2
# define SDVO_DTD_H_BLANK SDVO_I2C_ARG_3
# define SDVO_DTD_H_HIGH SDVO_I2C_ARG_4
# define SDVO_DTD_V_ACTIVE SDVO_I2C_ARG_5
# define SDVO_DTD_V_BLANK SDVO_I2C_ARG_6
# define SDVO_DTD_V_HIGH SDVO_I2C_ARG_7
/* Part 2 */
# define SDVO_DTD_HSYNC_OFF SDVO_I2C_ARG_0
# define SDVO_DTD_HSYNC_WIDTH SDVO_I2C_ARG_1
# define SDVO_DTD_VSYNC_OFF_WIDTH SDVO_I2C_ARG_2
# define SDVO_DTD_SYNC_OFF_WIDTH_HIGH SDVO_I2C_ARG_3
# define SDVO_DTD_DTD_FLAGS SDVO_I2C_ARG_4
# define SDVO_DTD_DTD_FLAG_INTERLACED (1 << 7)
# define SDVO_DTD_DTD_FLAG_STEREO_MASK (3 << 5)
# define SDVO_DTD_DTD_FLAG_INPUT_MASK (3 << 3)
# define SDVO_DTD_DTD_FLAG_SYNC_MASK (3 << 1)
# define SDVO_DTD_SDVO_FLAS SDVO_I2C_ARG_5
# define SDVO_DTD_SDVO_FLAG_STALL (1 << 7)
# define SDVO_DTD_SDVO_FLAG_CENTERED (0 << 6)
# define SDVO_DTD_SDVO_FLAG_UPPER_LEFT (1 << 6)
# define SDVO_DTD_SDVO_FLAG_SCALING_MASK (3 << 4)
# define SDVO_DTD_SDVO_FLAG_SCALING_NONE (0 << 4)
# define SDVO_DTD_SDVO_FLAG_SCALING_SHARP (1 << 4)
# define SDVO_DTD_SDVO_FLAG_SCALING_SMOOTH (2 << 4)
# define SDVO_DTD_VSYNC_OFF_HIGH SDVO_I2C_ARG_6
/**
* Generates a DTD based on the given width, height, and flags.
*
* This will be supported by any device supporting scaling or interlaced
* modes.
*/
#define SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING 0x1a
# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_LOW SDVO_I2C_ARG_0
# define SDVO_PREFERRED_INPUT_TIMING_CLOCK_HIGH SDVO_I2C_ARG_1
# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_LOW SDVO_I2C_ARG_2
# define SDVO_PREFERRED_INPUT_TIMING_WIDTH_HIGH SDVO_I2C_ARG_3
# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_LOW SDVO_I2C_ARG_4
# define SDVO_PREFERRED_INPUT_TIMING_HEIGHT_HIGH SDVO_I2C_ARG_5
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS SDVO_I2C_ARG_6
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_INTERLACED (1 << 0)
# define SDVO_PREFERRED_INPUT_TIMING_FLAGS_SCALED (1 << 1)
#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1 0x1b
#define SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2 0x1c
/** Returns a struct i830_sdvo_pixel_clock_range */
#define SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE 0x1d
/** Returns a struct i830_sdvo_pixel_clock_range */
#define SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE 0x1e
/** Returns a byte bitfield containing SDVO_CLOCK_RATE_MULT_* flags */
#define SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS 0x1f
/** Returns a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
#define SDVO_CMD_GET_CLOCK_RATE_MULT 0x20
/** Takes a byte containing a SDVO_CLOCK_RATE_MULT_* flag */
#define SDVO_CMD_SET_CLOCK_RATE_MULT 0x21
# define SDVO_CLOCK_RATE_MULT_1X (1 << 0)
# define SDVO_CLOCK_RATE_MULT_2X (1 << 1)
# define SDVO_CLOCK_RATE_MULT_4X (1 << 3)
#define SDVO_CMD_GET_SUPPORTED_TV_FORMATS 0x27
/** 5 bytes of bit flags for TV formats shared by all TV format functions */
struct i830_sdvo_tv_format {
unsigned int ntsc_m:1;
unsigned int ntsc_j:1;
unsigned int ntsc_443:1;
unsigned int pal_b:1;
unsigned int pal_d:1;
unsigned int pal_g:1;
unsigned int pal_h:1;
unsigned int pal_i:1;
unsigned int pal_m:1;
unsigned int pal_n:1;
unsigned int pal_nc:1;
unsigned int pal_60:1;
unsigned int secam_b:1;
unsigned int secam_d:1;
unsigned int secam_g:1;
unsigned int secam_k:1;
unsigned int secam_k1:1;
unsigned int secam_l:1;
unsigned int secam_60:1;
unsigned int hdtv_std_smpte_240m_1080i_59:1;
unsigned int hdtv_std_smpte_240m_1080i_60:1;
unsigned int hdtv_std_smpte_260m_1080i_59:1;
unsigned int hdtv_std_smpte_260m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080i_50:1;
unsigned int hdtv_std_smpte_274m_1080i_59:1;
unsigned int hdtv_std_smpte_274m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080p_23:1;
unsigned int hdtv_std_smpte_274m_1080p_24:1;
unsigned int hdtv_std_smpte_274m_1080p_25:1;
unsigned int hdtv_std_smpte_274m_1080p_29:1;
unsigned int hdtv_std_smpte_274m_1080p_30:1;
unsigned int hdtv_std_smpte_274m_1080p_50:1;
unsigned int hdtv_std_smpte_274m_1080p_59:1;
unsigned int hdtv_std_smpte_274m_1080p_60:1;
unsigned int hdtv_std_smpte_295m_1080i_50:1;
unsigned int hdtv_std_smpte_295m_1080p_50:1;
unsigned int hdtv_std_smpte_296m_720p_59:1;
unsigned int hdtv_std_smpte_296m_720p_60:1;
unsigned int hdtv_std_smpte_296m_720p_50:1;
unsigned int hdtv_std_smpte_293m_480p_59:1;
unsigned int hdtv_std_smpte_170m_480i_59:1;
unsigned int hdtv_std_iturbt601_576i_50:1;
unsigned int hdtv_std_iturbt601_576p_50:1;
unsigned int hdtv_std_eia_7702a_480i_60:1;
unsigned int hdtv_std_eia_7702a_480p_60:1;
unsigned int pad:3;
} __attribute__((packed));
#define SDVO_CMD_GET_TV_FORMAT 0x28
/** This command should be run before SetOutputTimingsPart[12] */
#define SDVO_CMD_SET_TV_FORMAT 0x29
/** Returns the resolutiosn that can be used with the given TV format */
#define SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT 0x83
struct i830_sdvo_sdtv_resolution_request {
unsigned int ntsc_m:1;
unsigned int ntsc_j:1;
unsigned int ntsc_443:1;
unsigned int pal_b:1;
unsigned int pal_d:1;
unsigned int pal_g:1;
unsigned int pal_h:1;
unsigned int pal_i:1;
unsigned int pal_m:1;
unsigned int pal_n:1;
unsigned int pal_nc:1;
unsigned int pal_60:1;
unsigned int secam_b:1;
unsigned int secam_d:1;
unsigned int secam_g:1;
unsigned int secam_k:1;
unsigned int secam_k1:1;
unsigned int secam_l:1;
unsigned int secam_60:1;
unsigned int pad:5;
} __attribute__((packed));
struct i830_sdvo_sdtv_resolution_reply {
unsigned int res_320x200:1;
unsigned int res_320x240:1;
unsigned int res_400x300:1;
unsigned int res_640x350:1;
unsigned int res_640x400:1;
unsigned int res_640x480:1;
unsigned int res_704x480:1;
unsigned int res_704x576:1;
unsigned int res_720x350:1;
unsigned int res_720x400:1;
unsigned int res_720x480:1;
unsigned int res_720x540:1;
unsigned int res_720x576:1;
unsigned int res_768x576:1;
unsigned int res_800x600:1;
unsigned int res_832x624:1;
unsigned int res_920x766:1;
unsigned int res_1024x768:1;
unsigned int res_1280x1024:1;
unsigned int pad:5;
} __attribute__((packed));
/* Get supported resolution with squire pixel aspect ratio that can be
scaled for the requested HDTV format */
#define SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT 0x85
struct i830_sdvo_hdtv_resolution_request {
unsigned int hdtv_std_smpte_240m_1080i_59:1;
unsigned int hdtv_std_smpte_240m_1080i_60:1;
unsigned int hdtv_std_smpte_260m_1080i_59:1;
unsigned int hdtv_std_smpte_260m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080i_50:1;
unsigned int hdtv_std_smpte_274m_1080i_59:1;
unsigned int hdtv_std_smpte_274m_1080i_60:1;
unsigned int hdtv_std_smpte_274m_1080p_23:1;
unsigned int hdtv_std_smpte_274m_1080p_24:1;
unsigned int hdtv_std_smpte_274m_1080p_25:1;
unsigned int hdtv_std_smpte_274m_1080p_29:1;
unsigned int hdtv_std_smpte_274m_1080p_30:1;
unsigned int hdtv_std_smpte_274m_1080p_50:1;
unsigned int hdtv_std_smpte_274m_1080p_59:1;
unsigned int hdtv_std_smpte_274m_1080p_60:1;
unsigned int hdtv_std_smpte_295m_1080i_50:1;
unsigned int hdtv_std_smpte_295m_1080p_50:1;
unsigned int hdtv_std_smpte_296m_720p_59:1;
unsigned int hdtv_std_smpte_296m_720p_60:1;
unsigned int hdtv_std_smpte_296m_720p_50:1;
unsigned int hdtv_std_smpte_293m_480p_59:1;
unsigned int hdtv_std_smpte_170m_480i_59:1;
unsigned int hdtv_std_iturbt601_576i_50:1;
unsigned int hdtv_std_iturbt601_576p_50:1;
unsigned int hdtv_std_eia_7702a_480i_60:1;
unsigned int hdtv_std_eia_7702a_480p_60:1;
unsigned int pad:6;
} __attribute__((packed));
struct i830_sdvo_hdtv_resolution_reply {
unsigned int res_640x480:1;
unsigned int res_800x600:1;
unsigned int res_1024x768:1;
unsigned int res_1280x960:1;
unsigned int res_1400x1050:1;
unsigned int res_1600x1200:1;
unsigned int res_1920x1440:1;
unsigned int res_2048x1536:1;
unsigned int res_2560x1920:1;
unsigned int res_3200x2400:1;
unsigned int res_3840x2880:1;
unsigned int pad1:5;
unsigned int res_848x480:1;
unsigned int res_1064x600:1;
unsigned int res_1280x720:1;
unsigned int res_1360x768:1;
unsigned int res_1704x960:1;
unsigned int res_1864x1050:1;
unsigned int res_1920x1080:1;
unsigned int res_2128x1200:1;
unsigned int res_2560x1400:1;
unsigned int res_2728x1536:1;
unsigned int res_3408x1920:1;
unsigned int res_4264x2400:1;
unsigned int res_5120x2880:1;
unsigned int pad2:3;
unsigned int res_768x480:1;
unsigned int res_960x600:1;
unsigned int res_1152x720:1;
unsigned int res_1124x768:1;
unsigned int res_1536x960:1;
unsigned int res_1680x1050:1;
unsigned int res_1728x1080:1;
unsigned int res_1920x1200:1;
unsigned int res_2304x1440:1;
unsigned int res_2456x1536:1;
unsigned int res_3072x1920:1;
unsigned int res_3840x2400:1;
unsigned int res_4608x2880:1;
unsigned int pad3:3;
unsigned int res_1280x1024:1;
unsigned int pad4:7;
unsigned int res_1280x768:1;
unsigned int pad5:7;
} __attribute__((packed));
/* Get supported power state returns info for encoder and monitor, rely on
last SetTargetInput and SetTargetOutput calls */
#define SDVO_CMD_GET_SUPPORTED_POWER_STATES 0x2a
/* Get power state returns info for encoder and monitor, rely on last
SetTargetInput and SetTargetOutput calls */
#define SDVO_CMD_GET_POWER_STATE 0x2b
/* Set encoder power state */
#define SDVO_CMD_SET_ENCODER_POWER_STATE 0x2c
# define SDVO_ENCODER_STATE_ON (1 << 0)
# define SDVO_ENCODER_STATE_STANDBY (1 << 1)
# define SDVO_ENCODER_STATE_SUSPEND (1 << 2)
# define SDVO_ENCODER_STATE_OFF (1 << 3)
# define SDVO_MONITOR_STATE_ON (1 << 4)
# define SDVO_MONITOR_STATE_STANDBY (1 << 5)
# define SDVO_MONITOR_STATE_SUSPEND (1 << 6)
# define SDVO_MONITOR_STATE_OFF (1 << 7)
#define SDVO_CMD_GET_MAX_PANEL_POWER_SEQUENCING 0x2d
#define SDVO_CMD_GET_PANEL_POWER_SEQUENCING 0x2e
#define SDVO_CMD_SET_PANEL_POWER_SEQUENCING 0x2f
/**
* The panel power sequencing parameters are in units of milliseconds.
* The high fields are bits 8:9 of the 10-bit values.
*/
struct sdvo_panel_power_sequencing {
uint8_t t0;
uint8_t t1;
uint8_t t2;
uint8_t t3;
uint8_t t4;
unsigned int t0_high:2;
unsigned int t1_high:2;
unsigned int t2_high:2;
unsigned int t3_high:2;
unsigned int t4_high:2;
unsigned int pad:6;
} __attribute__((packed));
#define SDVO_CMD_GET_MAX_BACKLIGHT_LEVEL 0x30
struct sdvo_max_backlight_reply {
uint8_t max_value;
uint8_t default_value;
} __attribute__((packed));
#define SDVO_CMD_GET_BACKLIGHT_LEVEL 0x31
#define SDVO_CMD_SET_BACKLIGHT_LEVEL 0x32
#define SDVO_CMD_GET_AMBIENT_LIGHT 0x33
struct sdvo_get_ambient_light_reply {
uint16_t trip_low;
uint16_t trip_high;
uint16_t value;
} __attribute__((packed));
#define SDVO_CMD_SET_AMBIENT_LIGHT 0x34
struct sdvo_set_ambient_light_reply {
uint16_t trip_low;
uint16_t trip_high;
unsigned int enable:1;
unsigned int pad:7;
} __attribute__((packed));
/* Set display power state */
#define SDVO_CMD_SET_DISPLAY_POWER_STATE 0x7d
# define SDVO_DISPLAY_STATE_ON (1 << 0)
# define SDVO_DISPLAY_STATE_STANDBY (1 << 1)
# define SDVO_DISPLAY_STATE_SUSPEND (1 << 2)
# define SDVO_DISPLAY_STATE_OFF (1 << 3)
#define SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS 0x84
struct i830_sdvo_enhancements_reply {
unsigned int flicker_filter:1;
unsigned int flicker_filter_adaptive:1;
unsigned int flicker_filter_2d:1;
unsigned int saturation:1;
unsigned int hue:1;
unsigned int brightness:1;
unsigned int contrast:1;
unsigned int overscan_h:1;
unsigned int overscan_v:1;
unsigned int position_h:1;
unsigned int position_v:1;
unsigned int sharpness:1;
unsigned int dot_crawl:1;
unsigned int dither:1;
unsigned int max_tv_chroma_filter:1;
unsigned int max_tv_luma_filter:1;
} __attribute__((packed));
/* Picture enhancement limits below are dependent on the current TV format,
* and thus need to be queried and set after it.
*/
#define SDVO_CMD_GET_MAX_FLICKER_FITER 0x4d
#define SDVO_CMD_GET_MAX_ADAPTIVE_FLICKER_FITER 0x7b
#define SDVO_CMD_GET_MAX_2D_FLICKER_FITER 0x52
#define SDVO_CMD_GET_MAX_SATURATION 0x55
#define SDVO_CMD_GET_MAX_HUE 0x58
#define SDVO_CMD_GET_MAX_BRIGHTNESS 0x5b
#define SDVO_CMD_GET_MAX_CONTRAST 0x5e
#define SDVO_CMD_GET_MAX_OVERSCAN_H 0x61
#define SDVO_CMD_GET_MAX_OVERSCAN_V 0x64
#define SDVO_CMD_GET_MAX_POSITION_H 0x67
#define SDVO_CMD_GET_MAX_POSITION_V 0x6a
#define SDVO_CMD_GET_MAX_SHARPNESS_V 0x6d
#define SDVO_CMD_GET_MAX_TV_CHROMA 0x74
#define SDVO_CMD_GET_MAX_TV_LUMA 0x77
struct i830_sdvo_enhancement_limits_reply {
uint16_t max_value;
uint16_t default_value;
} __attribute__((packed));
#define SDVO_CMD_GET_LVDS_PANEL_INFORMATION 0x7f
#define SDVO_CMD_SET_LVDS_PANEL_INFORMATION 0x80
# define SDVO_LVDS_COLOR_DEPTH_18 (0 << 0)
# define SDVO_LVDS_COLOR_DEPTH_24 (1 << 0)
# define SDVO_LVDS_CONNECTOR_SPWG (0 << 2)
# define SDVO_LVDS_CONNECTOR_OPENLDI (1 << 2)
# define SDVO_LVDS_SINGLE_CHANNEL (0 << 4)
# define SDVO_LVDS_DUAL_CHANNEL (1 << 4)
#define SDVO_CMD_GET_FLICKER_FILTER 0x4e
#define SDVO_CMD_SET_FLICKER_FILTER 0x4f
#define SDVO_CMD_GET_ADAPTIVE_FLICKER_FITER 0x50
#define SDVO_CMD_SET_ADAPTIVE_FLICKER_FITER 0x51
#define SDVO_CMD_GET_2D_FLICKER_FITER 0x53
#define SDVO_CMD_SET_2D_FLICKER_FITER 0x54
#define SDVO_CMD_GET_SATURATION 0x56
#define SDVO_CMD_SET_SATURATION 0x57
#define SDVO_CMD_GET_HUE 0x59
#define SDVO_CMD_SET_HUE 0x5a
#define SDVO_CMD_GET_BRIGHTNESS 0x5c
#define SDVO_CMD_SET_BRIGHTNESS 0x5d
#define SDVO_CMD_GET_CONTRAST 0x5f
#define SDVO_CMD_SET_CONTRAST 0x60
#define SDVO_CMD_GET_OVERSCAN_H 0x62
#define SDVO_CMD_SET_OVERSCAN_H 0x63
#define SDVO_CMD_GET_OVERSCAN_V 0x65
#define SDVO_CMD_SET_OVERSCAN_V 0x66
#define SDVO_CMD_GET_POSITION_H 0x68
#define SDVO_CMD_SET_POSITION_H 0x69
#define SDVO_CMD_GET_POSITION_V 0x6b
#define SDVO_CMD_SET_POSITION_V 0x6c
#define SDVO_CMD_GET_SHARPNESS 0x6e
#define SDVO_CMD_SET_SHARPNESS 0x6f
#define SDVO_CMD_GET_TV_CHROMA 0x75
#define SDVO_CMD_SET_TV_CHROMA 0x76
#define SDVO_CMD_GET_TV_LUMA 0x78
#define SDVO_CMD_SET_TV_LUMA 0x79
struct i830_sdvo_enhancements_arg {
uint16_t value;
}__attribute__((packed));
#define SDVO_CMD_GET_DOT_CRAWL 0x70
#define SDVO_CMD_SET_DOT_CRAWL 0x71
# define SDVO_DOT_CRAWL_ON (1 << 0)
# define SDVO_DOT_CRAWL_DEFAULT_ON (1 << 1)
#define SDVO_CMD_GET_DITHER 0x72
#define SDVO_CMD_SET_DITHER 0x73
# define SDVO_DITHER_ON (1 << 0)
# define SDVO_DITHER_DEFAULT_ON (1 << 1)
#define SDVO_CMD_SET_CONTROL_BUS_SWITCH 0x7a
# define SDVO_CONTROL_BUS_PROM (1 << 0)
# define SDVO_CONTROL_BUS_DDC1 (1 << 1)
# define SDVO_CONTROL_BUS_DDC2 (1 << 2)
# define SDVO_CONTROL_BUS_DDC3 (1 << 3)
/* HDMI op codes */
#define SDVO_CMD_GET_SUPP_ENCODE 0x9d
#define SDVO_CMD_GET_ENCODE 0x9e
#define SDVO_CMD_SET_ENCODE 0x9f
#define SDVO_ENCODE_DVI 0x0
#define SDVO_ENCODE_HDMI 0x1
#define SDVO_CMD_SET_PIXEL_REPLI 0x8b
#define SDVO_CMD_GET_PIXEL_REPLI 0x8c
#define SDVO_CMD_GET_COLORIMETRY_CAP 0x8d
#define SDVO_CMD_SET_COLORIMETRY 0x8e
#define SDVO_COLORIMETRY_RGB256 0x0
#define SDVO_COLORIMETRY_RGB220 0x1
#define SDVO_COLORIMETRY_YCrCb422 0x3
#define SDVO_COLORIMETRY_YCrCb444 0x4
#define SDVO_CMD_GET_COLORIMETRY 0x8f
#define SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER 0x90
#define SDVO_CMD_SET_AUDIO_STAT 0x91
#define SDVO_CMD_GET_AUDIO_STAT 0x92
#define SDVO_CMD_SET_HBUF_INDEX 0x93
#define SDVO_CMD_GET_HBUF_INDEX 0x94
#define SDVO_CMD_GET_HBUF_INFO 0x95
#define SDVO_CMD_SET_HBUF_AV_SPLIT 0x96
#define SDVO_CMD_GET_HBUF_AV_SPLIT 0x97
#define SDVO_CMD_SET_HBUF_DATA 0x98
#define SDVO_CMD_GET_HBUF_DATA 0x99
#define SDVO_CMD_SET_HBUF_TXRATE 0x9a
#define SDVO_CMD_GET_HBUF_TXRATE 0x9b
#define SDVO_HBUF_TX_DISABLED (0 << 6)
#define SDVO_HBUF_TX_ONCE (2 << 6)
#define SDVO_HBUF_TX_VSYNC (3 << 6)
#define SDVO_CMD_GET_AUDIO_TX_INFO 0x9c
struct i830_sdvo_encode{
uint8_t dvi_rev;
uint8_t hdmi_rev;
} __attribute__ ((packed));
#define SDVO_STALL_FLAG (1 << 7)

2042
src/i830_tv.c
View File

File diff suppressed because it is too large Load Diff

96
src/i830_uxa.c
View File

@ -91,34 +91,20 @@ static int uxa_pixmap_index;
Bool Bool
i830_pixmap_tiled(PixmapPtr pPixmap) i830_pixmap_tiled(PixmapPtr pPixmap)
{ {
ScreenPtr pScreen = pPixmap->drawable.pScreen;
ScrnInfoPtr pScrn = xf86Screens[pScreen->myNum];
I830Ptr pI830 = I830PTR(pScrn);
unsigned long offset;
dri_bo *bo; dri_bo *bo;
uint32_t tiling_mode, swizzle_mode;
int ret;
bo = i830_get_pixmap_bo(pPixmap); bo = i830_get_pixmap_bo(pPixmap);
if (bo != NULL) { assert(bo != NULL);
uint32_t tiling_mode, swizzle_mode;
int ret;
ret = drm_intel_bo_get_tiling(bo, &tiling_mode, &swizzle_mode); ret = drm_intel_bo_get_tiling(bo, &tiling_mode, &swizzle_mode);
if (ret != 0) { if (ret != 0) {
FatalError("Couldn't get tiling on bo %p: %s\n", FatalError("Couldn't get tiling on bo %p: %s\n",
bo, strerror(-ret)); bo, strerror(-ret));
}
return tiling_mode != I915_TILING_NONE;
} }
offset = intel_get_pixmap_offset(pPixmap); return tiling_mode != I915_TILING_NONE;
if (offset == pI830->front_buffer->offset &&
pI830->front_buffer->tiling != TILE_NONE)
{
return TRUE;
}
return FALSE;
} }
Bool Bool
@ -478,46 +464,35 @@ i830_uxa_prepare_access (PixmapPtr pixmap, uxa_access_t access)
{ {
dri_bo *bo = i830_get_pixmap_bo (pixmap); dri_bo *bo = i830_get_pixmap_bo (pixmap);
ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum]; ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
I830Ptr i830 = I830PTR(scrn);
intel_batch_flush(scrn, FALSE); intel_batch_flush(scrn, FALSE);
if (bo) { /* No VT sema or GEM? No GTT mapping. */
I830Ptr i830 = I830PTR(scrn); if (!scrn->vtSema) {
if (dri_bo_map(bo, access == UXA_ACCESS_RW) != 0)
return FALSE;
pixmap->devPrivate.ptr = bo->virtual;
return TRUE;
}
/* No VT sema or GEM? No GTT mapping. */ /* Kernel manages fences at GTT map/fault time */
if (!scrn->vtSema || !i830->have_gem) { if (bo->size < i830->max_gtt_map_size) {
if (dri_bo_map(bo, access == UXA_ACCESS_RW) != 0) if (drm_intel_gem_bo_map_gtt(bo)) {
return FALSE; xf86DrvMsg(scrn->scrnIndex, X_WARNING,
pixmap->devPrivate.ptr = bo->virtual; "%s: bo map failed\n",
return TRUE; __FUNCTION__);
return FALSE;
} }
} else {
/* Kernel manages fences at GTT map/fault time */ if (dri_bo_map(bo, access == UXA_ACCESS_RW) != 0) {
if (i830->kernel_exec_fencing) { xf86DrvMsg(scrn->scrnIndex, X_WARNING,
if (bo->size < i830->max_gtt_map_size) { "%s: bo map failed\n",
if (drm_intel_gem_bo_map_gtt(bo)) { __FUNCTION__);
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map failed\n",
__FUNCTION__);
return FALSE;
}
} else {
if (dri_bo_map(bo, access == UXA_ACCESS_RW) != 0) {
xf86DrvMsg(scrn->scrnIndex, X_WARNING,
"%s: bo map failed\n",
__FUNCTION__);
return FALSE;
}
}
pixmap->devPrivate.ptr = bo->virtual;
} else { /* or not... */
if (drm_intel_bo_pin(bo, 4096) != 0)
return FALSE; return FALSE;
drm_intel_gem_bo_start_gtt_access(bo, access == UXA_ACCESS_RW);
pixmap->devPrivate.ptr = i830->FbBase + bo->offset;
} }
} else }
i830_wait_ring_idle(scrn); pixmap->devPrivate.ptr = bo->virtual;
return TRUE; return TRUE;
} }
@ -535,19 +510,16 @@ i830_uxa_finish_access (PixmapPtr pixmap)
if (bo == i830->front_buffer->bo) if (bo == i830->front_buffer->bo)
i830->need_flush = TRUE; i830->need_flush = TRUE;
if (!scrn->vtSema || !i830->have_gem) { if (!scrn->vtSema) {
dri_bo_unmap(bo); dri_bo_unmap(bo);
pixmap->devPrivate.ptr = NULL; pixmap->devPrivate.ptr = NULL;
return; return;
} }
if (i830->kernel_exec_fencing) if (bo->size < i830->max_gtt_map_size)
if (bo->size < i830->max_gtt_map_size) drm_intel_gem_bo_unmap_gtt(bo);
drm_intel_gem_bo_unmap_gtt(bo);
else
dri_bo_unmap(bo);
else else
drm_intel_bo_unpin(bo); dri_bo_unmap(bo);
pixmap->devPrivate.ptr = NULL; pixmap->devPrivate.ptr = NULL;
} }
} }

32
src/i830_video.c
View File

@ -1667,7 +1667,8 @@ I830PutImage(ScrnInfoPtr pScrn,
if (IS_I965G(pI830)) { if (IS_I965G(pI830)) {
if (xvmc_passthrough(id, pPriv->rotation)) { if (xvmc_passthrough(id, pPriv->rotation)) {
pPriv->YBufOffset = buf - pI830->FbBase; /* XXX: KMS */
pPriv->YBufOffset = (uintptr_t)buf;
pPriv->UBufOffset = pPriv->YBufOffset + height*width; pPriv->UBufOffset = pPriv->YBufOffset + height*width;
pPriv->VBufOffset = pPriv->UBufOffset + height*width/4; pPriv->VBufOffset = pPriv->UBufOffset + height*width/4;
} }
@ -1811,32 +1812,3 @@ I830VideoBlockHandler(int i, pointer blockData, pointer pTimeout,
} }
} }
} }
void
i830_crtc_dpms_video(xf86CrtcPtr crtc, Bool on)
{
ScrnInfoPtr pScrn = crtc->scrn;
I830Ptr pI830 = I830PTR(pScrn);
I830PortPrivPtr pPriv;
/* no overlay */
if (pI830->adaptor == NULL)
return;
pPriv = GET_PORT_PRIVATE(pScrn);
if (crtc != pPriv->current_crtc)
return;
/* Check if it's the crtc the overlay is off */
if (!on) {
/* We stop the video when mode switching, so we don't lock up
* the engine. The overlayOK will determine whether we can re-enable
* with the current video on completion of the mode switch.
*/
I830StopVideo(pScrn, pPriv, TRUE);
pPriv->current_crtc = NULL;
pPriv->overlayOK = FALSE;
pPriv->oneLineMode = FALSE;
}
}

3
src/i915_hwmc.c
View File

@ -513,6 +513,8 @@ static int i915_xvmc_create_context (ScrnInfoPtr pScrn, XvMCContextPtr pContext,
contextRec->corrdata.size = ctxpriv->mcCorrdata->size; contextRec->corrdata.size = ctxpriv->mcCorrdata->size;
contextRec->deviceID = DEVICE_ID(pI830->PciInfo); contextRec->deviceID = DEVICE_ID(pI830->PciInfo);
/* XXX: KMS */
#if 0
if (IS_I915G(pI830) || IS_I915GM(pI830)) { if (IS_I915G(pI830) || IS_I915GM(pI830)) {
contextRec->sis.bus_addr = ctxpriv->mcStaticIndirectState->bus_addr; contextRec->sis.bus_addr = ctxpriv->mcStaticIndirectState->bus_addr;
contextRec->ssb.bus_addr = ctxpriv->mcSamplerState->bus_addr; contextRec->ssb.bus_addr = ctxpriv->mcSamplerState->bus_addr;
@ -520,6 +522,7 @@ static int i915_xvmc_create_context (ScrnInfoPtr pScrn, XvMCContextPtr pContext,
contextRec->psp.bus_addr = ctxpriv->mcPixelShaderProgram->bus_addr; contextRec->psp.bus_addr = ctxpriv->mcPixelShaderProgram->bus_addr;
contextRec->psc.bus_addr = ctxpriv->mcPixelShaderConstants->bus_addr; contextRec->psc.bus_addr = ctxpriv->mcPixelShaderConstants->bus_addr;
} }
#endif
pXvMC->ncontexts++; pXvMC->ncontexts++;
pXvMC->contexts[i] = pContext->context_id; pXvMC->contexts[i] = pContext->context_id;

5
src/i965_hwmc.c
View File

@ -74,7 +74,7 @@ static int create_context(ScrnInfoPtr pScrn,
private_context->is_g4x = IS_G4X(I830); private_context->is_g4x = IS_G4X(I830);
private_context->is_965_q = IS_965_Q(I830); private_context->is_965_q = IS_965_Q(I830);
private_context->is_igdng = IS_IGDNG(I830); private_context->is_igdng = IS_IGDNG(I830);
private_context->comm.kernel_exec_fencing = I830->kernel_exec_fencing; private_context->comm.kernel_exec_fencing = 1;
private_context->comm.type = xvmc_driver->flag; private_context->comm.type = xvmc_driver->flag;
*num_privates = sizeof(*private_context)/sizeof(CARD32); *num_privates = sizeof(*private_context)/sizeof(CARD32);
@ -164,7 +164,10 @@ static int put_image(ScrnInfoPtr pScrn,
if (id == FOURCC_XVMC) { if (id == FOURCC_XVMC) {
bo = intel_bo_gem_create_from_name(pI830->bufmgr, "surface", cmd->handle); bo = intel_bo_gem_create_from_name(pI830->bufmgr, "surface", cmd->handle);
dri_bo_pin(bo, 0x1000); dri_bo_pin(bo, 0x1000);
/* XXX: KMS */
#if 0
buf = pI830->FbBase + bo->offset; buf = pI830->FbBase + bo->offset;
#endif
} }
XvPutImage(pScrn, src_x, src_y, drw_x, drw_y, src_w, src_h, XvPutImage(pScrn, src_x, src_y, drw_x, drw_y, src_w, src_h,
drw_w, drw_h, id, buf, width, height, sync, clipBoxes, drw_w, drw_h, id, buf, width, height, sync, clipBoxes,

5
src/i965_render.c
View File

@ -1071,10 +1071,7 @@ i965_set_picture_surface_state(dri_bo *ss_bo, int ss_index,
local_ss.ss0.vert_line_stride_ofs = 0; local_ss.ss0.vert_line_stride_ofs = 0;
local_ss.ss0.mipmap_layout_mode = 0; local_ss.ss0.mipmap_layout_mode = 0;
local_ss.ss0.render_cache_read_mode = 0; local_ss.ss0.render_cache_read_mode = 0;
if (pixmap_bo != NULL) local_ss.ss1.base_addr = pixmap_bo->offset;
local_ss.ss1.base_addr = pixmap_bo->offset;
else
local_ss.ss1.base_addr = intel_get_pixmap_offset(pPixmap);
local_ss.ss2.mip_count = 0; local_ss.ss2.mip_count = 0;
local_ss.ss2.render_target_rotation = 0; local_ss.ss2.render_target_rotation = 0;

16
src/ivch/Makefile.am
View File

@ -1,16 +0,0 @@
# this is obnoxious:
# -module lets us name the module exactly how we want
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
@PCIACCESS_CFLAGS@
ivch_la_LTLIBRARIES = ivch.la
ivch_la_LDFLAGS = -module -avoid-version
ivch_ladir = @moduledir@/drivers
ivch_la_SOURCES = \
ivch.c \
ivch_module.c \
ivch_reg.h

373
src/ivch/ivch.c
View File

@ -1,373 +0,0 @@
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "miscstruct.h"
#include "xf86i2c.h"
#include "xf86Crtc.h"
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include <unistd.h>
#include "../i2c_vid.h"
#include "../i830_bios.h"
#include "ivch_reg.h"
struct ivch_priv {
I2CDevRec d;
xf86OutputPtr output;
Bool quiet;
uint16_t width, height;
uint16_t save_VR01;
uint16_t save_VR40;
};
struct vch_capabilities {
struct aimdb_block aimdb_block;
uint8_t panel_type;
uint8_t set_panel_type;
uint8_t slave_address;
uint8_t capabilities;
#define VCH_PANEL_FITTING_SUPPORT (0x3 << 0)
#define VCH_PANEL_FITTING_TEXT (1 << 2)
#define VCH_PANEL_FITTING_GRAPHICS (1 << 3)
#define VCH_PANEL_FITTING_RATIO (1 << 4)
#define VCH_DITHERING (1 << 5)
uint8_t backlight_gpio;
uint8_t set_panel_type_us_gpios;
} __attribute__ ((packed));
static void
ivch_dump_regs(I2CDevPtr d);
/**
* Reads a register on the ivch.
*
* Each of the 256 registers are 16 bits long.
*/
static Bool
ivch_read(struct ivch_priv *priv, int addr, uint16_t *data)
{
I2CBusPtr b = priv->d.pI2CBus;
I2CByte *p = (I2CByte *) data;
if (!b->I2CStart(b, priv->d.StartTimeout))
goto fail;
if (!b->I2CPutByte(&priv->d, priv->d.SlaveAddr | 1))
goto fail;
if (!b->I2CPutByte(&priv->d, addr))
goto fail;
if (!b->I2CGetByte(&priv->d, p++, FALSE))
goto fail;
if (!b->I2CGetByte(&priv->d, p++, TRUE))
goto fail;
b->I2CStop(&priv->d);
return TRUE;
fail:
if (!priv->quiet) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"ivch: Unable to read register 0x%02x from %s:%02x.\n",
addr, priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
}
b->I2CStop(&priv->d);
return FALSE;
}
/** Writes a 16-bit register on the ivch */
static Bool
ivch_write(struct ivch_priv *priv, int addr, uint16_t data)
{
I2CBusPtr b = priv->d.pI2CBus;
if (!b->I2CStart(b, priv->d.StartTimeout))
goto fail;
if (!b->I2CPutByte(&priv->d, priv->d.SlaveAddr))
goto fail;
if (!b->I2CPutByte(&priv->d, addr))
goto fail;
if (!b->I2CPutByte(&priv->d, data & 0xff))
goto fail;
if (!b->I2CPutByte(&priv->d, data >> 8))
goto fail;
b->I2CStop(&priv->d);
return TRUE;
fail:
b->I2CStop(&priv->d);
if (!priv->quiet) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to write register 0x%02x to %s:%d.\n",
addr, priv->d.pI2CBus->BusName, priv->d.SlaveAddr);
}
return FALSE;
}
/** Probes the given bus and slave address for an ivch */
static void *
ivch_init(I2CBusPtr b, I2CSlaveAddr addr)
{
struct ivch_priv *priv;
uint16_t temp;
priv = xcalloc(1, sizeof(struct ivch_priv));
if (priv == NULL)
return NULL;
priv->output = NULL;
priv->d.DevName = "i82807aa \"ivch\" LVDS/CMOS panel controller";
priv->d.SlaveAddr = addr;
priv->d.pI2CBus = b;
priv->d.StartTimeout = b->StartTimeout;
priv->d.BitTimeout = b->BitTimeout;
priv->d.AcknTimeout = b->AcknTimeout;
priv->d.ByteTimeout = b->ByteTimeout;
priv->d.DriverPrivate.ptr = priv;
priv->quiet = TRUE;
if (!ivch_read(priv, VR00, &temp))
goto out;
priv->quiet = FALSE;
/* Since the identification bits are probably zeroes, which doesn't seem
* very unique, check that the value in the base address field matches
* the address it's responding on.
*/
if ((temp & VR00_BASE_ADDRESS_MASK) != (priv->d.SlaveAddr >> 1)) {
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_ERROR,
"ivch detect failed due to address mismatch "
"(%d vs %d)\n",
(temp & VR00_BASE_ADDRESS_MASK), priv->d.SlaveAddr >> 1);
goto out;
}
if (!xf86I2CDevInit(&priv->d)) {
goto out;
}
ivch_read(priv, VR20, &priv->width);
ivch_read(priv, VR21, &priv->height);
return priv;
out:
xfree(priv);
return NULL;
}
static xf86OutputStatus
ivch_detect(I2CDevPtr d)
{
return XF86OutputStatusConnected;
}
static ModeStatus
ivch_mode_valid(I2CDevPtr d, DisplayModePtr mode)
{
if (mode->Clock > 112000)
return MODE_CLOCK_HIGH;
return MODE_OK;
}
/** Sets the power state of the panel connected to the ivch */
static void
ivch_dpms(I2CDevPtr d, int mode)
{
struct ivch_priv *priv = d->DriverPrivate.ptr;
int i;
uint16_t vr01, vr30, backlight;
/* Set the new power state of the panel. */
if (!ivch_read(priv, VR01, &vr01))
return;
if (mode == DPMSModeOn)
backlight = 1;
else
backlight = 0;
ivch_write(priv, VR80, backlight);
if (mode == DPMSModeOn)
vr01 |= VR01_LCD_ENABLE | VR01_DVO_ENABLE;
else
vr01 &= ~(VR01_LCD_ENABLE | VR01_DVO_ENABLE);
ivch_write(priv, VR01, vr01);
/* Wait for the panel to make its state transition */
for (i = 0; i < 100; i++) {
if (!ivch_read(priv, VR30, &vr30))
break;
if (((vr30 & VR30_PANEL_ON) != 0) == (mode == DPMSModeOn))
break;
usleep (1000);
}
/* And wait some more; without this, the vch fails to resync sometimes */
usleep (16 * 1000);
}
static void
ivch_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
{
struct ivch_priv *priv = d->DriverPrivate.ptr;
uint16_t vr40 = 0;
uint16_t vr01;
vr01 = 0;
vr40 = (VR40_STALL_ENABLE |
VR40_VERTICAL_INTERP_ENABLE |
VR40_HORIZONTAL_INTERP_ENABLE);
if (mode->HDisplay != adjusted_mode->HDisplay ||
mode->VDisplay != adjusted_mode->VDisplay)
{
uint16_t x_ratio, y_ratio;
vr01 |= VR01_PANEL_FIT_ENABLE;
vr40 |= VR40_CLOCK_GATING_ENABLE;
x_ratio = (((mode->HDisplay - 1) << 16) / (adjusted_mode->HDisplay - 1)) >> 2;
y_ratio = (((mode->VDisplay - 1) << 16) / (adjusted_mode->VDisplay - 1)) >> 2;
ivch_write (priv, VR42, x_ratio);
ivch_write (priv, VR41, y_ratio);
}
else
{
vr01 &= ~VR01_PANEL_FIT_ENABLE;
vr40 &= ~VR40_CLOCK_GATING_ENABLE;
}
vr40 &= ~VR40_AUTO_RATIO_ENABLE;
ivch_write(priv, VR01, vr01);
ivch_write(priv, VR40, vr40);
ivch_dump_regs(d);
}
static void
ivch_dump_regs(I2CDevPtr d)
{
struct ivch_priv *priv = d->DriverPrivate.ptr;
uint16_t val;
ivch_read(priv, VR00, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR00: 0x%04x\n", val);
ivch_read(priv, VR01, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR01: 0x%04x\n", val);
ivch_read(priv, VR30, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR30: 0x%04x\n", val);
ivch_read(priv, VR40, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR40: 0x%04x\n", val);
/* GPIO registers */
ivch_read(priv, VR80, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR80: 0x%04x\n", val);
ivch_read(priv, VR81, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR81: 0x%04x\n", val);
ivch_read(priv, VR82, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR82: 0x%04x\n", val);
ivch_read(priv, VR83, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR83: 0x%04x\n", val);
ivch_read(priv, VR84, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR84: 0x%04x\n", val);
ivch_read(priv, VR85, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR85: 0x%04x\n", val);
ivch_read(priv, VR86, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR86: 0x%04x\n", val);
ivch_read(priv, VR87, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR87: 0x%04x\n", val);
ivch_read(priv, VR88, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR88: 0x%04x\n", val);
/* Scratch register 0 - AIM Panel type */
ivch_read(priv, VR8E, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR8E: 0x%04x\n", val);
/* Scratch register 1 - Status register */
ivch_read(priv, VR8F, &val);
xf86DrvMsg(priv->d.pI2CBus->scrnIndex, X_INFO, "VR8F: 0x%04x\n", val);
}
static void
ivch_save(I2CDevPtr d)
{
struct ivch_priv *priv = d->DriverPrivate.ptr;
ivch_read(priv, VR01, &priv->save_VR01);
ivch_read(priv, VR40, &priv->save_VR40);
}
static void
ivch_restore(I2CDevPtr d)
{
struct ivch_priv *priv = d->DriverPrivate.ptr;
ivch_write(priv, VR01, priv->save_VR01);
ivch_write(priv, VR40, priv->save_VR40);
}
_X_EXPORT I830I2CVidOutputRec ivch_methods = {
.init = ivch_init,
.dpms = ivch_dpms,
.save = ivch_save,
.restore = ivch_restore,
.mode_valid = ivch_mode_valid,
.mode_set = ivch_mode_set,
.detect = ivch_detect,
.dump_regs = ivch_dump_regs,
};

64
src/ivch/ivch_module.c
View File

@ -1,64 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(ivch_setup);
static XF86ModuleVersionInfo ivch_version = {
"ivch",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{ 0,0,0,0 }
};
_X_EXPORT XF86ModuleData ivchModuleData = {
&ivch_version,
ivch_setup,
NULL
};
static pointer
ivch_setup(pointer module, pointer opts, int *errmaj, int *errmin)
{
return (pointer)1;
}

291
src/ivch/ivch_reg.h
View File

@ -1,291 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
/*
* Copyright © 2006 Intel Corporation
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
* DEALINGS IN THE SOFTWARE.
*
* Authors:
* Eric Anholt <eric@anholt.net>
*
*/
/** @file
* This file contains the register definitions for the i82807aa.
*
* Documentation on this chipset can be found in datasheet #29069001 at
* intel.com.
*/
#ifndef I82807AA_REG_H
#define I82807AA_REG_H
/** @defgroup VR00 VCH Revision & GMBus Base Addr
* @{
*/
#define VR00 0x00
# define VR00_BASE_ADDRESS_MASK 0x007f
/** @} */
/** @defgroup VR01 VCH Functionality Enable
* @{
*/
#define VR01 0x01
/**
* Enable the panel fitter
*/
# define VR01_PANEL_FIT_ENABLE (1 << 3)
/**
* Enables the LCD display.
*
* This must not be set while VR01_DVO_BYPASS_ENABLE is set.
*/
# define VR01_LCD_ENABLE (1 << 2)
/** Enables the DVO repeater. */
# define VR01_DVO_BYPASS_ENABLE (1 << 1)
/** Enables the DVO clock */
# define VR01_DVO_ENABLE (1 << 0)
/** @} */
/** @defgroup VR10 LCD Interface Format
* @{
*/
#define VR10 0x10
/** Enables LVDS output instead of CMOS */
# define VR10_LVDS_ENABLE (1 << 4)
/** Enables 18-bit LVDS output. */
# define VR10_INTERFACE_1X18 (0 << 2)
/** Enables 24-bit LVDS or CMOS output */
# define VR10_INTERFACE_1X24 (1 << 2)
/** Enables 2x18-bit LVDS or CMOS output. */
# define VR10_INTERFACE_2X18 (2 << 2)
/** Enables 2x24-bit LVDS output */
# define VR10_INTERFACE_2X24 (3 << 2)
/** @} */
/** @defgroup VR11 CMOS Output Control
* @{
*/
/** @} */
/** @defgroup VR12 LVDS Output Control
* @{
*/
/** @} */
/** @defgroup VR18 PLL clock select
* @{
*/
/** @} */
/** @defgroup VR19 PLL clock divisor M
* @{
*/
/** @} */
/** @defgroup VR1A PLL clock divisor N
* @{
*/
/** @} */
/** @defgroup VR1F FIFO Pre-load
* @{
*/
/** @} */
/** @defgroup VR20 LCD Horizontal Display Size
* @{
*/
#define VR20 0x20
/** @} */
/** @defgroup VR21 LCD Vertical Display Size
* @{
*/
#define VR21 0x20
/** @} */
/** @defgroup VR22 Horizontal TRP to DE Start Delay
* @{
*/
/** @} */
/** @defgroup VR23 Horizontal TRP to DE End Delay
* @{
*/
/** @} */
/** @defgroup VR24 Horizontal TRP To LP Start Delay
* @{
*/
/** @} */
/** @defgroup VR25 Horizontal TRP To LP End Delay
* @{
*/
/** @} */
/** @defgroup VR26 Vertical TRP To FLM Start Delay
* @{
*/
/** @} */
/** @defgroup VR27 Vertical TRP To FLM End Delay
* @{
*/
/** @} */
/** @defgroup VR30 Panel power down status
* @{
*/
#define VR30 0x30
/** Read only bit indicating that the panel is not in a safe poweroff state. */
# define VR30_PANEL_ON (1 << 15)
/** @} */
/** @defgroup VR31 Tpon Panel power on sequencing delay
* @{
*/
/** @} */
/** @defgroup VR32 Tpon Panel power off sequencing delay
* @{
*/
/** @} */
/** @defgroup VR33 Tstay Panel power off stay down delay
* @{
*/
/** @} */
/** @defgroup VR34 Maximal FLM Pulse Interval
* @{
*/
/** @} */
/** @defgroup VR35 Maximal LP Pulse Interval
* @{
*/
/** @} */
/** @defgroup VR40
* @{
*/
#define VR40 0x40
# define VR40_STALL_ENABLE (1 << 13)
# define VR40_VERTICAL_INTERP_ENABLE (1 << 12)
# define VR40_ENHANCED_PANEL_FITTING (1 << 11)
# define VR40_HORIZONTAL_INTERP_ENABLE (1 << 10)
# define VR40_AUTO_RATIO_ENABLE (1 << 9)
# define VR40_CLOCK_GATING_ENABLE (1 << 8)
/** @} */
/** @defgroup VR41 Panel Fitting Vertical Ratio
* @{
*
* (((image_height - 1) << 16) / ((panel_height - 1))) >> 2
*/
/** @} */
#define VR41 0x41
/** @defgroup VR42 Panel Fitting Horizontal Ratio
* @{
* (((image_width - 1) << 16) / ((panel_width - 1))) >> 2
*/
/** @} */
#define VR42 0x42
/** @defgroup VR43 Horizontal Image Size
* @{
*/
/** @} */
#define VR43 0x43
/** @defgroup VR44 Panel Fitting Coefficient 0
* @{
*/
/** @} */
/** @defgroup VR45 Panel Fitting Coefficient 1
* @{
*/
/** @} */
/** @defgroup VR46 Panel Fitting Coefficient 2
* @{
*/
/** @} */
/** @defgroup VR47 Panel Fitting Coefficient 3
* @{
*/
/** @} */
/** @defgroup VR48 Panel Fitting Coefficient 4
* @{
*/
/** @} */
/** @defgroup VR49 Panel Fitting Coefficient 5
* @{
*/
/** @} */
/** @defgroup VR80 GPIO 0
* @{
*/
/** @} */
#define VR80 0x80
#define VR81 0x81
#define VR82 0x82
#define VR83 0x83
#define VR84 0x84
#define VR85 0x85
#define VR86 0x86
#define VR87 0x87
/** @defgroup VR88 GPIO 8
* @{
*/
/** @} */
#define VR88 0x88
/** @defgroup VR8E Graphics BIOS scratch 0
* @{
*/
#define VR8E 0x8E
# define VR8E_PANEL_TYPE_MASK (0xf << 0)
# define VR8E_PANEL_INTERFACE_CMOS (0 << 4)
# define VR8E_PANEL_INTERFACE_LVDS (1 << 4)
# define VR8E_FORCE_DEFAULT_PANEL (1 << 5)
/** @} */
/** @defgroup VR8F Graphics BIOS scratch 1
* @{
*/
#define VR8F 0x8F
# define VR8F_VCH_PRESENT (1 << 0)
# define VR8F_DISPLAY_CONN (1 << 1)
# define VR8F_POWER_MASK (0x3c)
# define VR8F_POWER_POS (2)
/** @} */
#endif /* I82807AA_REG_H */

3
src/reg_dumper/statuspage.c
View File

@ -39,6 +39,9 @@
#include "reg_dumper.h" #include "reg_dumper.h"
#include "../i810_reg.h" #include "../i810_reg.h"
#define HWS_NEED_GFX(pI810) ((IS_G33CLASS(pI810) ||\
IS_G4X(pI810) || IS_IGDNG(pI810)))
int main(int argc, char **argv) int main(int argc, char **argv)
{ {
I830Rec i830; I830Rec i830;

17
src/sil164/Makefile.am
View File

@ -1,17 +0,0 @@
# this is obnoxious:
# -module lets us name the module exactly how we want
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
@PCIACCESS_CFLAGS@
sil164_la_LTLIBRARIES = sil164.la
sil164_la_LDFLAGS = -module -avoid-version
sil164_ladir = @moduledir@/drivers
sil164_la_SOURCES = \
sil164.c \
sil164_module.c \
sil164.h \
sil164_reg.h

270
src/sil164/sil164.c
View File

@ -1,270 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
/**************************************************************************
Copyright © 2006 Dave Airlie
All Rights Reserved.
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the
"Software"), to deal in the Software without restriction, including
without limitation the rights to use, copy, modify, merge, publish,
distribute, sub license, and/or sell copies of the Software, and to
permit persons to whom the Software is furnished to do so, subject to
the following conditions:
The above copyright notice and this permission notice (including the
next paragraph) shall be included in all copies or substantial portions
of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdint.h>
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "miscstruct.h"
#include "xf86i2c.h"
#include "xf86Crtc.h"
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include "../i2c_vid.h"
#include "sil164.h"
#include "sil164_reg.h"
typedef struct _Sil164SaveRec {
uint8_t reg8;
uint8_t reg9;
uint8_t regc;
} SIL164SaveRec;
typedef struct {
I2CDevRec d;
Bool quiet;
SIL164SaveRec SavedReg;
SIL164SaveRec ModeReg;
} SIL164Rec, *SIL164Ptr;
#define SILPTR(d) ((SIL164Ptr)(d->DriverPrivate.ptr))
static Bool
sil164ReadByte(SIL164Ptr sil, int addr, uint8_t *ch)
{
if (!xf86I2CReadByte(&(sil->d), addr, ch)) {
if (!sil->quiet) {
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to read from %s Slave %d.\n",
sil->d.pI2CBus->BusName, sil->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
static Bool
sil164WriteByte(SIL164Ptr sil, int addr, uint8_t ch)
{
if (!xf86I2CWriteByte(&(sil->d), addr, ch)) {
if (!sil->quiet) {
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to write to %s Slave %d.\n",
sil->d.pI2CBus->BusName, sil->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
/* Silicon Image 164 driver for chip on i2c bus */
static void *
sil164_init(I2CBusPtr b, I2CSlaveAddr addr)
{
/* this will detect the SIL164 chip on the specified i2c bus */
SIL164Ptr sil;
unsigned char ch;
sil = xcalloc(1, sizeof(SIL164Rec));
if (sil == NULL)
return NULL;
sil->d.DevName = "SIL164 TMDS Controller";
sil->d.SlaveAddr = addr;
sil->d.pI2CBus = b;
sil->d.StartTimeout = b->StartTimeout;
sil->d.BitTimeout = b->BitTimeout;
sil->d.AcknTimeout = b->AcknTimeout;
sil->d.ByteTimeout = b->ByteTimeout;
sil->d.DriverPrivate.ptr = sil;
sil->quiet = TRUE;
if (!sil164ReadByte(sil, SIL164_VID_LO, &ch))
goto out;
if (ch!=(SIL164_VID & 0xFF)) {
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_ERROR,
"sil164 not detected got %d: from %s Slave %d.\n",
ch, sil->d.pI2CBus->BusName, sil->d.SlaveAddr);
goto out;
}
if (!sil164ReadByte(sil, SIL164_DID_LO, &ch))
goto out;
if (ch!=(SIL164_DID & 0xFF)) {
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_ERROR,
"sil164 not detected got %d: from %s Slave %d.\n",
ch, sil->d.pI2CBus->BusName, sil->d.SlaveAddr);
goto out;
}
sil->quiet = FALSE;
if (!xf86I2CDevInit(&(sil->d))) {
goto out;
}
return sil;
out:
xfree(sil);
return NULL;
}
static xf86OutputStatus
sil164_detect(I2CDevPtr d)
{
SIL164Ptr sil = SILPTR(d);
uint8_t reg9;
sil164ReadByte(sil, SIL164_REG9, &reg9);
if (reg9 & SIL164_9_HTPLG)
return XF86OutputStatusConnected;
else
return XF86OutputStatusDisconnected;
}
static ModeStatus
sil164_mode_valid(I2CDevPtr d, DisplayModePtr mode)
{
return MODE_OK;
}
static void
sil164_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
{
/* As long as the basics are set up, since we don't have clock dependencies
* in the mode setup, we can just leave the registers alone and everything
* will work fine.
*/
/* recommended programming sequence from doc */
/*sil164WriteByte(sil, 0x08, 0x30);
sil164WriteByte(sil, 0x09, 0x00);
sil164WriteByte(sil, 0x0a, 0x90);
sil164WriteByte(sil, 0x0c, 0x89);
sil164WriteByte(sil, 0x08, 0x31);*/
/* don't do much */
return;
}
/* set the SIL164 power state */
static void
sil164_dpms(I2CDevPtr d, int mode)
{
SIL164Ptr sil = SILPTR(d);
int ret;
unsigned char ch;
ret = sil164ReadByte(sil, SIL164_REG8, &ch);
if (ret == FALSE)
return;
if (mode == DPMSModeOn)
ch |= SIL164_8_PD;
else
ch &= ~SIL164_8_PD;
sil164WriteByte(sil, SIL164_REG8, ch);
return;
}
static void
sil164_dump_regs(I2CDevPtr d)
{
SIL164Ptr sil = SILPTR(d);
uint8_t val;
sil164ReadByte(sil, SIL164_FREQ_LO, &val);
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_INFO, "SIL164_FREQ_LO: 0x%02x\n",
val);
sil164ReadByte(sil, SIL164_FREQ_HI, &val);
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_INFO, "SIL164_FREQ_HI: 0x%02x\n",
val);
sil164ReadByte(sil, SIL164_REG8, &val);
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_INFO, "SIL164_REG8: 0x%02x\n", val);
sil164ReadByte(sil, SIL164_REG9, &val);
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_INFO, "SIL164_REG9: 0x%02x\n", val);
sil164ReadByte(sil, SIL164_REGC, &val);
xf86DrvMsg(sil->d.pI2CBus->scrnIndex, X_INFO, "SIL164_REGC: 0x%02x\n", val);
}
static void
sil164_save(I2CDevPtr d)
{
SIL164Ptr sil = SILPTR(d);
if (!sil164ReadByte(sil, SIL164_REG8, &sil->SavedReg.reg8))
return;
if (!sil164ReadByte(sil, SIL164_REG9, &sil->SavedReg.reg9))
return;
if (!sil164ReadByte(sil, SIL164_REGC, &sil->SavedReg.regc))
return;
return;
}
static void
sil164_restore(I2CDevPtr d)
{
SIL164Ptr sil = SILPTR(d);
/* Restore it powered down initially */
sil164WriteByte(sil, SIL164_REG8, sil->SavedReg.reg8 & ~0x1);
sil164WriteByte(sil, SIL164_REG9, sil->SavedReg.reg9);
sil164WriteByte(sil, SIL164_REGC, sil->SavedReg.regc);
sil164WriteByte(sil, SIL164_REG8, sil->SavedReg.reg8);
}
_X_EXPORT I830I2CVidOutputRec SIL164VidOutput = {
.init = sil164_init,
.detect = sil164_detect,
.mode_valid = sil164_mode_valid,
.mode_set = sil164_mode_set,
.dpms = sil164_dpms,
.dump_regs = sil164_dump_regs,
.save = sil164_save,
.restore = sil164_restore,
};

31
src/sil164/sil164.h
View File

@ -1,31 +0,0 @@
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifndef SIL164_H
#define SIL164_H
#define SIL164_ADDR_1 0x38
#endif

38
src/sil164/sil164_module.c
View File

@ -1,38 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(sil164Setup);
static XF86ModuleVersionInfo sil164VersRec = {
"sil164",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{ 0,0,0,0 }
};
_X_EXPORT XF86ModuleData sil164ModuleData = {
&sil164VersRec,
sil164Setup,
NULL
};
static pointer
sil164Setup(pointer module, pointer opts, int *errmaj, int *errmin)
{
return (pointer)1;
}

60
src/sil164/sil164_reg.h
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@ -1,60 +0,0 @@
/* -*- c-basic-offset: 4 -*- */
/**************************************************************************
Copyright 2006 Dave Airlie <airlied@linux.ie>
Permission is hereby granted, free of charge, to any person obtaining a
copy of this software and associated documentation files (the "Software"),
to deal in the Software without restriction, including without limitation
on the rights to use, copy, modify, merge, publish, distribute, sub
license, and/or sell copies of the Software, and to permit persons to whom
the Software is furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice (including the next
paragraph) shall be included in all copies or substantial portions of the
Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
THE COPYRIGHT HOLDERS AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
USE OR OTHER DEALINGS IN THE SOFTWARE.
**************************************************************************/
#ifndef SIL164_REG_H
#define SIL164_REG_H
#define SIL164_VID 0x0001
#define SIL164_DID 0x0006
#define SIL164_VID_LO 0x00
#define SIL164_VID_HI 0x01
#define SIL164_DID_LO 0x02
#define SIL164_DID_HI 0x03
#define SIL164_REV 0x04
#define SIL164_RSVD 0x05
#define SIL164_FREQ_LO 0x06
#define SIL164_FREQ_HI 0x07
#define SIL164_REG8 0x08
#define SIL164_8_VEN (1<<5)
#define SIL164_8_HEN (1<<4)
#define SIL164_8_DSEL (1<<3)
#define SIL164_8_BSEL (1<<2)
#define SIL164_8_EDGE (1<<1)
#define SIL164_8_PD (1<<0)
#define SIL164_REG9 0x09
#define SIL164_9_VLOW (1<<7)
#define SIL164_9_MSEL_MASK (0x7<<4)
#define SIL164_9_TSEL (1<<3)
#define SIL164_9_RSEN (1<<2)
#define SIL164_9_HTPLG (1<<1)
#define SIL164_9_MDI (1<<0)
#define SIL164_REGC 0x0c
#endif

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src/tfp410/Makefile.am
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@ -1,17 +0,0 @@
# this is obnoxious:
# -module lets us name the module exactly how we want
# -avoid-version prevents gratuitous .0.0.0 version numbers on the end
# _ladir passes a dummy rpath to libtool so the thing will actually link
# TODO: -nostdlib/-Bstatic/-lgcc platform magic, not installing the .a, etc.
AM_CFLAGS = @WARN_CFLAGS@ @XORG_CFLAGS@ @DRI_CFLAGS@ \
@PCIACCESS_CFLAGS@
tfp410_la_LTLIBRARIES = tfp410.la
tfp410_la_LDFLAGS = -module -avoid-version
tfp410_ladir = @moduledir@/drivers
tfp410_la_SOURCES = \
tfp410.c \
tfp410_module.c \
tfp410.h \
tfp410_reg.h

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src/tfp410/tfp410.c
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/* -*- c-basic-offset: 4 -*- */
/*
* Copyright © 2007 Dave Mueller
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Dave Mueller <dave.mueller@gmx.ch>
*
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdint.h>
#include "xf86.h"
#include "xf86_OSproc.h"
#include "compiler.h"
#include "miscstruct.h"
#include "xf86i2c.h"
#include "xf86Crtc.h"
#ifdef HAVE_XEXTPROTO_71
#include <X11/extensions/dpmsconst.h>
#else
#define DPMS_SERVER
#include <X11/extensions/dpms.h>
#endif
#include "../i2c_vid.h"
#include "tfp410.h"
#include "tfp410_reg.h"
typedef struct _TFP410SaveRec {
uint8_t ctl1;
uint8_t ctl2;
} TFP410SaveRec;
typedef struct {
I2CDevRec d;
Bool quiet;
TFP410SaveRec SavedReg;
TFP410SaveRec ModeReg;
} TFP410Rec, *TFP410Ptr;
#define TFPPTR(d) ((TFP410Ptr)(d->DriverPrivate.ptr))
static Bool
tfp410ReadByte(TFP410Ptr tfp, int addr, uint8_t *ch)
{
if (!xf86I2CReadByte(&(tfp->d), addr, ch)) {
if (!tfp->quiet) {
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to read from %s Slave %d.\n",
tfp->d.pI2CBus->BusName, tfp->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
static Bool
tfp410WriteByte(TFP410Ptr tfp, int addr, uint8_t ch)
{
if (!xf86I2CWriteByte(&(tfp->d), addr, ch)) {
if (!tfp->quiet) {
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_ERROR,
"Unable to write to %s Slave %d.\n",
tfp->d.pI2CBus->BusName, tfp->d.SlaveAddr);
}
return FALSE;
}
return TRUE;
}
static int
tfp410GetID(TFP410Ptr tfp, int addr)
{
unsigned char ch1, ch2;
if (tfp410ReadByte(tfp, addr+0, &ch1) &&
tfp410ReadByte(tfp, addr+1, &ch2)) {
return ((ch2<<8) & 0xFF00) | (ch1 & 0x00FF);
}
return -1;
}
/* Ti TFP410 driver for chip on i2c bus */
static void *
tfp410_init(I2CBusPtr b, I2CSlaveAddr addr)
{
/* this will detect the tfp410 chip on the specified i2c bus */
TFP410Ptr tfp;
int id;
tfp = xcalloc(1, sizeof(TFP410Rec));
if (tfp == NULL)
return NULL;
tfp->d.DevName = "TFP410 TMDS Controller";
tfp->d.SlaveAddr = addr;
tfp->d.pI2CBus = b;
tfp->d.StartTimeout = b->StartTimeout;
tfp->d.BitTimeout = b->BitTimeout;
tfp->d.AcknTimeout = b->AcknTimeout;
tfp->d.ByteTimeout = b->ByteTimeout;
tfp->d.DriverPrivate.ptr = tfp;
tfp->quiet = TRUE;
if ((id = tfp410GetID(tfp, TFP410_VID_LO)) != TFP410_VID) {
if (id != 0xffffffff) {
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_ERROR,
"tfp410 not detected got VID %X: from %s Slave %d.\n",
id, tfp->d.pI2CBus->BusName, tfp->d.SlaveAddr);
}
goto out;
}
if ((id = tfp410GetID(tfp, TFP410_DID_LO)) != TFP410_DID) {
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_ERROR,
"tfp410 not detected got DID %X: from %s Slave %d.\n",
id, tfp->d.pI2CBus->BusName, tfp->d.SlaveAddr);
goto out;
}
tfp->quiet = FALSE;
if (!xf86I2CDevInit(&(tfp->d))) {
goto out;
}
return tfp;
out:
xfree(tfp);
return NULL;
}
static xf86OutputStatus
tfp410_detect(I2CDevPtr d)
{
TFP410Ptr tfp = TFPPTR(d);
xf86OutputStatus ret = XF86OutputStatusDisconnected;
unsigned char ctl2;
if (tfp410ReadByte(tfp, TFP410_CTL_2, &ctl2)) {
if (ctl2 & TFP410_CTL_2_HTPLG)
ret = XF86OutputStatusConnected;
else
ret = XF86OutputStatusDisconnected;
}
return ret;
}
static ModeStatus
tfp410_mode_valid(I2CDevPtr d, DisplayModePtr mode)
{
return MODE_OK;
}
static void
tfp410_mode_set(I2CDevPtr d, DisplayModePtr mode, DisplayModePtr adjusted_mode)
{
/* As long as the basics are set up, since we don't have clock dependencies
* in the mode setup, we can just leave the registers alone and everything
* will work fine.
*/
/* don't do much */
return;
}
/* set the tfp410 power state */
static void
tfp410_dpms(I2CDevPtr d, int mode)
{
TFP410Ptr tfp = TFPPTR(d);
unsigned char ctl1;
if (!tfp410ReadByte(tfp, TFP410_CTL_1, &ctl1))
return;
if (mode == DPMSModeOn)
ctl1 |= TFP410_CTL_1_PD;
else
ctl1 &= ~TFP410_CTL_1_PD;
tfp410WriteByte(tfp, TFP410_CTL_1, ctl1);
}
static void
tfp410_dump_regs(I2CDevPtr d)
{
TFP410Ptr tfp = TFPPTR(d);
uint8_t val, val2;
tfp410ReadByte(tfp, TFP410_REV, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_REV: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_CTL_1, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_CTL1: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_CTL_2, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_CTL2: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_CTL_3, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_CTL3: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_USERCFG, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_USERCFG: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_DE_DLY, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_DE_DLY: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_DE_CTL, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_DE_CTL: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_DE_TOP, &val);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_DE_TOP: 0x%02X\n", val);
tfp410ReadByte(tfp, TFP410_DE_CNT_LO, &val);
tfp410ReadByte(tfp, TFP410_DE_CNT_HI, &val2);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
tfp410ReadByte(tfp, TFP410_DE_LIN_LO, &val);
tfp410ReadByte(tfp, TFP410_DE_LIN_HI, &val2);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
tfp410ReadByte(tfp, TFP410_H_RES_LO, &val);
tfp410ReadByte(tfp, TFP410_H_RES_HI, &val2);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_H_RES: 0x%02X%02X\n", val2, val);
tfp410ReadByte(tfp, TFP410_V_RES_LO, &val);
tfp410ReadByte(tfp, TFP410_V_RES_HI, &val2);
xf86DrvMsg(tfp->d.pI2CBus->scrnIndex, X_INFO,
"TFP410_V_RES: 0x%02X%02X\n", val2, val);
}
static void
tfp410_save(I2CDevPtr d)
{
TFP410Ptr tfp = TFPPTR(d);
if (!tfp410ReadByte(tfp, TFP410_CTL_1, &tfp->SavedReg.ctl1))
return;
if (!tfp410ReadByte(tfp, TFP410_CTL_2, &tfp->SavedReg.ctl2))
return;
}
static void
tfp410_restore(I2CDevPtr d)
{
TFP410Ptr tfp = TFPPTR(d);
/* Restore it powered down initially */
tfp410WriteByte(tfp, TFP410_CTL_1, tfp->SavedReg.ctl1 & ~0x1);
tfp410WriteByte(tfp, TFP410_CTL_2, tfp->SavedReg.ctl2);
tfp410WriteByte(tfp, TFP410_CTL_1, tfp->SavedReg.ctl1);
}
_X_EXPORT I830I2CVidOutputRec TFP410VidOutput = {
.init = tfp410_init,
.detect = tfp410_detect,
.mode_valid = tfp410_mode_valid,
.mode_set = tfp410_mode_set,
.dpms = tfp410_dpms,
.dump_regs = tfp410_dump_regs,
.save = tfp410_save,
.restore = tfp410_restore,
};

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/*
* Copyright © 2007 Dave Mueller
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Dave Mueller <dave.mueller@gmx.ch>
*
*/
#ifndef TFP410_H
#define TFP410_H
#define TFP410_ADDR_1 0x38
#endif

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src/tfp410/tfp410_module.c
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/* -*- c-basic-offset: 4 -*- */
#ifdef HAVE_XORG_CONFIG_H
#include <xorg-config.h>
#endif
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "xf86Module.h"
static MODULESETUPPROTO(tfp410Setup);
static XF86ModuleVersionInfo tfp410VersRec = {
"tfp410",
MODULEVENDORSTRING,
MODINFOSTRING1,
MODINFOSTRING2,
XORG_VERSION_CURRENT,
1, 0, 0,
ABI_CLASS_VIDEODRV,
ABI_VIDEODRV_VERSION,
MOD_CLASS_NONE,
{ 0,0,0,0 }
};
_X_EXPORT XF86ModuleData tfp410ModuleData = {
&tfp410VersRec,
tfp410Setup,
NULL
};
static pointer
tfp410Setup(pointer module, pointer opts, int *errmaj, int *errmin)
{
return (pointer)1;
}

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src/tfp410/tfp410_reg.h
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/* -*- c-basic-offset: 4 -*- */
/*
* Copyright © 2007 Dave Mueller
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice (including the next
* paragraph) shall be included in all copies or substantial portions of the
* Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
* IN THE SOFTWARE.
*
* Authors:
* Dave Mueller <dave.mueller@gmx.ch>
*
*/
#ifndef TFP410_REG_H
#define TFP410_REG_H
/* register definitions according to the TFP410 data sheet */
#define TFP410_VID 0x014C
#define TFP410_DID 0x0410
#define TFP410_VID_LO 0x00
#define TFP410_VID_HI 0x01
#define TFP410_DID_LO 0x02
#define TFP410_DID_HI 0x03
#define TFP410_REV 0x04
#define TFP410_CTL_1 0x08
#define TFP410_CTL_1_TDIS (1<<6)
#define TFP410_CTL_1_VEN (1<<5)
#define TFP410_CTL_1_HEN (1<<4)
#define TFP410_CTL_1_DSEL (1<<3)
#define TFP410_CTL_1_BSEL (1<<2)
#define TFP410_CTL_1_EDGE (1<<1)
#define TFP410_CTL_1_PD (1<<0)
#define TFP410_CTL_2 0x09
#define TFP410_CTL_2_VLOW (1<<7)
#define TFP410_CTL_2_MSEL_MASK (0x7<<4)
#define TFP410_CTL_2_MSEL (1<<4)
#define TFP410_CTL_2_TSEL (1<<3)
#define TFP410_CTL_2_RSEN (1<<2)
#define TFP410_CTL_2_HTPLG (1<<1)
#define TFP410_CTL_2_MDI (1<<0)
#define TFP410_CTL_3 0x0A
#define TFP410_CTL_3_DK_MASK (0x7<<5)
#define TFP410_CTL_3_DK (1<<5)
#define TFP410_CTL_3_DKEN (1<<4)
#define TFP410_CTL_3_CTL_MASK (0x7<<1)
#define TFP410_CTL_3_CTL (1<<1)
#define TFP410_USERCFG 0x0B
#define TFP410_DE_DLY 0x32
#define TFP410_DE_CTL 0x33
#define TFP410_DE_CTL_DEGEN (1<<6)
#define TFP410_DE_CTL_VSPOL (1<<5)
#define TFP410_DE_CTL_HSPOL (1<<4)
#define TFP410_DE_CTL_DEDLY8 (1<<0)
#define TFP410_DE_TOP 0x34
#define TFP410_DE_CNT_LO 0x36
#define TFP410_DE_CNT_HI 0x37
#define TFP410_DE_LIN_LO 0x38
#define TFP410_DE_LIN_HI 0x39
#define TFP410_H_RES_LO 0x3A
#define TFP410_H_RES_HI 0x3B
#define TFP410_V_RES_LO 0x3C
#define TFP410_V_RES_HI 0x3D
#endif