uxa: Reuse in-flight bo
When we need to allocate a new bo for use as a gpu target, first check if we can reuse a pixmap that has already been relocated into the aperture as a temporary target, for instance a glyph mask or a clip mask. Before: backend test min(s) median(s) stddev. xlib firefox-planet-gnome 50.568 50.873 0.30% xcb firefox-planet-gnome 49.686 53.003 3.92% xlib evolution 40.115 40.131 0.86% xcb evolution 28.241 28.285 0.18% After: backend test min(s) median(s) stddev. xlib firefox-planet-gnome 47.759 48.233 0.80% xcb firefox-planet-gnome 48.611 48.657 0.87% xlib evolution 38.954 38.991 0.05% xcb evolution 26.561 26.654 0.19% And even more dramatic improvements when using a font size larger than the maximum size of the glyph cache: xcb firefox-36-20090611: 1.79x speedup xlib firefox-36-20090611: 1.74x speedup xcb firefox-36-20090609: 1.62x speedup xlib firefox-36-20090609: 1.59x speedup Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson
parent
96aa7a236a
commit
c374c94e41
13
src/i830.h
13
src/i830.h
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@ -136,14 +136,22 @@ list_is_empty(struct list *head)
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#define list_first_entry(ptr, type, member) \
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list_entry((ptr)->next, type, member)
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#define list_foreach(pos, head) \
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for (pos = (head)->next; pos != (head); pos = pos->next)
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#define list_foreach_entry(pos, type, head, member) \
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for (pos = list_entry((head)->next, type, member);\
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&pos->member != (head); \
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pos = list_entry(pos->member.next, type, member))
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struct intel_pixmap {
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dri_bo *bo;
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uint32_t tiling;
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uint32_t tiling, stride;
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uint32_t flush_write_domain;
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uint32_t flush_read_domains;
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uint32_t batch_write_domain;
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uint32_t batch_read_domains;
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struct list flush, batch;
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struct list flush, batch, in_flight;
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};
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struct intel_pixmap *i830_get_pixmap_intel(PixmapPtr pixmap);
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@ -252,6 +260,7 @@ typedef struct intel_screen_private {
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int batch_atomic_limit;
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struct list batch_pixmaps;
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struct list flush_pixmaps;
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struct list in_flight;
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/* For Xvideo */
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Bool use_drmmode_overlay;
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@ -195,6 +195,18 @@ void intel_batch_submit(ScrnInfoPtr scrn)
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list_del(&entry->flush);
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}
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while (!list_is_empty(&intel->in_flight)) {
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struct intel_pixmap *entry;
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entry = list_first_entry(&intel->in_flight,
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struct intel_pixmap,
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in_flight);
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dri_bo_unreference(entry->bo);
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list_del(&entry->in_flight);
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xfree(entry);
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}
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/* Save a ref to the last batch emitted, which we use for syncing
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* in debug code.
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*/
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@ -1054,6 +1054,7 @@ void i830_init_bufmgr(ScrnInfoPtr scrn)
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list_init(&intel->batch_pixmaps);
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list_init(&intel->flush_pixmaps);
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list_init(&intel->in_flight);
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}
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Bool i830_crtc_on(xf86CrtcPtr crtc)
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@ -127,7 +127,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
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{
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ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
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intel_screen_private *intel = intel_get_screen_private(scrn);
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int pitch_align;
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int pitch, pitch_align;
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int size;
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if (*tiling != I915_TILING_NONE) {
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@ -151,6 +151,9 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
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}
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}
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pitch = (w * pixmap->drawable.bitsPerPixel + 7) / 8;
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if (pitch <= 256)
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*tiling = I915_TILING_NONE;
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repeat:
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if (*tiling == I915_TILING_NONE) {
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pitch_align = intel->accel_pixmap_pitch_alignment;
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@ -158,8 +161,7 @@ i830_uxa_pixmap_compute_size(PixmapPtr pixmap,
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pitch_align = 512;
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}
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*stride = ROUND_TO((w * pixmap->drawable.bitsPerPixel + 7) / 8,
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pitch_align);
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*stride = ROUND_TO(pitch, pitch_align);
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if (*tiling == I915_TILING_NONE) {
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/* Round the height up so that the GPU's access to a 2x2 aligned
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@ -548,17 +550,19 @@ dri_bo *i830_get_pixmap_bo(PixmapPtr pixmap)
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void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
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{
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ScrnInfoPtr scrn = xf86Screens[pixmap->drawable.pScreen->myNum];
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intel_screen_private *intel = intel_get_screen_private(scrn);
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struct intel_pixmap *priv;
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priv = i830_get_pixmap_intel(pixmap);
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if (priv != NULL) {
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dri_bo_unreference(priv->bo);
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priv->flush_read_domains = priv->flush_write_domain = 0;
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priv->batch_read_domains = priv->batch_write_domain = 0;
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list_del(&priv->batch);
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list_del(&priv->flush);
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if (list_is_empty(&priv->batch)) {
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dri_bo_unreference(priv->bo);
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} else {
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list_add(&priv->in_flight, &intel->in_flight);
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priv = NULL;
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}
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}
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if (bo != NULL) {
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@ -576,6 +580,7 @@ void i830_set_pixmap_bo(PixmapPtr pixmap, dri_bo * bo)
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dri_bo_reference(bo);
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priv->bo = bo;
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priv->stride = i830_pixmap_pitch(pixmap);
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ret = drm_intel_bo_get_tiling(bo,
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&priv->tiling,
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@ -883,35 +888,26 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
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if (w && h) {
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struct intel_pixmap *priv;
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unsigned int size;
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unsigned int size, tiling;
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int stride;
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priv = xcalloc(1, sizeof (struct intel_pixmap));
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if (priv == NULL) {
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fbDestroyPixmap(pixmap);
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return NullPixmap;
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}
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/* Always attempt to tile, compute_size() will remove the
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* tiling for pixmaps that are either too large or too small
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* to be effectively tiled.
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*/
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priv->tiling = I915_TILING_X;
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tiling = I915_TILING_X;
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if (usage == INTEL_CREATE_PIXMAP_TILING_Y)
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priv->tiling = I915_TILING_Y;
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tiling = I915_TILING_Y;
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if (usage == UXA_CREATE_PIXMAP_FOR_MAP)
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priv->tiling = I915_TILING_NONE;
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tiling = I915_TILING_NONE;
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if (priv->tiling != I915_TILING_NONE) {
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if (w < 256)
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priv->tiling = I915_TILING_NONE;
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if (h < 8)
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priv->tiling = I915_TILING_NONE;
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if (h < 32 && priv->tiling == I915_TILING_Y)
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priv->tiling = I915_TILING_X;
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if (tiling != I915_TILING_NONE) {
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if (h <= 4)
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tiling = I915_TILING_NONE;
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if (h <= 16 && tiling == I915_TILING_Y)
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tiling = I915_TILING_X;
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}
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size = i830_uxa_pixmap_compute_size(pixmap, w, h,
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&priv->tiling, &stride);
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size = i830_uxa_pixmap_compute_size(pixmap, w, h, &tiling, &stride);
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/* Fail very large allocations on 32-bit systems. Large BOs will
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* tend to hit SW fallbacks frequently, and also will tend to fail
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@ -923,7 +919,37 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
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*/
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if (sizeof(unsigned long) == 4 &&
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size > (unsigned int)(1024 * 1024 * 1024)) {
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xfree(priv);
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fbDestroyPixmap(pixmap);
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return NullPixmap;
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}
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/* Perform a premilinary search for an in-flight bo */
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if (usage != UXA_CREATE_PIXMAP_FOR_MAP) {
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int aligned_h;
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if (tiling == I915_TILING_X)
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aligned_h = ALIGN(h, 8);
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else if (tiling == I915_TILING_Y)
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aligned_h = ALIGN(h, 32);
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else
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aligned_h = ALIGN(h, 2);
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list_foreach_entry(priv, struct intel_pixmap,
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&intel->in_flight,
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in_flight) {
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if (priv->tiling == tiling &&
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priv->stride >= stride &&
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priv->bo->size >= priv->stride * aligned_h) {
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list_del(&priv->in_flight);
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screen->ModifyPixmapHeader(pixmap, w, h, 0, 0, priv->stride, NULL);
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i830_uxa_set_pixmap_intel(pixmap, priv);
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return pixmap;
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}
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}
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}
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priv = xcalloc(1, sizeof (struct intel_pixmap));
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if (priv == NULL) {
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fbDestroyPixmap(pixmap);
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return NullPixmap;
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}
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@ -941,6 +967,8 @@ i830_uxa_create_pixmap(ScreenPtr screen, int w, int h, int depth,
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return NullPixmap;
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}
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priv->stride = stride;
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priv->tiling = tiling;
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if (priv->tiling != I915_TILING_NONE)
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drm_intel_bo_set_tiling(priv->bo,
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&priv->tiling,
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