Merge branch 'modesetting-origin' into modesetting
This commit is contained in:
commit
c70e7bc701
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@ -1663,9 +1663,6 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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pScrn->currentMode = pScrn->modes;
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#ifndef USE_PITCHES
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#define USE_PITCHES 1
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#endif
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pI830->disableTiling = FALSE;
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/*
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@ -1685,18 +1682,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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if (I830IsPrimary(pScrn) && !pI830->directRenderingDisabled) {
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int savedDisplayWidth = pScrn->displayWidth;
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int memNeeded = 0;
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/* Good pitches to allow tiling. Don't care about pitches < 1024. */
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static const int pitches[] = {
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/*
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128 * 2,
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128 * 4,
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*/
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128 * 8,
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128 * 16,
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128 * 32,
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128 * 64,
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0
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};
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Bool tiled = FALSE;
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#ifdef I830_XV
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/*
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@ -1706,16 +1692,28 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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pI830->XvEnabled = !pI830->XvDisabled;
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#endif
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for (i = 0; pitches[i] != 0; i++) {
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#if USE_PITCHES
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if (pitches[i] >= pScrn->displayWidth) {
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pScrn->displayWidth = pitches[i];
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break;
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if (IS_I965G(pI830)) {
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int tile_pixels = 512 / pI830->cpp;
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pScrn->displayWidth = (pScrn->displayWidth + tile_pixels - 1) &
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~(tile_pixels - 1);
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tiled = TRUE;
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} else {
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/* Good pitches to allow tiling. Don't care about pitches < 1024. */
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static const int pitches[] = {
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KB(1),
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KB(2),
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KB(4),
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KB(8),
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0
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};
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for (i = 0; pitches[i] != 0; i++) {
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if (pitches[i] >= pScrn->displayWidth) {
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pScrn->displayWidth = pitches[i];
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tiled = TRUE;
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break;
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}
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}
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#else
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if (pitches[i] == pScrn->displayWidth)
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break;
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#endif
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}
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/*
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@ -1723,7 +1721,7 @@ I830PreInit(ScrnInfoPtr pScrn, int flags)
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* memory available to enable tiling.
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*/
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savedMMSize = pI830->mmSize;
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if (pScrn->displayWidth == pitches[i]) {
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if (tiled) {
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retry_dryrun:
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I830ResetAllocations(pScrn, 0);
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if (I830Allocate2DMemory(pScrn, ALLOCATE_DRY_RUN | ALLOC_INITIAL) &&
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@ -438,20 +438,33 @@ AllocateOverlay(ScrnInfoPtr pScrn, int flags)
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#endif
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static Bool
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IsTileable(int pitch)
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IsTileable(ScrnInfoPtr pScrn, int pitch)
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{
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I830Ptr pI830 = I830PTR(pScrn);
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if (IS_I965G(pI830)) {
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if (pitch / 512 * 512 == pitch && pitch <= KB(128))
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return TRUE;
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else
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return FALSE;
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}
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/*
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* Allow tiling for pitches that are a power of 2 multiple of 128 bytes,
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* up to 64 * 128 (= 8192) bytes.
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*/
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switch (pitch) {
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case 128 * 1:
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case 128 * 2:
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case 128 * 4:
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case 128 * 8:
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case 128 * 16:
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case 128 * 32:
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case 128 * 64:
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case 128:
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case 256:
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if (IS_I945G(pI830) || IS_I945GM(pI830))
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return TRUE;
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else
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return FALSE;
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case 512:
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case KB(1):
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case KB(2):
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case KB(4):
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case KB(8):
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return TRUE;
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default:
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return FALSE;
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@ -475,7 +488,7 @@ I830AllocateRotatedBuffer(ScrnInfoPtr pScrn, int flags)
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memset(&(pI830->RotatedMem), 0, sizeof(I830MemRange));
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pI830->RotatedMem.Key = -1;
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tileable = !(flags & ALLOC_NO_TILING) &&
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IsTileable(pScrn->displayWidth * pI830->cpp);
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IsTileable(pScrn, pScrn->displayWidth * pI830->cpp);
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if (tileable) {
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/* Make the height a multiple of the tile height (16) */
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lines = (height + 15) / 16 * 16;
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@ -540,7 +553,7 @@ I830AllocateRotated2Buffer(ScrnInfoPtr pScrn, int flags)
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memset(&(pI830->RotatedMem2), 0, sizeof(I830MemRange));
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pI830->RotatedMem2.Key = -1;
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tileable = !(flags & ALLOC_NO_TILING) &&
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IsTileable(pI830Ent->pScrn_2->displayWidth * pI8302->cpp);
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IsTileable(pScrn, pI830Ent->pScrn_2->displayWidth * pI8302->cpp);
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if (tileable) {
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/* Make the height a multiple of the tile height (16) */
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lines = (height + 15) / 16 * 16;
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@ -699,7 +712,7 @@ I830AllocateFramebuffer(ScrnInfoPtr pScrn, I830Ptr pI830, BoxPtr FbMemBox,
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}
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tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
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IsTileable(pScrn->displayWidth * pI830->cpp);
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IsTileable(pScrn, pScrn->displayWidth * pI830->cpp);
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if (tileable) {
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if (IS_I9XX(pI830))
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align = MB(1);
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@ -886,7 +899,7 @@ I830Allocate2DMemory(ScrnInfoPtr pScrn, const int flags)
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maxFb / lineSize - pScrn->virtualY);
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pI830->FbMemBox.y2 = maxFb / lineSize;
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tileable = !(flags & ALLOC_NO_TILING) && pI830->allowPageFlip &&
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IsTileable(pScrn->displayWidth * pI830->cpp);
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IsTileable(pScrn, pScrn->displayWidth * pI830->cpp);
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if (tileable) {
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if (IS_I9XX(pI830))
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align = MB(1);
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@ -1113,7 +1126,7 @@ I830AllocateBackBuffer(ScrnInfoPtr pScrn, const int flags)
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memset(&(pI830->BackBuffer), 0, sizeof(pI830->BackBuffer));
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pI830->BackBuffer.Key = -1;
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tileable = !(flags & ALLOC_NO_TILING) &&
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IsTileable(pScrn->displayWidth * pI830->cpp);
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IsTileable(pScrn, pScrn->displayWidth * pI830->cpp);
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if (tileable) {
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/* Make the height a multiple of the tile height (16) */
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lines = (height + 15) / 16 * 16;
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@ -1176,7 +1189,7 @@ I830AllocateDepthBuffer(ScrnInfoPtr pScrn, const int flags)
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memset(&(pI830->DepthBuffer), 0, sizeof(pI830->DepthBuffer));
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pI830->DepthBuffer.Key = -1;
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tileable = !(flags & ALLOC_NO_TILING) &&
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IsTileable(pScrn->displayWidth * pI830->cpp);
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IsTileable(pScrn, pScrn->displayWidth * pI830->cpp);
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if (tileable) {
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/* Make the height a multiple of the tile height (16) */
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lines = (height + 15) / 16 * 16;
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@ -1714,7 +1727,7 @@ I830SetupMemoryTiling(ScrnInfoPtr pScrn)
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if (!pI830->directRenderingEnabled)
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return;
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if (!IsTileable(pScrn->displayWidth * pI830->cpp)) {
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if (!IsTileable(pScrn, pScrn->displayWidth * pI830->cpp)) {
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xf86DrvMsg(pScrn->scrnIndex, X_INFO,
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"I830SetupMemoryTiling: Not tileable 0x%x\n",
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pScrn->displayWidth * pI830->cpp);
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