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sna/gen8+: Discard any blt using a LINEAR buffer that is not 64byte aligned 

The bug we discovered back in

commit 3a22b6f6d5
Author: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Date:   Wed Nov 19 15:10:05 2014 +0200

    sna: gen8 BLT broken when address has bit 4 set

turns out to be even wider than our initial finding. It is now
recommended that you avoid using the BLT on LINEAR addresses that are not
cache-line aligned (64 bytes). You can convert the offset into a
coordinate offset (provided the address is at least pixel aligned), but
that remains quite hairy to fit into the current code base. So keep
saying no to misaligned blits (we either use the 3D engine instead,
which may end up thrashing the TLBs given the LINEAR layout, or we just
use the CPU).

The impact of issuing misaligned blits is that the blitter ends up
performing the blit presuming the aligned address, causing it to end up
offset (and vary per line).

Reported-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
This commit is contained in:
Chris Wilson 2017-08-22 20:20:23 +01:00
parent 7534e96ffb
commit c89905754b
1 changed files with 1 additions and 1 deletions
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2
src/sna/kgem.h
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@ -587,7 +587,7 @@ static inline bool kgem_bo_can_blt(struct kgem *kgem,
return false;
}
if (kgem->gen >= 0100 && bo->proxy && bo->delta & (1 << 4)) {
if (kgem->gen >= 0100 && bo->proxy && bo->delta & 63) {
DBG(("%s: can not blt to handle=%d, delta=%d\n",
__FUNCTION__, bo->handle, bo->delta));
return false;