From cae0ae237b79fa7d3a82dfc8d3fb595ccb6c63e1 Mon Sep 17 00:00:00 2001
From: Samuel Thibault <samuel.thibault@ens-lyon.org>
Date: Tue, 1 May 2007 12:41:18 -0700
Subject: [PATCH] Bug #10714: Fix build without DRI.

---
 src/i830.h        | 4 +++-
 src/i830_memory.c | 8 ++++++--
 2 files changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/i830.h b/src/i830.h
index f69ad737..8034302b 100644
--- a/src/i830.h
+++ b/src/i830.h
@@ -307,6 +307,9 @@ typedef struct _I830Rec {
    int *used3D;
 
    i830_memory *logical_context;
+
+   unsigned int front_tiled;
+
 #ifdef XF86DRI
    i830_memory *back_buffer;
    i830_memory *third_buffer;
@@ -319,7 +322,6 @@ typedef struct _I830Rec {
    int mmModeFlags;
    int mmSize;
 
-   unsigned int front_tiled;
    unsigned int back_tiled;
    unsigned int third_tiled;
    unsigned int depth_tiled;
diff --git a/src/i830_memory.c b/src/i830_memory.c
index 2cc93272..23e7dbca 100644
--- a/src/i830_memory.c
+++ b/src/i830_memory.c
@@ -231,11 +231,13 @@ i830_reset_allocations(ScrnInfoPtr pScrn)
     pI830->exa_965_state = NULL;
     pI830->overlay_regs = NULL;
     pI830->logical_context = NULL;
+#ifdef XF86DRI
     pI830->back_buffer = NULL;
     pI830->third_buffer = NULL;
     pI830->depth_buffer = NULL;
     pI830->textures = NULL;
     pI830->memory_manager = NULL;
+#endif
     pI830->LpRing->mem = NULL;
 
     /* Reset the fence register allocation. */
@@ -248,6 +250,7 @@ i830_free_3d_memory(ScrnInfoPtr pScrn)
 {
     I830Ptr pI830 = I830PTR(pScrn);
 
+#ifdef XF86_DRI
     i830_free_memory(pScrn, pI830->back_buffer);
     pI830->back_buffer = NULL;
     i830_free_memory(pScrn, pI830->third_buffer);
@@ -258,6 +261,7 @@ i830_free_3d_memory(ScrnInfoPtr pScrn)
     pI830->textures = NULL;
     i830_free_memory(pScrn, pI830->memory_manager);
     pI830->memory_manager = NULL;
+#endif
 }
 
 /**
@@ -691,6 +695,7 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
 	i830_describe_tiling(pScrn, verbosity, prefix, pI830->front_buffer,
 			     pI830->front_tiled);
     }
+#ifdef XF86DRI
     if (pI830->back_buffer != NULL) {
 	i830_describe_tiling(pScrn, verbosity, prefix, pI830->back_buffer,
 			     pI830->back_tiled);
@@ -703,6 +708,7 @@ i830_describe_allocations(ScrnInfoPtr pScrn, int verbosity, const char *prefix)
 	i830_describe_tiling(pScrn, verbosity, prefix, pI830->depth_buffer,
 			     pI830->depth_tiled);
     }
+#endif
 }
 
 static Bool
@@ -1330,7 +1336,6 @@ i830_allocate_3d_memory(ScrnInfoPtr pScrn)
 }
 #endif
 
-#ifdef XF86DRI
 /**
  * Sets up a fence area for the hardware.
  *
@@ -1529,7 +1534,6 @@ i830_set_fence(ScrnInfoPtr pScrn, int nr, unsigned int offset,
 
     pI830->fence[nr] = val;
 }
-#endif
 
 /**
  * Called at EnterVT to grab the AGP GART and bind our allocations.