Many fixes to mode_get, mode_set, clock limits, and register dumps on i855.
This should fix a number of issues with i855s, particularly with integrated LVDS panels.
This commit is contained in:
Eric Anholt
parent
3e8e75e5d8
commit
cd1d4b398e
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@ -299,6 +299,20 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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#define VCLK_DIVISOR_VGA0 0x6000
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#define VCLK_DIVISOR_VGA1 0x6004
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#define VCLK_POST_DIV 0x6010
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/** Selects a post divisor of 4 instead of 2. */
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# define VGA1_PD_P2_DIV_4 (1 << 15)
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/** Overrides the p2 post divisor field */
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# define VGA1_PD_P1_DIV_2 (1 << 13)
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# define VGA1_PD_P1_SHIFT 8
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/** P1 value is 2 greater than this field */
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# define VGA1_PD_P1_MASK (0x1f << 8)
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/** Selects a post divisor of 4 instead of 2. */
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# define VGA0_PD_P2_DIV_4 (1 << 7)
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/** Overrides the p2 post divisor field */
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# define VGA0_PD_P1_DIV_2 (1 << 5)
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# define VGA0_PD_P1_SHIFT 0
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/** P1 value is 2 greater than this field */
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# define VGA0_PD_P1_MASK (0x1f << 0)
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#define POST_DIV_SELECT 0x70
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#define POST_DIV_1 0x00
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@ -847,9 +861,18 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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# define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */
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# define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */
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# define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */
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/**
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* The i830 generation, in DAC/serial mode, defines p1 as two plus this
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* bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set.
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*/
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# define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000
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/**
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* The i830 generation, in LVDS mode, defines P1 as the bit number set within
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* this field (only one bit may be set).
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*/
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# define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000
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# define DPLL_FPA01_P1_POST_DIV_SHIFT 16
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# define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */
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# define DPLL_FPA01_P1_POS_DIV_MASK_I830 0x001f0000 /* i830 */
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# define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */
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# define PLL_REF_INPUT_DREFCLK (0 << 13)
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# define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */
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@ -102,6 +102,28 @@ DEBUGSTRING(i830_debug_fp)
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((val & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT));
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}
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DEBUGSTRING(i830_debug_vga_pd)
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{
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int vga0_p1, vga0_p2, vga1_p1, vga1_p2;
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/* XXX: i9xx version */
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if (val & VGA0_PD_P1_DIV_2)
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vga0_p1 = 2;
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else
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vga0_p1 = ((val & VGA0_PD_P1_MASK) >> VGA0_PD_P1_SHIFT) + 2;
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vga0_p2 = (val & VGA0_PD_P2_DIV_4) ? 4 : 2;
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if (val & VGA1_PD_P1_DIV_2)
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vga1_p1 = 2;
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else
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vga1_p1 = ((val & VGA1_PD_P1_MASK) >> VGA1_PD_P1_SHIFT) + 2;
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vga1_p2 = (val & VGA1_PD_P2_DIV_4) ? 4 : 2;
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return XNFprintf("vga0 p1 = %d, p2 = %d, vga1 p1 = %d, p2 = %d",
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vga0_p1, vga0_p2, vga1_p1, vga1_p2);
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}
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DEBUGSTRING(i830_debug_pp_status)
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{
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char *status = val & PP_ON ? "on" : "off";
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@ -140,18 +162,44 @@ DEBUGSTRING(i830_debug_dpll)
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char sdvoextra[20];
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int p1, p2 = 0;
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p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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switch (val & DPLL_MODE_MASK) {
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case DPLLB_MODE_DAC_SERIAL:
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mode = "dac/serial";
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p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
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break;
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case DPLLB_MODE_LVDS:
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mode = "LVDS";
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p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
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break;
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if (IS_I9XX(pI830)) {
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p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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switch (val & DPLL_MODE_MASK) {
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case DPLLB_MODE_DAC_SERIAL:
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mode = "DAC/serial";
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p2 = val & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
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break;
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case DPLLB_MODE_LVDS:
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mode = "LVDS";
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p2 = val & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
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break;
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}
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} else {
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Bool is_lvds = (INREG(LVDS) & LVDS_PORT_EN) && (reg == DPLL_B);
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if (val & PLL_P2_DIVIDE_BY_4)
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p2 = 4;
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else
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p2 = 2;
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if (is_lvds) {
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mode = "LVDS";
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/* Map the bit number set from (1, 6) to (-1, 4). */
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p1 = ffs((val & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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} else {
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mode = "DAC/serial";
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if (val & PLL_P1_DIVIDE_BY_TWO) {
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p1 = 2;
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} else {
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/* Map the number in the field to (1, 31) */
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p1 = ((val & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
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}
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}
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}
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switch (val & PLL_REF_INPUT_MASK) {
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case PLL_REF_INPUT_DREFCLK:
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clock = "default";
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@ -162,7 +210,12 @@ DEBUGSTRING(i830_debug_dpll)
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case PLL_REF_INPUT_TVCLKINBC:
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clock = "TV B/C";
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break;
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case PLLB_REF_INPUT_SPREADSPECTRUMIN:
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if (reg == DPLL_B)
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clock = "spread spectrum";
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break;
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}
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if (IS_I945G(pI830) || IS_I945GM(pI830)) {
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sprintf(sdvoextra, ", SDVO mult %d",
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(int)((val & SDVO_MULTIPLIER_MASK) >>
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@ -171,9 +224,9 @@ DEBUGSTRING(i830_debug_dpll)
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sdvoextra[0] = '\0';
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}
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return XNFprintf("%s, %s%s, %s mode, %s clock, p1 = %d, "
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return XNFprintf("%s, %s%s, %s clock, %s mode, p1 = %d, "
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"p2 = %d%s%s",
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enabled, dvomode, vgamode, mode, clock, p1, p2,
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enabled, dvomode, vgamode, clock, mode, p1, p2,
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fpextra, sdvoextra);
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}
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@ -233,9 +286,9 @@ static struct i830SnapshotRec {
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char *(*debug_output)(I830Ptr pI830, int reg, CARD32 val);
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CARD32 val;
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} i830_snapshot[] = {
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DEFINEREG(VCLK_DIVISOR_VGA0),
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DEFINEREG(VCLK_DIVISOR_VGA1),
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DEFINEREG(VCLK_POST_DIV),
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DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
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DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
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DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),
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DEFINEREG2(DPLL_TEST, i830_debug_dpll_test),
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DEFINEREG(D_STATE),
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DEFINEREG(DSPCLK_GATE_D),
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@ -85,10 +85,15 @@ typedef struct {
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#define I8XX_M2_MAX 16
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#define I8XX_P_MIN 4
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#define I8XX_P_MAX 128
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/* LVDS p1 value can go from 1 to 6, while DAC goes from 2 to 33. These
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* values below get 2 added in the clock calculations.
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*/
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#define I8XX_P1_MIN 0
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#define I8XX_P1_MAX 30
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#define I8XX_P2_SLOW 1
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#define I8XX_P2_FAST 0
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#define I8XX_P1_MAX 31
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#define I8XX_P1_LVDS_MIN -1
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#define I8XX_P1_LVDS_MAX 4
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#define I8XX_P2_SLOW 1 /* this is a bit shift amount */
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#define I8XX_P2_FAST 0 /* this is a bit shift amount */
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#define I8XX_P2_SLOW_LIMIT 165000
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#define I9XX_DOT_MIN 20000
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@ -116,12 +121,13 @@ typedef struct {
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#define I9XX_P2_LVDS_FAST 7
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#define I9XX_P2_LVDS_SLOW_LIMIT 112000
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#define INTEL_LIMIT_I8XX 0
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#define INTEL_LIMIT_I9XX_SDVO_DAC 1
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#define INTEL_LIMIT_I9XX_LVDS 2
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#define INTEL_LIMIT_I8XX_DVO_DAC 0
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#define INTEL_LIMIT_I8XX_LVDS 1
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#define INTEL_LIMIT_I9XX_SDVO_DAC 2
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#define INTEL_LIMIT_I9XX_LVDS 3
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static const intel_limit_t intel_limits[] = {
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{
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{ /* INTEL_LIMIT_I8XX_DVO_DAC */
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.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
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.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
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.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
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@ -133,7 +139,19 @@ static const intel_limit_t intel_limits[] = {
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.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
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.p2_slow = I8XX_P2_SLOW, .p2_fast = I8XX_P2_FAST },
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},
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{
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{ /* INTEL_LIMIT_I8XX_LVDS */
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.dot = { .min = I8XX_DOT_MIN, .max = I8XX_DOT_MAX },
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.vco = { .min = I8XX_VCO_MIN, .max = I8XX_VCO_MAX },
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.n = { .min = I8XX_N_MIN, .max = I8XX_N_MAX },
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.m = { .min = I8XX_M_MIN, .max = I8XX_M_MAX },
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.m1 = { .min = I8XX_M1_MIN, .max = I8XX_M1_MAX },
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.m2 = { .min = I8XX_M2_MIN, .max = I8XX_M2_MAX },
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.p = { .min = I8XX_P_MIN, .max = I8XX_P_MAX },
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.p1 = { .min = I8XX_P1_LVDS_MIN, .max = I8XX_P1_LVDS_MAX },
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.p2 = { .dot_limit = I8XX_P2_SLOW_LIMIT,
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.p2_slow = I8XX_P2_FAST, .p2_fast = I8XX_P2_FAST },
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},
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{ /* INTEL_LIMIT_I9XX_SDVO_DAC */
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.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
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.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
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.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
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@ -145,7 +163,7 @@ static const intel_limit_t intel_limits[] = {
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.p2 = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
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.p2_slow = I9XX_P2_SDVO_DAC_SLOW, .p2_fast = I9XX_P2_SDVO_DAC_FAST },
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},
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{
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{ /* INTEL_LIMIT_I9XX_LVDS */
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.dot = { .min = I9XX_DOT_MIN, .max = I9XX_DOT_MAX },
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.vco = { .min = I9XX_VCO_MIN, .max = I9XX_VCO_MAX },
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.n = { .min = I9XX_N_MIN, .max = I9XX_N_MAX },
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@ -168,15 +186,18 @@ static const intel_limit_t *intel_limit (xf86CrtcPtr crtc)
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I830Ptr pI830 = I830PTR(pScrn);
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const intel_limit_t *limit;
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if (IS_I9XX(pI830))
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{
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if (IS_I9XX(pI830)) {
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if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
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limit = &intel_limits[INTEL_LIMIT_I9XX_LVDS];
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else
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limit = &intel_limits[INTEL_LIMIT_I9XX_SDVO_DAC];
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} else {
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if (i830PipeHasType (crtc, I830_OUTPUT_LVDS))
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limit = &intel_limits[INTEL_LIMIT_I8XX_LVDS];
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else
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limit = &intel_limits[INTEL_LIMIT_I8XX_DVO_DAC];
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}
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else
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limit = &intel_limits[INTEL_LIMIT_I8XX];
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return limit;
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}
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@ -792,7 +813,15 @@ i830_crtc_mode_set(xf86CrtcPtr crtc, DisplayModePtr mode,
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if (IS_I965G(pI830))
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dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
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} else {
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dpll |= clock.p1 << 16;
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if (is_lvds) {
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/* map (-1 to 4) to ((1 << 0) to (1 << 5)). */
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dpll |= (1 << (clock.p1 + 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
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} else {
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if (clock.p1 == 0)
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dpll |= PLL_P1_DIVIDE_BY_TWO;
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else
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dpll |= clock.p1 << DPLL_FPA01_P1_POST_DIV_SHIFT;
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}
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dpll |= clock.p2 << 23;
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}
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@ -1250,35 +1279,59 @@ i830_crtc_clock_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
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clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
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clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
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clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
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clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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switch (dpll & DPLL_MODE_MASK) {
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case DPLLB_MODE_DAC_SERIAL:
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clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
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break;
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case DPLLB_MODE_LVDS:
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clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
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break;
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default:
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xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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"Unknown DPLL mode %08x in programmed mode\n",
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(int)(dpll & DPLL_MODE_MASK));
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return 0;
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}
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/* XXX: Handle the 100Mhz refclk */
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if (IS_I9XX(pI830))
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i9xx_clock(96000, &clock);
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else
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i9xx_clock(48000, &clock);
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if (IS_I9XX(pI830)) {
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clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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if (!i830PllIsValid(crtc, &clock)) {
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xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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"Bad clock found programmed in pipe %c\n",
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pipe == 0 ? 'A' : 'B');
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i830PrintPll("", &clock);
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switch (dpll & DPLL_MODE_MASK) {
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case DPLLB_MODE_DAC_SERIAL:
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clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ? 5 : 10;
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break;
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case DPLLB_MODE_LVDS:
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clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ? 7 : 14;
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break;
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default:
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xf86DrvMsg(pScrn->scrnIndex, X_WARNING,
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"Unknown DPLL mode %08x in programmed mode\n",
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(int)(dpll & DPLL_MODE_MASK));
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return 0;
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}
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/* XXX: Handle the 100Mhz refclk */
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i9xx_clock(96000, &clock);
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} else {
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Bool is_lvds = (pipe == 1) && (INREG(LVDS) & LVDS_PORT_EN);
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if (is_lvds) {
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/* Map the bit number set from (1, 6) to (-1, 4). */
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clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT) - 2;
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clock.p2 = 0;
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} else {
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if (dpll & PLL_P1_DIVIDE_BY_TWO) {
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clock.p1 = 0;
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} else {
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/* Map the number in the field to (1, 31) */
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clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
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DPLL_FPA01_P1_POST_DIV_SHIFT);
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}
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if (dpll & PLL_P2_DIVIDE_BY_4)
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clock.p2 = 1;
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else
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clock.p2 = 0;
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}
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/* XXX: Deal with other refclocks */
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i8xx_clock(48000, &clock);
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}
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/* XXX: It would be nice to validate the clocks, but we can't reuse
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* i830PllIsValid() because it relies on the xf86_config output
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* configuration being accurate, which it isn't necessarily.
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*/
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if (0)
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i830PrintPll("probed", &clock);
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return clock.dot;
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}
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@ -1299,8 +1352,6 @@ i830_crtc_mode_get(ScrnInfoPtr pScrn, xf86CrtcPtr crtc)
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if (mode == NULL)
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return NULL;
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memset(mode, 0, sizeof(*mode));
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mode->Clock = i830_crtc_clock_get(pScrn, crtc);
|
||||
mode->HDisplay = (htot & 0xffff) + 1;
|
||||
mode->HTotal = ((htot & 0xffff0000) >> 16) + 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue