Enumerate all possible wm_state objects
We have a collection of wm_state objects for each ps kernel, (one for each combination of src and mask extend and repeat values). Thanks to Dave Airlie for noticing an errant write through a wild wm_state pointer in an early version of this commit. (cherry picked from 7763706a93d3021907273f9b330750ba110e2fc3 commit) This cherry-pick required more reformatting than most, due to the projective texturing merge.
This commit is contained in:
Carl Worth
Eric Anholt
parent
2293a3677d
commit
d3138d9ff0
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@ -277,15 +277,13 @@ static struct brw_surface_state *mask_surf_state, mask_surf_state_local;
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static struct brw_vs_unit_state *vs_state, vs_state_local;
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static struct brw_sf_unit_state *sf_state, sf_state_local;
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static struct brw_wm_unit_state *wm_state, wm_state_local;
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static uint32_t *binding_table;
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static int binding_table_entries;
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static int dest_surf_offset, src_surf_offset, mask_surf_offset;
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static int vs_offset;
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static int sf_offset, wm_offset, cc_offset, vb_offset;
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static int wm_scratch_offset;
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static int sf_offset, cc_offset, vb_offset;
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static int binding_table_offset;
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static int next_offset, total_state_size;
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static char *state_base;
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@ -420,6 +418,12 @@ static const uint32_t ps_kernel_masknoca_projective_static [][4] = {
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#define KERNEL_DECL(template) \
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uint32_t template [((sizeof (template ## _static) + 63) & ~63) / 16][4];
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#define WM_STATE_DECL(kernel) \
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struct brw_wm_unit_state wm_state_ ## kernel[SAMPLER_STATE_FILTER_COUNT] \
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[SAMPLER_STATE_EXTEND_COUNT] \
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[SAMPLER_STATE_FILTER_COUNT] \
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[SAMPLER_STATE_EXTEND_COUNT]
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/* Many of the fields in the state structure must be aligned to a
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* 64-byte boundary, (or a 32-byte boundary, but 64 is good enough for
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* those too).
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@ -467,6 +471,17 @@ typedef struct _gen4_state {
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KERNEL_DECL (ps_kernel_masknoca_affine);
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KERNEL_DECL (ps_kernel_masknoca_projective);
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uint8_t wm_scratch[128 * PS_MAX_THREADS];
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WM_STATE_DECL (nomask_affine);
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WM_STATE_DECL (nomask_projective);
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WM_STATE_DECL (maskca_affine);
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WM_STATE_DECL (maskca_projective);
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WM_STATE_DECL (maskca_srcalpha_affine);
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WM_STATE_DECL (maskca_srcalpha_projective);
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WM_STATE_DECL (masknoca_affine);
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WM_STATE_DECL (masknoca_projective);
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/* Index by [src_filter][src_extend][mask_filter][mask_extend] */
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struct brw_sampler_state sampler_state[SAMPLER_STATE_FILTER_COUNT]
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[SAMPLER_STATE_EXTEND_COUNT]
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@ -564,6 +579,55 @@ cc_state_init (struct brw_cc_unit_state *cc_state,
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cc_state->cc6.dest_blend_factor = dst_blend;
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}
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static void
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wm_state_init (struct brw_wm_unit_state *wm_state,
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Bool has_mask,
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int scratch_offset,
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int kernel_offset,
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int sampler_state_offset)
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{
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memset(wm_state, 0, sizeof (*wm_state));
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wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
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wm_state->thread1.single_program_flow = 0;
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assert((scratch_offset & 1023) == 0);
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wm_state->thread2.scratch_space_base_pointer = scratch_offset >> 10;
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wm_state->thread2.per_thread_scratch_space = PS_SCRATCH_SPACE_LOG;
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wm_state->thread3.const_urb_entry_read_length = 0;
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wm_state->thread3.const_urb_entry_read_offset = 0;
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wm_state->thread3.urb_entry_read_offset = 0;
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/* wm kernel use urb from 3, see wm_program in compiler module */
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wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
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wm_state->wm4.stats_enable = 1; /* statistic */
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assert((sampler_state_offset & 31) == 0);
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wm_state->wm4.sampler_state_pointer = sampler_state_offset >> 5;
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wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
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wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
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wm_state->wm5.transposed_urb_read = 0;
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wm_state->wm5.thread_dispatch_enable = 1;
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/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
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* start point
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*/
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wm_state->wm5.enable_16_pix = 1;
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wm_state->wm5.enable_8_pix = 0;
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wm_state->wm5.early_depth_test = 1;
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assert((kernel_offset & 63) == 0);
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wm_state->thread0.kernel_start_pointer = kernel_offset >> 6;
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/* Each pair of attributes (src/mask coords) is two URB entries */
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if (has_mask) {
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wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
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wm_state->thread3.urb_entry_read_length = 4;
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} else {
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wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
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wm_state->thread3.urb_entry_read_length = 2;
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}
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}
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/**
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* Called at EnterVT to fill in our state buffer with any static information.
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*/
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@ -586,6 +650,7 @@ gen4_state_init (gen4_state_t *state, uint32_t state_base_offset)
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KERNEL_COPY (ps_kernel_maskca_srcalpha_projective);
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KERNEL_COPY (ps_kernel_masknoca_affine);
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KERNEL_COPY (ps_kernel_masknoca_projective);
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#undef KERNEL_COPY
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memset(&state->sampler_default_color, 0,
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sizeof(state->sampler_default_color));
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@ -623,7 +688,34 @@ gen4_state_init (gen4_state_t *state, uint32_t state_base_offset)
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}
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}
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#undef KERNEL_COPY
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#define SETUP_WM_STATE(kernel, has_mask) \
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wm_state_init(&state->wm_state_ ## kernel [i][j][k][l], \
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has_mask, \
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state_base_offset + offsetof(gen4_state_t, \
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wm_scratch), \
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state_base_offset + offsetof(gen4_state_t, \
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ps_kernel_ ## kernel), \
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state_base_offset + offsetof(gen4_state_t, \
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sampler_state[i][j][k][l]));
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for (i = 0; i < SAMPLER_STATE_FILTER_COUNT; i++) {
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for (j = 0; j < SAMPLER_STATE_EXTEND_COUNT; j++) {
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for (k = 0; k < SAMPLER_STATE_FILTER_COUNT; k++) {
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for (l = 0; l < SAMPLER_STATE_EXTEND_COUNT; l++) {
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SETUP_WM_STATE (nomask_affine, FALSE);
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SETUP_WM_STATE (nomask_projective, FALSE);
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SETUP_WM_STATE (maskca_affine, TRUE);
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SETUP_WM_STATE (maskca_projective, TRUE);
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SETUP_WM_STATE (maskca_srcalpha_affine, TRUE);
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SETUP_WM_STATE (maskca_srcalpha_projective, TRUE);
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SETUP_WM_STATE (masknoca_affine, TRUE);
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SETUP_WM_STATE (masknoca_projective, TRUE);
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}
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}
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}
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}
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#undef SETUP_WM_STATE
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}
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static uint32_t
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@ -737,12 +829,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
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sf_offset = ALIGN(next_offset, 32);
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next_offset = sf_offset + sizeof(*sf_state);
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wm_offset = ALIGN(next_offset, 32);
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next_offset = wm_offset + sizeof(*wm_state);
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wm_scratch_offset = ALIGN(next_offset, 1024);
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next_offset = wm_scratch_offset + PS_SCRATCH_SPACE * PS_MAX_THREADS;
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/* Align VB to native size of elements, for safety */
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vb_offset = ALIGN(next_offset, 32);
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next_offset = vb_offset + vb_size;
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@ -982,108 +1068,6 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
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sf_state = (void *)(state_base + sf_offset);
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memcpy (sf_state, &sf_state_local, sizeof (sf_state_local));
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/* Set up the PS kernel (dispatched by WM) */
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wm_state = &wm_state_local;
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memset(wm_state, 0, sizeof (*wm_state));
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if (pMask) {
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if (pMaskPicture->componentAlpha &&
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PICT_FORMAT_RGB(pMaskPicture->format))
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{
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if (i965_blend_op[op].src_alpha) {
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if (is_affine) {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_maskca_srcalpha_affine)) >> 6;
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} else {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_maskca_srcalpha_projective)) >> 6;
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}
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} else {
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if (is_affine) {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_maskca_affine)) >> 6;
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} else {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_maskca_projective)) >> 6;
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}
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}
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} else {
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if (is_affine) {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_masknoca_affine)) >> 6;
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} else {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_masknoca_projective)) >> 6;
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}
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}
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} else {
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if (is_affine) {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_nomask_affine)) >> 6;
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} else {
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wm_state->thread0.kernel_start_pointer =
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(state_base_offset +
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offsetof(gen4_state_t,
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ps_kernel_nomask_projective)) >> 6;
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}
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}
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wm_state->thread0.grf_reg_count = BRW_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
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wm_state->thread1.single_program_flow = 0;
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if (!pMask)
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wm_state->thread1.binding_table_entry_count = 2; /* 1 tex and fb */
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else
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wm_state->thread1.binding_table_entry_count = 3; /* 2 tex and fb */
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wm_state->thread2.scratch_space_base_pointer = (state_base_offset +
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wm_scratch_offset)>>10;
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wm_state->thread2.per_thread_scratch_space = PS_SCRATCH_SPACE_LOG;
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wm_state->thread3.const_urb_entry_read_length = 0;
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wm_state->thread3.const_urb_entry_read_offset = 0;
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/* Each pair of attributes (src/mask coords) is one URB entry */
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if (pMask)
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wm_state->thread3.urb_entry_read_length = 4;
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else
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wm_state->thread3.urb_entry_read_length = 2;
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wm_state->thread3.urb_entry_read_offset = 0;
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/* wm kernel use urb from 3, see wm_program in compiler module */
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wm_state->thread3.dispatch_grf_start_reg = 3; /* must match kernel */
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wm_state->wm4.stats_enable = 1; /* statistic */
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wm_state->wm4.sampler_state_pointer = (state_base_offset +
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offsetof(gen4_state_t,
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sampler_state
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[src_filter]
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[src_extend]
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[mask_filter]
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[mask_extend][0])) >> 5;
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wm_state->wm4.sampler_count = 1; /* 1-4 samplers used */
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wm_state->wm5.max_threads = PS_MAX_THREADS - 1;
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wm_state->wm5.transposed_urb_read = 0;
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wm_state->wm5.thread_dispatch_enable = 1;
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/* just use 16-pixel dispatch (4 subspans), don't need to change kernel
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* start point
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*/
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wm_state->wm5.enable_16_pix = 1;
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wm_state->wm5.enable_8_pix = 0;
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wm_state->wm5.early_depth_test = 1;
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wm_state = (void *)(state_base + wm_offset);
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memcpy (wm_state, &wm_state_local, sizeof (wm_state_local));
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/* Begin the long sequence of commands needed to set up the 3D
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* rendering pipe
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*/
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@ -1166,7 +1150,49 @@ i965_prepare_composite(int op, PicturePtr pSrcPicture,
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OUT_BATCH(BRW_GS_DISABLE); /* disable GS, resulting in passthrough */
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OUT_BATCH(BRW_CLIP_DISABLE); /* disable CLIP, resulting in passthrough */
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OUT_BATCH(state_base_offset + sf_offset); /* 32 byte aligned */
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OUT_BATCH(state_base_offset + wm_offset); /* 32 byte aligned */
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/* Shorthand for long array lookup */
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#define OUT_WM_KERNEL(kernel) do { \
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uint32_t offset = state_base_offset + \
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offsetof(gen4_state_t, \
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wm_state_ ## kernel \
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[src_filter] \
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[src_extend] \
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[mask_filter] \
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[mask_extend]); \
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assert((offset & 31) == 0); \
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OUT_BATCH(offset); \
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} while (0)
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if (pMask) {
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if (pMaskPicture->componentAlpha &&
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PICT_FORMAT_RGB(pMaskPicture->format))
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{
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if (i965_blend_op[op].src_alpha) {
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if (is_affine)
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OUT_WM_KERNEL(maskca_srcalpha_affine);
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else
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OUT_WM_KERNEL(maskca_srcalpha_projective);
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} else {
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if (is_affine)
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OUT_WM_KERNEL(maskca_affine);
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else
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OUT_WM_KERNEL(maskca_projective);
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}
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} else {
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if (is_affine)
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OUT_WM_KERNEL(masknoca_affine);
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else
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OUT_WM_KERNEL(masknoca_projective);
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}
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} else {
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if (is_affine)
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OUT_WM_KERNEL(nomask_affine);
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else
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OUT_WM_KERNEL(nomask_projective);
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}
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#undef OUT_WM_KERNEL
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/* 64 byte aligned */
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OUT_BATCH(state_base_offset +
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offsetof(gen4_state_t, cc_state[src_blend][dst_blend]));
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