From d36cae801f1dcb06d4f93f2f27cc9b9de73e89c9 Mon Sep 17 00:00:00 2001 From: Chris Wilson Date: Tue, 1 Jan 2013 21:03:06 +0000 Subject: [PATCH] sna/gen4+: Tidy special handling of 2s2s vertex elements Signed-off-by: Chris Wilson --- src/sna/gen4_render.c | 71 +++++++++++-------------------------------- src/sna/gen5_render.c | 60 +++++++++--------------------------- src/sna/gen6_render.c | 57 +++++++++------------------------- src/sna/gen7_render.c | 56 +++++++++------------------------- 4 files changed, 60 insertions(+), 184 deletions(-) diff --git a/src/sna/gen4_render.c b/src/sna/gen4_render.c index 405eb7d7..893c5ee0 100644 --- a/src/sna/gen4_render.c +++ b/src/sna/gen4_render.c @@ -876,51 +876,12 @@ gen4_emit_vertex_elements(struct sna *sna, */ struct gen4_render_state *render = &sna->render_state.gen4; uint32_t src_format, dw; - int src_offset, dst_offset; int id = op->u.gen4.ve_id; if (render->ve_id == id) return; render->ve_id = id; - if (id == VERTEX_2s2s) { - DBG(("%s: setup COPY\n", __FUNCTION__)); - assert(op->floats_per_rect == 6); - - OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + 2)) + 1 - 2)); - - /* x,y */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT | - 4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); - - /* s,t */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 4 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT | - 8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); - - /* magic */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN4_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT | - 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); - return; - } - /* The VUE layout * dword 0-3: position (x, y, 1.0, 1.0), * dword 4-7: texture coordinate 0 (u0, v0, w0, 1.0) @@ -937,23 +898,26 @@ gen4_emit_vertex_elements(struct sna *sna, VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT | (1*4) << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); - src_offset = 4; - dst_offset = 8; /* u0, v0, w0 */ /* u0, v0, w0 */ - DBG(("%s: first channel %d floats, offset=%d\n", __FUNCTION__, - id & 3, src_offset)); + DBG(("%s: first channel %d floats, offset=4b\n", __FUNCTION__, id & 3)); dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; switch (id & 3) { + default: + assert(0); + case 0: + src_format = GEN4_SURFACEFORMAT_R16G16_SSCALED; + dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; + dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; + dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; + break; case 1: src_format = GEN4_SURFACEFORMAT_R32_FLOAT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; break; - default: - assert(0); case 2: src_format = GEN4_SURFACEFORMAT_R32G32_FLOAT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; @@ -969,17 +933,16 @@ gen4_emit_vertex_elements(struct sna *sna, } OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | src_format << VE0_FORMAT_SHIFT | - src_offset << VE0_OFFSET_SHIFT); - OUT_BATCH(dw | dst_offset << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); - src_offset += (id & 3) * sizeof(float); - dst_offset += 4; + 4 << VE0_OFFSET_SHIFT); + OUT_BATCH(dw | 8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); /* u1, v1, w1 */ if (id >> 2) { - DBG(("%s: second channel %d floats, offset=%d\n", __FUNCTION__, - (id >> 2) & 3, src_offset)); + unsigned src_offset = 4 + ((id & 3) ?: 1) * sizeof(float); + DBG(("%s: second channel %d floats, offset=%db\n", __FUNCTION__, + id >> 2, src_offset)); dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; - switch ((id >> 2) & 3) { + switch (id >> 2) { case 1: src_format = GEN4_SURFACEFORMAT_R32_FLOAT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; @@ -1004,7 +967,7 @@ gen4_emit_vertex_elements(struct sna *sna, OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | src_format << VE0_FORMAT_SHIFT | src_offset << VE0_OFFSET_SHIFT); - OUT_BATCH(dw | dst_offset << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); + OUT_BATCH(dw | 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); } else { OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | GEN4_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | @@ -1013,7 +976,7 @@ gen4_emit_vertex_elements(struct sna *sna, VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT | - dst_offset << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); + 12 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT); } } diff --git a/src/sna/gen5_render.c b/src/sna/gen5_render.c index 5be56ddc..15f5f58b 100644 --- a/src/sna/gen5_render.c +++ b/src/sna/gen5_render.c @@ -871,7 +871,6 @@ gen5_emit_vertex_elements(struct sna *sna, int id = op->u.gen5.ve_id; bool has_mask = id >> 2; uint32_t format, dw; - int offset; if (!DBG_NO_STATE_CACHE && render->ve_id == id) return; @@ -879,40 +878,6 @@ gen5_emit_vertex_elements(struct sna *sna, DBG(("%s: changing %d -> %d\n", __FUNCTION__, render->ve_id, id)); render->ve_id = id; - if (id == VERTEX_2s2s) { - DBG(("%s: setup COPY\n", __FUNCTION__)); - assert(op->floats_per_rect == 6); - - OUT_BATCH(GEN5_3DSTATE_VERTEX_ELEMENTS | ((2 * (1 + 2)) + 1 - 2)); - - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN5_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); - - /* x,y */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - - /* s,t */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 4 << VE0_OFFSET_SHIFT); - OUT_BATCH(VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - return; - } - /* The VUE layout * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) * dword 4-7: position (x, y, 1.0, 1.0), @@ -940,21 +905,26 @@ gen5_emit_vertex_elements(struct sna *sna, VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT | VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - offset = 4; /* u0, v0, w0 */ - DBG(("%s: id=%d, first channel %d floats, offset=%d\n", __FUNCTION__, - id, id & 3, offset)); + DBG(("%s: id=%d, first channel %d floats, offset=4b\n", __FUNCTION__, + id, id & 3)); dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; switch (id & 3) { + default: + assert(0); + case 0: + format = GEN5_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT; + dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; + dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; + dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; + break; case 1: format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; dw |= VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; dw |= VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT; break; - default: - assert(0); case 2: format = GEN5_SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; @@ -969,16 +939,16 @@ gen5_emit_vertex_elements(struct sna *sna, break; } OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - format | offset << VE0_OFFSET_SHIFT); + format | 4 << VE0_OFFSET_SHIFT); OUT_BATCH(dw); /* u1, v1, w1 */ if (has_mask) { - offset += (id & 3) * sizeof(float); - DBG(("%s: id=%x, second channel %d floats, offset=%d\n", __FUNCTION__, - id, (id >> 2) & 3, offset)); + unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float); + DBG(("%s: id=%x, second channel %d floats, offset=%db\n", __FUNCTION__, + id, id >> 2, offset)); dw = VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; - switch ((id >> 2) & 3) { + switch (id >> 2) { case 1: format = GEN5_SURFACEFORMAT_R32_FLOAT << VE0_FORMAT_SHIFT; dw |= VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; diff --git a/src/sna/gen6_render.c b/src/sna/gen6_render.c index 142fc049..d484ddeb 100644 --- a/src/sna/gen6_render.c +++ b/src/sna/gen6_render.c @@ -731,7 +731,7 @@ gen6_emit_vertex_elements(struct sna *sna, * texture coordinate 1 if (has_mask is true): same as above */ struct gen6_render_state *render = &sna->render_state.gen6; - uint32_t src_format, dw, offset; + uint32_t src_format, dw; int id = GEN6_VERTEX(op->u.gen6.flags); bool has_mask; @@ -741,40 +741,6 @@ gen6_emit_vertex_elements(struct sna *sna, return; render->ve_id = id; - if (id == VERTEX_2s2s) { - DBG(("%s: setup COPY\n", __FUNCTION__)); - - OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | - ((2 * (1 + 2)) + 1 - 2)); - - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN6_SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT); - - /* x,y */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 0 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - - /* u0, v0, w0 */ - OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | - GEN6_SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT | - 4 << VE0_OFFSET_SHIFT); - OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT | - GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | - GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | - GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - return; - } - /* The VUE layout * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) * dword 4-7: position (x, y, 1.0, 1.0), @@ -803,20 +769,25 @@ gen6_emit_vertex_elements(struct sna *sna, GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT | GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT | GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT); - offset = 4; /* u0, v0, w0 */ - DBG(("%s: first channel %d floats, offset=%d\n", __FUNCTION__, id & 3, offset)); + DBG(("%s: first channel %d floats, offset=4b\n", __FUNCTION__, id & 3)); dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; switch (id & 3) { + default: + assert(0); + case 0: + src_format = GEN6_SURFACEFORMAT_R16G16_SSCALED; + dw |= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; + dw |= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT; + dw |= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT; + break; case 1: src_format = GEN6_SURFACEFORMAT_R32_FLOAT; dw |= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; dw |= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT; dw |= GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT; break; - default: - assert(0); case 2: src_format = GEN6_SURFACEFORMAT_R32G32_FLOAT; dw |= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; @@ -832,15 +803,15 @@ gen6_emit_vertex_elements(struct sna *sna, } OUT_BATCH(id << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID | src_format << VE0_FORMAT_SHIFT | - offset << VE0_OFFSET_SHIFT); + 4 << VE0_OFFSET_SHIFT); OUT_BATCH(dw); - offset += (id & 3) * sizeof(float); /* u1, v1, w1 */ if (has_mask) { - DBG(("%s: second channel %d floats, offset=%d\n", __FUNCTION__, (id >> 2) & 3, offset)); + unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float); + DBG(("%s: second channel %d floats, offset=%db\n", __FUNCTION__, id >> 2, offset)); dw = GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT; - switch ((id >> 2) & 3) { + switch (id >> 2) { case 1: src_format = GEN6_SURFACEFORMAT_R32_FLOAT; dw |= GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT; diff --git a/src/sna/gen7_render.c b/src/sna/gen7_render.c index ca688d4e..8a1cfff5 100644 --- a/src/sna/gen7_render.c +++ b/src/sna/gen7_render.c @@ -862,7 +862,7 @@ gen7_emit_vertex_elements(struct sna *sna, * texture coordinate 1 if (has_mask is true): same as above */ struct gen7_render_state *render = &sna->render_state.gen7; - uint32_t src_format, dw, offset; + uint32_t src_format, dw; int id = GEN7_VERTEX(op->u.gen7.flags); bool has_mask; @@ -872,39 +872,6 @@ gen7_emit_vertex_elements(struct sna *sna, return; render->ve_id = id; - if (id == VERTEX_2s2s) { - DBG(("%s: setup COPY\n", __FUNCTION__)); - - OUT_BATCH(GEN7_3DSTATE_VERTEX_ELEMENTS | - ((2 * (1 + 2)) + 1 - 2)); - - OUT_BATCH(VERTEX_2s2s << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - GEN7_SURFACEFORMAT_R32G32B32A32_FLOAT << GEN7_VE0_FORMAT_SHIFT | - 0 << GEN7_VE0_OFFSET_SHIFT); - OUT_BATCH(GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_3_SHIFT); - - /* x,y */ - OUT_BATCH(VERTEX_2s2s << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT | - 0 << GEN7_VE0_OFFSET_SHIFT); /* offsets vb in bytes */ - OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT); - - OUT_BATCH(VERTEX_2s2s << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | - GEN7_SURFACEFORMAT_R16G16_SSCALED << GEN7_VE0_FORMAT_SHIFT | - 4 << GEN7_VE0_OFFSET_SHIFT); /* offset vb in bytes */ - OUT_BATCH(GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT | - GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT | - GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | - GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT); - return; - } - /* The VUE layout * dword 0-3: pad (0.0, 0.0, 0.0. 0.0) * dword 4-7: position (x, y, 1.0, 1.0), @@ -933,20 +900,25 @@ gen7_emit_vertex_elements(struct sna *sna, GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT | GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT | GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT); - offset = 4; /* u0, v0, w0 */ - DBG(("%s: first channel %d floats, offset=%d\n", __FUNCTION__, id & 3, offset)); + DBG(("%s: first channel %d floats, offset=4b\n", __FUNCTION__, id & 3)); dw = GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT; switch (id & 3) { + default: + assert(0); + case 0: + src_format = GEN7_SURFACEFORMAT_R16G16_SSCALED; + dw |= GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT; + dw |= GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_1_SHIFT; + dw |= GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT; + break; case 1: src_format = GEN7_SURFACEFORMAT_R32_FLOAT; dw |= GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT; dw |= GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_1_SHIFT; dw |= GEN7_VFCOMPONENT_STORE_0 << GEN7_VE1_VFCOMPONENT_2_SHIFT; break; - default: - assert(0); case 2: src_format = GEN7_SURFACEFORMAT_R32G32_FLOAT; dw |= GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT; @@ -962,15 +934,15 @@ gen7_emit_vertex_elements(struct sna *sna, } OUT_BATCH(id << GEN7_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN7_VE0_VALID | src_format << GEN7_VE0_FORMAT_SHIFT | - offset << GEN7_VE0_OFFSET_SHIFT); + 4 << GEN7_VE0_OFFSET_SHIFT); OUT_BATCH(dw); - offset += (id & 3) * sizeof(float); /* u1, v1, w1 */ if (has_mask) { - DBG(("%s: second channel %d floats, offset=%d\n", __FUNCTION__, (id >> 2) & 3, offset)); + unsigned offset = 4 + ((id & 3) ?: 1) * sizeof(float); + DBG(("%s: second channel %d floats, offset=%db\n", __FUNCTION__, id >> 2, offset)); dw = GEN7_VFCOMPONENT_STORE_1_FLT << GEN7_VE1_VFCOMPONENT_3_SHIFT; - switch ((id >> 2) & 3) { + switch (id >> 2) { case 1: src_format = GEN7_SURFACEFORMAT_R32_FLOAT; dw |= GEN7_VFCOMPONENT_STORE_SRC << GEN7_VE1_VFCOMPONENT_0_SHIFT;