From d51555fba4e57c059fd184c1e54822d7e5b62a2f Mon Sep 17 00:00:00 2001
From: Eric Anholt <eric@anholt.net>
Date: Fri, 10 Nov 2006 14:40:40 -0800
Subject: [PATCH] Fix clock range for single-channel LVDS.

---
 src/i830_display.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/src/i830_display.c b/src/i830_display.c
index 36036603..f661c4ed 100644
--- a/src/i830_display.c
+++ b/src/i830_display.c
@@ -189,7 +189,10 @@ i830FindBestPLL(ScrnInfoPtr pScrn, int pipe, int target, int refclk,
 	min_p1 = 1;
 	max_p1 = 8;
 	if (i830PipeHasType (pScrn, pipe, I830_OUTPUT_LVDS)) {
-	    if (target < 200000) /* XXX: Is this the right cutoff? */
+	    /* The single-channel range is 25-112Mhz, and dual-channel
+	     * is 80-224Mhz.  Prefer single channel as much as possible.
+	     */
+	    if (target < 112000)
 		p2 = 14;
 	    else
 		p2 = 7;