Add some MCHBAR registers for debugging tile swizzling issues.

This commit is contained in:
Eric Anholt 2008-08-31 14:27:29 -07:00
parent c7aaf0118b
commit da63b5adec
2 changed files with 56 additions and 0 deletions

View File

@ -113,6 +113,20 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
#define COLEXP_RESERVED 0x30
#define BITBLT_STATUS 0x01
#define CHDECMISC 0x10111
#define C0DRB0 0x10200
#define C0DRB1 0x10202
#define C0DRB2 0x10204
#define C0DRB3 0x10206
#define C0DRA01 0x10208
#define C0DRA23 0x1020a
#define C1DRB0 0x10600
#define C1DRB1 0x10602
#define C1DRB2 0x10604
#define C1DRB3 0x10606
#define C1DRA01 0x10608
#define C1DRA23 0x1060a
/* p375.
*/
#define DISPLAY_CNTL 0x70008

View File

@ -48,6 +48,32 @@
#define DEBUGSTRING(func) static char *func(I830Ptr pI830, int reg, \
uint32_t val)
DEBUGSTRING(i830_16bit_func)
{
return XNFprintf("0x%04x", (uint16_t)val);
}
DEBUGSTRING(i830_debug_chdecmisc)
{
char *enhmodesel = NULL;
switch ((val >> 5) & 3) {
case 1: enhmodesel = "XOR bank/rank"; break;
case 2: enhmodesel = "swap bank"; break;
case 3: enhmodesel = "XOR bank"; break;
case 0: enhmodesel = "none"; break;
}
return XNFprintf("%s, ch2 enh %sabled, ch1 enh %sabled, ch0 enh %sabled, "
"flex %sabled, ep %spresent",
enhmodesel,
(val & (1 << 4)) ? "en" : "dis",
(val & (1 << 3)) ? "en" : "dis",
(val & (1 << 2)) ? "en" : "dis",
(val & (1 << 1)) ? "en" : "dis",
(val & (1 << 0)) ? "" : "not ");
}
DEBUGSTRING(i830_debug_xyminus1)
{
return XNFprintf("%d, %d", (val & 0xffff) + 1,
@ -481,6 +507,8 @@ DEBUGSTRING(i810_debug_fence_new)
#define DEFINEREG(reg) \
{ reg, #reg, NULL, 0 }
#define DEFINEREG_16BIT(reg) \
{ reg, #reg, i830_16bit_func, 0 }
#define DEFINEREG2(reg, func) \
{ reg, #reg, func, 0 }
@ -490,6 +518,20 @@ static struct i830SnapshotRec {
char *(*debug_output)(I830Ptr pI830, int reg, uint32_t val);
uint32_t val;
} i830_snapshot[] = {
DEFINEREG2(CHDECMISC, i830_debug_chdecmisc),
DEFINEREG_16BIT(C0DRB0),
DEFINEREG_16BIT(C0DRB1),
DEFINEREG_16BIT(C0DRB2),
DEFINEREG_16BIT(C0DRB3),
DEFINEREG_16BIT(C1DRB0),
DEFINEREG_16BIT(C1DRB1),
DEFINEREG_16BIT(C1DRB2),
DEFINEREG_16BIT(C1DRB3),
DEFINEREG_16BIT(C0DRA01),
DEFINEREG_16BIT(C0DRA23),
DEFINEREG_16BIT(C1DRA01),
DEFINEREG_16BIT(C1DRA23),
DEFINEREG2(VCLK_DIVISOR_VGA0, i830_debug_fp),
DEFINEREG2(VCLK_DIVISOR_VGA1, i830_debug_fp),
DEFINEREG2(VCLK_POST_DIV, i830_debug_vga_pd),